ATE397247T1 - Mikroprozessor und verfahren zur anweisungsausrichtung - Google Patents
Mikroprozessor und verfahren zur anweisungsausrichtungInfo
- Publication number
- ATE397247T1 ATE397247T1 AT05738590T AT05738590T ATE397247T1 AT E397247 T1 ATE397247 T1 AT E397247T1 AT 05738590 T AT05738590 T AT 05738590T AT 05738590 T AT05738590 T AT 05738590T AT E397247 T1 ATE397247 T1 AT E397247T1
- Authority
- AT
- Austria
- Prior art keywords
- instructions
- padd
- cache
- microprocessor
- processing
- Prior art date
Links
- 230000003068 static effect Effects 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3814—Implementation provisions of instruction buffers, e.g. prefetch buffer; banks
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
- G06F9/3016—Decoding the operand specifier, e.g. specifier format
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
- G06F9/3016—Decoding the operand specifier, e.g. specifier format
- G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/3017—Runtime instruction translation, e.g. macros
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3802—Instruction prefetching
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3816—Instruction alignment, e.g. cache line crossing
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Advance Control (AREA)
- Executing Machine-Instructions (AREA)
- Communication Control (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP04102357 | 2004-05-27 |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE397247T1 true ATE397247T1 (de) | 2008-06-15 |
Family
ID=34967382
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT05738590T ATE397247T1 (de) | 2004-05-27 | 2005-05-18 | Mikroprozessor und verfahren zur anweisungsausrichtung |
Country Status (7)
Country | Link |
---|---|
US (1) | US20080028189A1 (de) |
EP (1) | EP1754142B1 (de) |
JP (1) | JP2008500626A (de) |
CN (1) | CN1957326B (de) |
AT (1) | ATE397247T1 (de) |
DE (1) | DE602005007216D1 (de) |
WO (1) | WO2005116819A1 (de) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7376815B2 (en) | 2005-02-25 | 2008-05-20 | Qualcomm Incorporated | Methods and apparatus to insure correct predecode |
US8006238B2 (en) * | 2006-09-26 | 2011-08-23 | International Business Machines Corporation | Workload partitioning in a parallel system with hetergeneous alignment constraints |
JP4968930B2 (ja) * | 2007-08-03 | 2012-07-04 | キヤノン株式会社 | 画像処理装置、画像補正方法、画像処理方法及びプログラム |
US9032154B2 (en) * | 2007-12-13 | 2015-05-12 | Sandisk Technologies Inc. | Integration of secure data transfer applications for generic IO devices |
CN104050092B (zh) | 2013-03-15 | 2018-05-01 | 上海芯豪微电子有限公司 | 一种数据缓存系统及方法 |
US10423353B2 (en) | 2016-11-11 | 2019-09-24 | Micron Technology, Inc. | Apparatuses and methods for memory alignment |
US11836035B2 (en) | 2021-08-06 | 2023-12-05 | Western Digital Technologies, Inc. | Data storage device with data verification circuitry |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6081884A (en) * | 1998-01-05 | 2000-06-27 | Advanced Micro Devices, Inc. | Embedding two different instruction sets within a single long instruction word using predecode bits |
US6192465B1 (en) * | 1998-09-21 | 2001-02-20 | Advanced Micro Devices, Inc. | Using multiple decoders and a reorder queue to decode instructions out of order |
US6240506B1 (en) * | 1998-10-02 | 2001-05-29 | Advanced Micro Devices, Inc. | Expanding instructions with variable-length operands to a fixed length |
US6247097B1 (en) * | 1999-01-22 | 2001-06-12 | International Business Machines Corporation | Aligned instruction cache handling of instruction fetches across multiple predicted branch instructions |
US6421696B1 (en) * | 1999-08-17 | 2002-07-16 | Advanced Micro Devices, Inc. | System and method for high speed execution of Fast Fourier Transforms utilizing SIMD instructions on a general purpose processor |
US6715062B1 (en) * | 2000-07-26 | 2004-03-30 | International Business Machines Corporation | Processor and method for performing a hardware test during instruction execution in a normal mode |
WO2002061574A1 (en) * | 2001-01-30 | 2002-08-08 | Koninklijke Philips Electronics N.V. | Computer instruction with instruction fetch control bits |
US7376815B2 (en) * | 2005-02-25 | 2008-05-20 | Qualcomm Incorporated | Methods and apparatus to insure correct predecode |
-
2005
- 2005-05-18 DE DE602005007216T patent/DE602005007216D1/de active Active
- 2005-05-18 US US11/597,872 patent/US20080028189A1/en not_active Abandoned
- 2005-05-18 JP JP2007514241A patent/JP2008500626A/ja not_active Withdrawn
- 2005-05-18 AT AT05738590T patent/ATE397247T1/de not_active IP Right Cessation
- 2005-05-18 EP EP05738590A patent/EP1754142B1/de active Active
- 2005-05-18 CN CN2005800170745A patent/CN1957326B/zh active Active
- 2005-05-18 WO PCT/IB2005/051617 patent/WO2005116819A1/en active IP Right Grant
Also Published As
Publication number | Publication date |
---|---|
EP1754142B1 (de) | 2008-05-28 |
CN1957326A (zh) | 2007-05-02 |
JP2008500626A (ja) | 2008-01-10 |
DE602005007216D1 (de) | 2008-07-10 |
CN1957326B (zh) | 2010-07-28 |
US20080028189A1 (en) | 2008-01-31 |
WO2005116819A1 (en) | 2005-12-08 |
EP1754142A1 (de) | 2007-02-21 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |