ATE384385T1 - PARALLEL DATA TRANSMISSION WITH MULTIPLE SYNCHRONIZATION CODES - Google Patents

PARALLEL DATA TRANSMISSION WITH MULTIPLE SYNCHRONIZATION CODES

Info

Publication number
ATE384385T1
ATE384385T1 AT02733052T AT02733052T ATE384385T1 AT E384385 T1 ATE384385 T1 AT E384385T1 AT 02733052 T AT02733052 T AT 02733052T AT 02733052 T AT02733052 T AT 02733052T AT E384385 T1 ATE384385 T1 AT E384385T1
Authority
AT
Austria
Prior art keywords
synchronization codes
clock signal
data transmission
synchronization
parallel data
Prior art date
Application number
AT02733052T
Other languages
German (de)
Inventor
Gregory Ehmann
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=25356767&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=ATE384385(T1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE384385T1 publication Critical patent/ATE384385T1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/14—Channel dividing arrangements, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4906—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes
    • H04L25/4908—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes using mBnB codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Information Transfer Systems (AREA)
  • Dc Digital Transmission (AREA)
  • Communication Control (AREA)

Abstract

A high-speed parallel-data communication approach overcomes skewing problems by transferring digital data with automatic realignment. In one example embodiment, a parallel bus has parallel bus lines adapted to transfer digital data from a data file, along with a synchronizing clock signal. To calibrate the synchronization, the sending module transfers synchronization codes which are sampled and validated according to an edge of the clock signal by a receiving module and then used to time-adjust the edge of the clock signal relative to the synchronization codes. The synchronization codes are implemented to toggle the bus lines with each of the synchronization codes transferred.
AT02733052T 2001-05-31 2002-05-28 PARALLEL DATA TRANSMISSION WITH MULTIPLE SYNCHRONIZATION CODES ATE384385T1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/871,117 US6920576B2 (en) 2001-05-31 2001-05-31 Parallel data communication having multiple sync codes

Publications (1)

Publication Number Publication Date
ATE384385T1 true ATE384385T1 (en) 2008-02-15

Family

ID=25356767

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02733052T ATE384385T1 (en) 2001-05-31 2002-05-28 PARALLEL DATA TRANSMISSION WITH MULTIPLE SYNCHRONIZATION CODES

Country Status (7)

Country Link
US (1) US6920576B2 (en)
EP (1) EP1397895B1 (en)
JP (1) JP4228051B2 (en)
KR (1) KR100873569B1 (en)
AT (1) ATE384385T1 (en)
DE (1) DE60224666T2 (en)
WO (1) WO2002098091A2 (en)

Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6907552B2 (en) * 2001-08-29 2005-06-14 Tricn Inc. Relative dynamic skew compensation of parallel data lines
DE10156111A1 (en) * 2001-11-16 2003-06-05 Philips Intellectual Property Receive circuit for receiving message signals
US7720107B2 (en) * 2003-06-16 2010-05-18 Cisco Technology, Inc. Aligning data in a wide, high-speed, source synchronous parallel link
US7216247B2 (en) * 2004-08-05 2007-05-08 Texas Instruments Incorporated Methods and systems to reduce data skew in FIFOs
US7526704B2 (en) * 2005-08-23 2009-04-28 Micron Technology, Inc. Testing system and method allowing adjustment of signal transmit timing
DE602006020778D1 (en) * 2006-01-03 2011-04-28 Nxp Bv SYSTEM AND METHOD FOR SERIAL DATA COMMUNICATION
US7783911B2 (en) * 2006-06-27 2010-08-24 International Business Machines Corporation Programmable bus driver launch delay/cycle delay to reduce elastic interface elasticity requirements
US7734944B2 (en) * 2006-06-27 2010-06-08 International Business Machines Corporation Mechanism for windaging of a double rate driver
US7752475B2 (en) * 2006-06-27 2010-07-06 International Business Machines Corporation Late data launch for a double data rate elastic interface
US7882322B2 (en) * 2006-06-27 2011-02-01 International Business Machines Corporation Early directory access of a double data rate elastic interface
US7739538B2 (en) * 2006-06-27 2010-06-15 International Business Machines Corporation Double data rate chaining for synchronous DDR interfaces
US20080046772A1 (en) * 2006-07-17 2008-02-21 International Business Machines Corporation Shifting inactive clock edge for noise reduction
US7546494B2 (en) * 2006-08-03 2009-06-09 Avalon Microelectronics Inc. Skew-correcting apparatus using dual loopback
US7760836B2 (en) * 2006-08-03 2010-07-20 Avalon Microelectronics, Inc. Skew-correcting apparatus using external communications element
US7536579B2 (en) * 2006-08-03 2009-05-19 Avalon Microelectronics, Inc. Skew-correcting apparatus using iterative approach
US20090055694A1 (en) * 2007-08-22 2009-02-26 Tektronix, Inc. Apparatus and method for measuring skew in serial data communication
US20090102529A1 (en) * 2007-10-23 2009-04-23 International Business Machines Corporation Shifting inactive clock edge for noise reduction
EP2278714B1 (en) 2009-07-02 2015-09-16 Nxp B.V. Power stage
CN102299787B (en) * 2011-08-25 2014-03-05 北京昆腾微电子有限公司 Method for realizing data synchronization in high-speed system-on-chip circuit and device
US9331866B2 (en) 2012-04-20 2016-05-03 Nxp B.V. Network communications apparatus, system, and method
US8787502B2 (en) 2012-04-24 2014-07-22 Nxp B.V. Capacitive isolated voltage domains
US8571093B1 (en) 2012-04-24 2013-10-29 Nxp B.V. Communication interface for galvanic isolation
US8818265B2 (en) 2012-04-24 2014-08-26 Nxp B.V. Interface for communication between voltage domains
US8867592B2 (en) 2012-05-09 2014-10-21 Nxp B.V. Capacitive isolated voltage domains
US9007141B2 (en) 2012-05-23 2015-04-14 Nxp B.V. Interface for communication between voltage domains
US8693528B1 (en) 2012-11-30 2014-04-08 Nxp B.V. Common mode suppression circuit
US8680690B1 (en) 2012-12-07 2014-03-25 Nxp B.V. Bond wire arrangement for efficient signal transmission
US9467060B2 (en) 2013-04-03 2016-10-11 Nxp B.V. Capacitive level shifter devices, methods and systems
US8896377B1 (en) 2013-05-29 2014-11-25 Nxp B.V. Apparatus for common mode suppression
US10448215B2 (en) 2016-06-24 2019-10-15 JIO, Inc. Communicating location change information
US10791429B2 (en) 2016-06-24 2020-09-29 JIO, Inc. Communicating location change information in accordance with a reporting approach
US10686583B2 (en) * 2017-07-04 2020-06-16 Kandou Labs, S.A. Method for measuring and correcting multi-wire skew
JP2020198577A (en) * 2019-06-04 2020-12-10 キオクシア株式会社 Memory system
CN114826503B (en) * 2022-06-27 2022-09-27 杭州加速科技有限公司 Method and device for calibrating parallel bus data sampling window in FPGA

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE307970B (en) 1965-08-30 1969-01-27 Ericsson Telefon Ab L M
US5734685A (en) * 1996-01-03 1998-03-31 Credence Systems Corporation Clock signal deskewing system
US6215798B1 (en) * 1996-11-01 2001-04-10 Telefonaktiebolaget Lm Ericsson (Publ) Multi-frame synchronization for parallel channel transmissions
US5978419A (en) * 1997-06-24 1999-11-02 Sun Microsystems, Inc. Transmitter and receiver circuits for high-speed parallel digital data transmission link
JP3387379B2 (en) * 1997-09-01 2003-03-17 富士通株式会社 Parallel data skew detection circuit
US6725388B1 (en) * 2000-06-13 2004-04-20 Intel Corporation Method and system for performing link synchronization between two clock domains by inserting command signals into a data stream transmitted between the two clock domains

Also Published As

Publication number Publication date
KR20030029120A (en) 2003-04-11
US20020184549A1 (en) 2002-12-05
DE60224666T2 (en) 2008-12-24
JP4228051B2 (en) 2009-02-25
EP1397895A2 (en) 2004-03-17
JP2004527988A (en) 2004-09-09
KR100873569B1 (en) 2008-12-12
US6920576B2 (en) 2005-07-19
WO2002098091A3 (en) 2003-04-24
WO2002098091A2 (en) 2002-12-05
EP1397895B1 (en) 2008-01-16
DE60224666D1 (en) 2008-03-06

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