ATE384385T1 - Parallele datenübertragung mit mehreren synchronisierungskodes - Google Patents

Parallele datenübertragung mit mehreren synchronisierungskodes

Info

Publication number
ATE384385T1
ATE384385T1 AT02733052T AT02733052T ATE384385T1 AT E384385 T1 ATE384385 T1 AT E384385T1 AT 02733052 T AT02733052 T AT 02733052T AT 02733052 T AT02733052 T AT 02733052T AT E384385 T1 ATE384385 T1 AT E384385T1
Authority
AT
Austria
Prior art keywords
synchronization codes
clock signal
data transmission
synchronization
parallel data
Prior art date
Application number
AT02733052T
Other languages
English (en)
Inventor
Gregory Ehmann
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=25356767&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=ATE384385(T1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE384385T1 publication Critical patent/ATE384385T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/14—Channel dividing arrangements, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4906—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes
    • H04L25/4908—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes using mBnB codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
AT02733052T 2001-05-31 2002-05-28 Parallele datenübertragung mit mehreren synchronisierungskodes ATE384385T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/871,117 US6920576B2 (en) 2001-05-31 2001-05-31 Parallel data communication having multiple sync codes

Publications (1)

Publication Number Publication Date
ATE384385T1 true ATE384385T1 (de) 2008-02-15

Family

ID=25356767

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02733052T ATE384385T1 (de) 2001-05-31 2002-05-28 Parallele datenübertragung mit mehreren synchronisierungskodes

Country Status (7)

Country Link
US (1) US6920576B2 (de)
EP (1) EP1397895B1 (de)
JP (1) JP4228051B2 (de)
KR (1) KR100873569B1 (de)
AT (1) ATE384385T1 (de)
DE (1) DE60224666T2 (de)
WO (1) WO2002098091A2 (de)

Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6907552B2 (en) * 2001-08-29 2005-06-14 Tricn Inc. Relative dynamic skew compensation of parallel data lines
DE10156111A1 (de) * 2001-11-16 2003-06-05 Philips Intellectual Property Empfangsschaltung zum Empfang von Nachrichtensignalen
US7720107B2 (en) * 2003-06-16 2010-05-18 Cisco Technology, Inc. Aligning data in a wide, high-speed, source synchronous parallel link
US7216247B2 (en) * 2004-08-05 2007-05-08 Texas Instruments Incorporated Methods and systems to reduce data skew in FIFOs
US7526704B2 (en) * 2005-08-23 2009-04-28 Micron Technology, Inc. Testing system and method allowing adjustment of signal transmit timing
WO2007077501A1 (en) * 2006-01-03 2007-07-12 Nxp B.V. Serial data communication system and method
US7882322B2 (en) * 2006-06-27 2011-02-01 International Business Machines Corporation Early directory access of a double data rate elastic interface
US7783911B2 (en) * 2006-06-27 2010-08-24 International Business Machines Corporation Programmable bus driver launch delay/cycle delay to reduce elastic interface elasticity requirements
US7739538B2 (en) * 2006-06-27 2010-06-15 International Business Machines Corporation Double data rate chaining for synchronous DDR interfaces
US7734944B2 (en) * 2006-06-27 2010-06-08 International Business Machines Corporation Mechanism for windaging of a double rate driver
US7752475B2 (en) * 2006-06-27 2010-07-06 International Business Machines Corporation Late data launch for a double data rate elastic interface
US20080046772A1 (en) * 2006-07-17 2008-02-21 International Business Machines Corporation Shifting inactive clock edge for noise reduction
US7546494B2 (en) * 2006-08-03 2009-06-09 Avalon Microelectronics Inc. Skew-correcting apparatus using dual loopback
US7760836B2 (en) * 2006-08-03 2010-07-20 Avalon Microelectronics, Inc. Skew-correcting apparatus using external communications element
US7536579B2 (en) * 2006-08-03 2009-05-19 Avalon Microelectronics, Inc. Skew-correcting apparatus using iterative approach
US20090055694A1 (en) * 2007-08-22 2009-02-26 Tektronix, Inc. Apparatus and method for measuring skew in serial data communication
US20090102529A1 (en) * 2007-10-23 2009-04-23 International Business Machines Corporation Shifting inactive clock edge for noise reduction
EP2278714B1 (de) 2009-07-02 2015-09-16 Nxp B.V. Leistungsstufe
CN102299787B (zh) * 2011-08-25 2014-03-05 北京昆腾微电子有限公司 在高速系统级芯片电路中实现数据同步的方法和装置
US9331866B2 (en) 2012-04-20 2016-05-03 Nxp B.V. Network communications apparatus, system, and method
US8818265B2 (en) 2012-04-24 2014-08-26 Nxp B.V. Interface for communication between voltage domains
US8571093B1 (en) * 2012-04-24 2013-10-29 Nxp B.V. Communication interface for galvanic isolation
US8787502B2 (en) 2012-04-24 2014-07-22 Nxp B.V. Capacitive isolated voltage domains
US8867592B2 (en) 2012-05-09 2014-10-21 Nxp B.V. Capacitive isolated voltage domains
US9007141B2 (en) 2012-05-23 2015-04-14 Nxp B.V. Interface for communication between voltage domains
US8693528B1 (en) 2012-11-30 2014-04-08 Nxp B.V. Common mode suppression circuit
US8680690B1 (en) 2012-12-07 2014-03-25 Nxp B.V. Bond wire arrangement for efficient signal transmission
US9467060B2 (en) 2013-04-03 2016-10-11 Nxp B.V. Capacitive level shifter devices, methods and systems
US8896377B1 (en) 2013-05-29 2014-11-25 Nxp B.V. Apparatus for common mode suppression
US10791429B2 (en) 2016-06-24 2020-09-29 JIO, Inc. Communicating location change information in accordance with a reporting approach
US10448215B2 (en) 2016-06-24 2019-10-15 JIO, Inc. Communicating location change information
US10686583B2 (en) * 2017-07-04 2020-06-16 Kandou Labs, S.A. Method for measuring and correcting multi-wire skew
JP2020198577A (ja) * 2019-06-04 2020-12-10 キオクシア株式会社 メモリシステム
CN114826503B (zh) * 2022-06-27 2022-09-27 杭州加速科技有限公司 Fpga内并行总线数据采样窗口的校准方法、装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE307970B (de) * 1965-08-30 1969-01-27 Ericsson Telefon Ab L M
US5734685A (en) * 1996-01-03 1998-03-31 Credence Systems Corporation Clock signal deskewing system
US6215798B1 (en) * 1996-11-01 2001-04-10 Telefonaktiebolaget Lm Ericsson (Publ) Multi-frame synchronization for parallel channel transmissions
US5978419A (en) * 1997-06-24 1999-11-02 Sun Microsystems, Inc. Transmitter and receiver circuits for high-speed parallel digital data transmission link
JP3387379B2 (ja) * 1997-09-01 2003-03-17 富士通株式会社 パラレルデータスキュー検出回路
US6725388B1 (en) * 2000-06-13 2004-04-20 Intel Corporation Method and system for performing link synchronization between two clock domains by inserting command signals into a data stream transmitted between the two clock domains

Also Published As

Publication number Publication date
US20020184549A1 (en) 2002-12-05
EP1397895B1 (de) 2008-01-16
JP4228051B2 (ja) 2009-02-25
US6920576B2 (en) 2005-07-19
DE60224666T2 (de) 2008-12-24
KR100873569B1 (ko) 2008-12-12
WO2002098091A2 (en) 2002-12-05
WO2002098091A3 (en) 2003-04-24
DE60224666D1 (de) 2008-03-06
JP2004527988A (ja) 2004-09-09
KR20030029120A (ko) 2003-04-11
EP1397895A2 (de) 2004-03-17

Similar Documents

Publication Publication Date Title
ATE384385T1 (de) Parallele datenübertragung mit mehreren synchronisierungskodes
WO2002097646A3 (en) Parallel data communication having skew intolerant data groups
KR960003177A (ko) 셀프-타임 통신 인터페이스와 디지탈 데이타 전송 방법
US7839839B2 (en) Differential inverse multiplexing virtual channels in 40G ethernet applications
CN1957556A (zh) 确定第一与第二时钟域之间的时间差
AU2002233528A1 (en) Synchronous to asynchronous to synchronous interface
MXPA04004338A (es) Comunicaciones en una red inalambrica asincroncia.
DE602004031925D1 (de) Asynchrone system-on-a-chip-verbindung
WO2009144308A3 (de) Serial-peripheral-interface-schnittstelle mit verminderter verbindungsleitungsanzahl
CN102169270A (zh) 光串行化/解串行化装置和方法及其制造方法
US9001951B1 (en) Techniques for transferring time information between clock domains
JP5826222B2 (ja) 高速シリアルデータ信号のレシーバ回路網
WO1999053406A3 (en) High-speed data bus for network switching
ATE443892T1 (de) I2c-slave/master-schnittstellenverbesserung durch verwendung von automaten
EP2207315B1 (de) Übertragung von parallelen Datenflüssen in einem Parallelbus
WO2006017460A3 (en) Data transmission synchronization
WO2020177414A1 (zh) 基于FlexE一层交叉架构的数据处理方法及系统
WO1999038295A8 (en) Method and apparatus for source synchronous data transfer
WO2016058344A1 (zh) 一种确定链路延时的方法、装置、通信设备和存储介质
IL157748A0 (en) Method and system for galvanically isolated transmission of gigabit/sec data via a slip ring arrangement
WO2003088595A3 (en) Synchronization in a communication system
CN101950278A (zh) 高速低功耗串行通信数据接收接口架构
US10284358B1 (en) Clock and frame synchronization carried as a single composite signal allows the use of a single transmission line with a narrower bandwidth
CN111357243A (zh) 总线系统的用户设备、运行方法及总线系统
CN100570590C (zh) 一种硬件板卡的背板接口

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties