ATE377791T1 - Verfahren zum prüfen von codes für mikroschaltungen mit eingeschränkten ressourcen - Google Patents

Verfahren zum prüfen von codes für mikroschaltungen mit eingeschränkten ressourcen

Info

Publication number
ATE377791T1
ATE377791T1 AT03735717T AT03735717T ATE377791T1 AT E377791 T1 ATE377791 T1 AT E377791T1 AT 03735717 T AT03735717 T AT 03735717T AT 03735717 T AT03735717 T AT 03735717T AT E377791 T1 ATE377791 T1 AT E377791T1
Authority
AT
Austria
Prior art keywords
code
limited resources
microcircuit
registers
micro circuits
Prior art date
Application number
AT03735717T
Other languages
English (en)
Inventor
Jean-Francois Grezes
Alexandre Benoit
Original Assignee
Gemplus Card Int
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gemplus Card Int filed Critical Gemplus Card Int
Application granted granted Critical
Publication of ATE377791T1 publication Critical patent/ATE377791T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/44—Encoding
    • G06F8/441—Register allocation; Assignment of physical memory space to logical memory space
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/445—Program loading or initiating
    • G06F9/44589—Program code verification, e.g. Java bytecode verification, proof-carrying code

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Devices For Executing Special Programs (AREA)
  • Debugging And Monitoring (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Microscoopes, Condenser (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Slot Machines And Peripheral Devices (AREA)
  • Structure Of Printed Boards (AREA)
AT03735717T 2002-05-27 2003-05-23 Verfahren zum prüfen von codes für mikroschaltungen mit eingeschränkten ressourcen ATE377791T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0206445A FR2840084A1 (fr) 2002-05-27 2002-05-27 Procede de verification de codes pour microcircuits a ressources limitees

Publications (1)

Publication Number Publication Date
ATE377791T1 true ATE377791T1 (de) 2007-11-15

Family

ID=29415115

Family Applications (1)

Application Number Title Priority Date Filing Date
AT03735717T ATE377791T1 (de) 2002-05-27 2003-05-23 Verfahren zum prüfen von codes für mikroschaltungen mit eingeschränkten ressourcen

Country Status (8)

Country Link
US (1) US20050252977A1 (de)
EP (1) EP1512071B1 (de)
CN (1) CN1672130A (de)
AT (1) ATE377791T1 (de)
AU (1) AU2003238085A1 (de)
DE (1) DE60317324D1 (de)
FR (1) FR2840084A1 (de)
WO (1) WO2003100607A2 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2884994A1 (fr) 2005-04-22 2006-10-27 Gemplus Sa Procede de verification de pseudo-code charge dans un systeme embarque, notamment une carte a puce
US8200983B1 (en) * 2006-09-09 2012-06-12 9Rays.Net, Inc. System and method for tamper-proofing executable binary assemblies
JP2013138409A (ja) * 2011-11-30 2013-07-11 Canon Inc 情報処理装置およびその方法
EP2782006B1 (de) * 2013-03-19 2018-06-13 Nxp B.V. Prozess und System zur Überprüfung eines Computerprogramms auf einer Chipkarte
US10261764B2 (en) * 2014-05-13 2019-04-16 Oracle International Corporation Handling value types
US11416273B2 (en) * 2020-01-16 2022-08-16 Red Hat, Inc. Adaptive and secure bitecode injection based on comparison with previously stored bytecode

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5748964A (en) * 1994-12-20 1998-05-05 Sun Microsystems, Inc. Bytecode program interpreter apparatus and method with pre-verification of data type restrictions
BR9713267A (pt) * 1996-10-25 2004-06-15 Schlumberger Systems & Service Cartão de circuito integrado para uso com um terminal, processo para uso com o mesmo, microcontrolador e processo para sua programação
US6092147A (en) * 1997-04-15 2000-07-18 Sun Microsystems, Inc. Virtual machine with securely distributed bytecode verification
FR2795835B1 (fr) * 1999-07-01 2001-10-05 Bull Cp8 Procede de verification de transformateurs de codes pour un systeme embarque, notamment sur une carte a puce
FR2797963B1 (fr) * 1999-08-23 2002-11-29 Trusted Logic Protocole de gestion, procede de verification et de transformation d'un fragment de programme telecharge et systemes correspondants
US6560774B1 (en) * 1999-09-01 2003-05-06 Microsoft Corporation Verifier to check intermediate language
US6763463B1 (en) * 1999-11-05 2004-07-13 Microsoft Corporation Integrated circuit card with data modifying capabilities and related methods
US6981245B1 (en) * 2000-09-14 2005-12-27 Sun Microsystems, Inc. Populating binary compatible resource-constrained devices with content verified using API definitions
US7506175B2 (en) * 2000-11-06 2009-03-17 International Business Machines Corporation File language verification
EP1207454A1 (de) * 2000-11-15 2002-05-22 International Business Machines Corporation Java Laufzeitsystem mit modifizierten Verknüpfungsnamen

Also Published As

Publication number Publication date
FR2840084A1 (fr) 2003-11-28
WO2003100607A2 (fr) 2003-12-04
EP1512071B1 (de) 2007-11-07
US20050252977A1 (en) 2005-11-17
WO2003100607A3 (fr) 2004-02-19
EP1512071A2 (de) 2005-03-09
DE60317324D1 (de) 2007-12-20
AU2003238085A1 (en) 2003-12-12
CN1672130A (zh) 2005-09-21

Similar Documents

Publication Publication Date Title
WO2004042499A3 (en) Debugging using control-dataflow graph with reconfigurable hardware emulation
DE60313652D1 (de) Verfahren und gerät zur kontrolle der umwandlung von programm-kodes
DE602004032466D1 (de) Durchführung von prüfungen an der betriebsmittelbenutzung von computerprogrammen
ATE526628T1 (de) System und verfahren zum modellieren, abstrahieren und analysieren von software
ATE415655T1 (de) Vorrichtung und verfahren zum automatischen parallelisieren von netzwerkanwendungen durch pipeline-transformation
DE60211846D1 (de) Verfahren, System und Computerprogramm zur Erzeugung von Codes für CDMA-Nachrichtenübertragung
SE0202019D0 (sv) Revalidation of a compiler for safety control
ATE365349T1 (de) Verfahren und system zum debuggen unter verwendung duplizierter logik
ATE377791T1 (de) Verfahren zum prüfen von codes für mikroschaltungen mit eingeschränkten ressourcen
WO2004010295A3 (en) Method and apparatus for instrumentation on/off
TW200506717A (en) Method and system for performing global processor resource assignment in an assembler
CN104899138A (zh) 一种uvm验证环境中复用c程序测试向量的方法
ATE425503T1 (de) Wasserzeichenmarkierung eines computerprogrammcodes
US7085964B2 (en) Dynamic test program generator for VLIW simulation
ATE438145T1 (de) Verfahren und vorrichtung zur mehrfachverarbeitungsausführung von computeranweisungen
Wilcox Professional verification: a guide to advanced functional verification
CN108572892B (zh) 一种基于PowerPC多核处理器的离线测试方法和装置
EP1191443A3 (de) Verfahren und System zum Testen eines Prozessors
DE602004031573D1 (de) Chipkartenemulator und ein damit verbundenes Verfahren mit einer Pufferschnittstelle
CN116149645A (zh) 基于ascet模型的软件集成方法、系统及介质
DE602006014549D1 (de) Verfahren und system für debug und test unter verwendung replizierter logik
US11796593B2 (en) Compiler-based code generation for post-silicon validation
Glamm et al. Automatic verification of instruction set simulation using synchronized state comparison
DE50207670D1 (de) Verfahren zur aktualisierung von elektronisch modifizierbaren komponenten eines automatisierungsgerätes
Turpin A progressive software development lifecycle

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties