ATE373623T1 - Metallverdrahtungsverfahren für unterschnittene löcher - Google Patents
Metallverdrahtungsverfahren für unterschnittene löcherInfo
- Publication number
- ATE373623T1 ATE373623T1 AT03256418T AT03256418T ATE373623T1 AT E373623 T1 ATE373623 T1 AT E373623T1 AT 03256418 T AT03256418 T AT 03256418T AT 03256418 T AT03256418 T AT 03256418T AT E373623 T1 ATE373623 T1 AT E373623T1
- Authority
- AT
- Austria
- Prior art keywords
- metal wiring
- undercut
- wiring method
- undercut holes
- milling
- Prior art date
Links
- 239000002184 metal Substances 0.000 title abstract 7
- 238000000034 method Methods 0.000 title abstract 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 2
- 239000011521 glass Substances 0.000 abstract 2
- 229910052710 silicon Inorganic materials 0.000 abstract 2
- 239000010703 silicon Substances 0.000 abstract 2
- 238000000992 sputter etching Methods 0.000 abstract 2
- 239000000758 substrate Substances 0.000 abstract 2
- 238000000151 deposition Methods 0.000 abstract 1
- 238000012858 packaging process Methods 0.000 abstract 1
- 238000003466 welding Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/0006—Interconnects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Power Engineering (AREA)
- Micromachines (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Coating With Molten Metal (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2002-0063608A KR100461002B1 (ko) | 2002-10-17 | 2002-10-17 | 언더컷 메탈 배선방법 |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE373623T1 true ATE373623T1 (de) | 2007-10-15 |
Family
ID=36592652
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT03256418T ATE373623T1 (de) | 2002-10-17 | 2003-10-10 | Metallverdrahtungsverfahren für unterschnittene löcher |
Country Status (9)
Country | Link |
---|---|
US (1) | US6835594B2 (de) |
EP (1) | EP1411025B1 (de) |
JP (1) | JP2004136435A (de) |
KR (1) | KR100461002B1 (de) |
AT (1) | ATE373623T1 (de) |
DE (1) | DE60316394T2 (de) |
DK (1) | DK1411025T3 (de) |
ES (1) | ES2294247T3 (de) |
TW (1) | TWI233917B (de) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CA2621103C (en) * | 2005-09-06 | 2015-11-03 | Nantero, Inc. | Nanotube fabric-based sensor systems and methods of making same |
US7915696B2 (en) * | 2007-10-24 | 2011-03-29 | General Electric Company | Electrical connection through a substrate to a microelectromechanical device |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH047836A (ja) * | 1990-04-26 | 1992-01-13 | Toshiba Corp | 半導体装置及びその製造方法 |
US5198390A (en) * | 1992-01-16 | 1993-03-30 | Cornell Research Foundation, Inc. | RIE process for fabricating submicron, silicon electromechanical structures |
US5468595A (en) * | 1993-01-29 | 1995-11-21 | Electron Vision Corporation | Method for three-dimensional control of solubility properties of resist layers |
US5363021A (en) * | 1993-07-12 | 1994-11-08 | Cornell Research Foundation, Inc. | Massively parallel array cathode |
EP0735577A3 (de) * | 1994-12-14 | 1997-04-02 | Applied Materials Inc | Abscheidungsverfahren und Einrichtung dafür |
US5610431A (en) * | 1995-05-12 | 1997-03-11 | The Charles Stark Draper Laboratory, Inc. | Covers for micromechanical sensors and other semiconductor devices |
KR100442824B1 (ko) * | 1997-05-12 | 2004-09-18 | 삼성전자주식회사 | 마이크로구조물소자및그제조방법 |
US6333560B1 (en) * | 1999-01-14 | 2001-12-25 | International Business Machines Corporation | Process and structure for an interlock and high performance multilevel structures for chip interconnects and packaging technologies |
EP1050905B1 (de) * | 1999-05-07 | 2017-06-21 | Shinko Electric Industries Co. Ltd. | Verfahren zur Herstellung einer Halbleitervorrichtung mit isolierender Schicht |
KR100314622B1 (ko) * | 1999-06-15 | 2001-11-17 | 이형도 | 마이크로 센서 및 그 패키지방법 |
JP3872936B2 (ja) * | 2000-06-30 | 2007-01-24 | 株式会社東芝 | 磁気抵抗効果素子の製造方法と強磁性トンネル接合素子 |
JP2002043317A (ja) * | 2000-07-27 | 2002-02-08 | Sony Corp | 半導体装置の製造方法 |
US6566274B1 (en) * | 2001-11-28 | 2003-05-20 | Unaxis Balzer Limited | Lithography process for transparent substrates |
-
2002
- 2002-10-17 KR KR10-2002-0063608A patent/KR100461002B1/ko not_active IP Right Cessation
-
2003
- 2003-10-10 ES ES03256418T patent/ES2294247T3/es not_active Expired - Lifetime
- 2003-10-10 DE DE60316394T patent/DE60316394T2/de not_active Expired - Fee Related
- 2003-10-10 DK DK03256418T patent/DK1411025T3/da active
- 2003-10-10 EP EP03256418A patent/EP1411025B1/de not_active Expired - Lifetime
- 2003-10-10 AT AT03256418T patent/ATE373623T1/de not_active IP Right Cessation
- 2003-10-16 JP JP2003356508A patent/JP2004136435A/ja active Pending
- 2003-10-17 US US10/686,769 patent/US6835594B2/en not_active Expired - Lifetime
- 2003-10-17 TW TW092128849A patent/TWI233917B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
TW200426110A (en) | 2004-12-01 |
EP1411025A3 (de) | 2004-11-03 |
DE60316394T2 (de) | 2008-01-17 |
EP1411025A2 (de) | 2004-04-21 |
TWI233917B (en) | 2005-06-11 |
KR100461002B1 (ko) | 2004-12-09 |
DE60316394D1 (de) | 2007-10-31 |
US20040203186A1 (en) | 2004-10-14 |
ES2294247T3 (es) | 2008-04-01 |
EP1411025B1 (de) | 2007-09-19 |
DK1411025T3 (da) | 2007-11-05 |
JP2004136435A (ja) | 2004-05-13 |
US6835594B2 (en) | 2004-12-28 |
KR20040034949A (ko) | 2004-04-29 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP1416069A4 (de) | Organisches halbleiterelement | |
DE60321287D1 (de) | Verpackung auf Waferebene für mikroelektromechanische Vorrichtungen | |
WO2002084739A1 (en) | Thin film-device manufacturing method, and semiconductor device | |
WO2018094905A1 (zh) | 在mems传感器上形成过滤网的方法以及mems传感器 | |
EP1788617A4 (de) | Substrathalteeinrichtung, belichtungsvorrichtung damit, belichtungsverfahren, verfahren zur bauelementeherstellung und flüssigkeitsabweisende platte | |
US20130050228A1 (en) | Glass as a substrate material and a final package for mems and ic devices | |
FI20000900A (fi) | Menetelmä ohutkalvon kasvattamiseksi substraatille | |
FI20001694A0 (fi) | Menetelmä ohutkalvon kasvattamiseksi substraatille | |
US20040251524A1 (en) | Wafer bonding using reactive foils for massively parallel micro-electromechanical systems packaging | |
WO2003088340A3 (de) | Verfahren zur herstellung strukturierter schichten auf substraten | |
US20130050155A1 (en) | Glass as a substrate material and a final package for mems and ic devices | |
WO2005039868A3 (de) | Strukturierung von elektrischen funktionsschichten mittels einer transferfolie und strukturierung des klebers | |
ATE408584T1 (de) | Dünnschichtverkapselung von mems-bauelementen | |
US20210020491A1 (en) | Multi-layer tethers for micro-transfer printing | |
DE602006016850D1 (de) | Verfahren zur herstellung von ein gettermaterial enthaltenden mikromechanischen vorrichtungen und so hergestellte vorrichtungen | |
JP2008274373A (ja) | 蒸着用マスク | |
AU2003270040A1 (en) | Fabrication method for a monocrystalline semiconductor layer on a substrate | |
EP0886329A3 (de) | Elektrolumineszentes Bauteil, elektrolumineszentes Gerät und Herstellungsverfahren | |
EP1548821A3 (de) | Klebefilm zum Schneiden von Halbleiterchips | |
WO2004090201A3 (fr) | Procede de fabrication de cristaux monocristallins | |
WO2002043124A3 (fr) | Procede de fabrication d'un substrat contenant une couche mince sur un support et substrat obtenu par ce procede | |
FR2827708B1 (fr) | Dispositif a semi-conducteur sur substrat soi et procede de fabrication | |
ATE463845T1 (de) | Dünnfilmtranistor-bauelement und diesbezügliches verfahren | |
TR200200495T2 (tr) | Mikro köprü yapısı | |
WO2002046091A3 (de) | Verfahren zur herstellung eines fluidbauelements, fluidbauelement und analysevorrichtung |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |