ATE338976T1 - Vliw prozessor mit datenueberflussmittel - Google Patents
Vliw prozessor mit datenueberflussmittelInfo
- Publication number
- ATE338976T1 ATE338976T1 AT03710133T AT03710133T ATE338976T1 AT E338976 T1 ATE338976 T1 AT E338976T1 AT 03710133 T AT03710133 T AT 03710133T AT 03710133 T AT03710133 T AT 03710133T AT E338976 T1 ATE338976 T1 AT E338976T1
- Authority
- AT
- Austria
- Prior art keywords
- vliw processor
- register file
- distributed register
- functional units
- data abundance
- Prior art date
Links
- 230000008878 coupling Effects 0.000 abstract 1
- 238000010168 coupling process Methods 0.000 abstract 1
- 238000005859 coupling reaction Methods 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
- G06F9/30043—LOAD or STORE instructions; Clear instruction
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/3012—Organisation of register space, e.g. banked or distributed register file
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
- G06F9/3826—Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
- G06F9/3828—Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage with global bypass, e.g. between pipelines, between clusters
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multi Processors (AREA)
- Executing Machine-Instructions (AREA)
- Image Processing (AREA)
- Hardware Redundancy (AREA)
- Advance Control (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP02076524 | 2002-04-18 |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE338976T1 true ATE338976T1 (de) | 2006-09-15 |
Family
ID=29225683
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT03710133T ATE338976T1 (de) | 2002-04-18 | 2003-04-01 | Vliw prozessor mit datenueberflussmittel |
Country Status (8)
Country | Link |
---|---|
US (1) | US7107432B2 (de) |
EP (1) | EP1499959B1 (de) |
JP (1) | JP3979998B2 (de) |
CN (1) | CN1320451C (de) |
AT (1) | ATE338976T1 (de) |
AU (1) | AU2003214554A1 (de) |
DE (1) | DE60308168T2 (de) |
WO (1) | WO2003088037A1 (de) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030105617A1 (en) * | 2001-12-05 | 2003-06-05 | Nec Usa, Inc. | Hardware acceleration system for logic simulation |
US20070073999A1 (en) * | 2005-09-28 | 2007-03-29 | Verheyen Henry T | Hardware acceleration system for logic simulation using shift register as local cache with path for bypassing shift register |
US7444276B2 (en) * | 2005-09-28 | 2008-10-28 | Liga Systems, Inc. | Hardware acceleration system for logic simulation using shift register as local cache |
US20070074000A1 (en) * | 2005-09-28 | 2007-03-29 | Liga Systems, Inc. | VLIW Acceleration System Using Multi-state Logic |
EP1934845A4 (de) * | 2005-09-28 | 2010-05-19 | Liga Systems Inc | Hardware-beschleunigungssystem zur logischen simulation unter verwendung eines schieberegisters als lokalem cache |
CN101158891B (zh) * | 2007-11-19 | 2010-07-21 | 中国科学院计算技术研究所 | 在非cisc处理器上进行浮点栈溢出检查的装置和方法 |
TWI401602B (zh) * | 2009-07-06 | 2013-07-11 | Nat Univ Tsing Hua | 處理器之使用暫存器檔案的溢出方法 |
US9009692B2 (en) * | 2009-12-26 | 2015-04-14 | Oracle America, Inc. | Minimizing register spills by using register moves |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3745450B2 (ja) | 1996-05-13 | 2006-02-15 | 株式会社ルネサステクノロジ | 並列処理プロセッサ |
WO1998006042A1 (en) * | 1996-08-07 | 1998-02-12 | Sun Microsystems, Inc. | Wide instruction unpack method and apparatus |
US7114056B2 (en) * | 1998-12-03 | 2006-09-26 | Sun Microsystems, Inc. | Local and global register partitioning in a VLIW processor |
US6487630B2 (en) * | 1999-02-26 | 2002-11-26 | Intel Corporation | Processor with register stack engine that dynamically spills/fills physical registers to backing store |
US6928645B2 (en) * | 2001-03-30 | 2005-08-09 | Intel Corporation | Software-based speculative pre-computation and multithreading |
US20030105617A1 (en) * | 2001-12-05 | 2003-06-05 | Nec Usa, Inc. | Hardware acceleration system for logic simulation |
-
2003
- 2003-04-01 AT AT03710133T patent/ATE338976T1/de not_active IP Right Cessation
- 2003-04-01 EP EP03710133A patent/EP1499959B1/de not_active Expired - Lifetime
- 2003-04-01 WO PCT/IB2003/001364 patent/WO2003088037A1/en active IP Right Grant
- 2003-04-01 AU AU2003214554A patent/AU2003214554A1/en not_active Abandoned
- 2003-04-01 US US10/511,208 patent/US7107432B2/en not_active Expired - Fee Related
- 2003-04-01 CN CNB038085011A patent/CN1320451C/zh not_active Expired - Fee Related
- 2003-04-01 JP JP2003584913A patent/JP3979998B2/ja not_active Expired - Fee Related
- 2003-04-01 DE DE60308168T patent/DE60308168T2/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
AU2003214554A1 (en) | 2003-10-27 |
US7107432B2 (en) | 2006-09-12 |
JP2005523498A (ja) | 2005-08-04 |
DE60308168T2 (de) | 2007-08-23 |
CN1320451C (zh) | 2007-06-06 |
CN1647031A (zh) | 2005-07-27 |
EP1499959A1 (de) | 2005-01-26 |
JP3979998B2 (ja) | 2007-09-19 |
DE60308168D1 (de) | 2006-10-19 |
EP1499959B1 (de) | 2006-09-06 |
WO2003088037A1 (en) | 2003-10-23 |
US20050144424A1 (en) | 2005-06-30 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |