ATE309549T1 - Testen von schaltungen mit mehreren taktsignal- domänen - Google Patents

Testen von schaltungen mit mehreren taktsignal- domänen

Info

Publication number
ATE309549T1
ATE309549T1 AT02791935T AT02791935T ATE309549T1 AT E309549 T1 ATE309549 T1 AT E309549T1 AT 02791935 T AT02791935 T AT 02791935T AT 02791935 T AT02791935 T AT 02791935T AT E309549 T1 ATE309549 T1 AT E309549T1
Authority
AT
Austria
Prior art keywords
circuits
sub
clock signal
clock
gate
Prior art date
Application number
AT02791935T
Other languages
English (en)
Inventor
Hubertus G H Vermeulen
Sandeep K Goel
Original Assignee
Koninkl Philips Electronics Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv filed Critical Koninkl Philips Electronics Nv
Application granted granted Critical
Publication of ATE309549T1 publication Critical patent/ATE309549T1/de

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318552—Clock circuits details
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558—Addressing or selecting of subparts of the device under test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318583—Design for test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318594—Timing aspects

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Logic Circuits (AREA)
AT02791935T 2002-01-28 2002-12-23 Testen von schaltungen mit mehreren taktsignal- domänen ATE309549T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP02075343 2002-01-28
PCT/IB2002/005706 WO2003065065A1 (en) 2002-01-28 2002-12-23 Testing of circuit with plural clock domains

Publications (1)

Publication Number Publication Date
ATE309549T1 true ATE309549T1 (de) 2005-11-15

Family

ID=27635844

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02791935T ATE309549T1 (de) 2002-01-28 2002-12-23 Testen von schaltungen mit mehreren taktsignal- domänen

Country Status (7)

Country Link
US (1) US7076709B2 (de)
EP (1) EP1472551B1 (de)
JP (1) JP3977334B2 (de)
CN (1) CN100360950C (de)
AT (1) ATE309549T1 (de)
DE (1) DE60207307T2 (de)
WO (1) WO2003065065A1 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7055117B2 (en) 2003-12-29 2006-05-30 Agere Systems, Inc. System and method for debugging system-on-chips using single or n-cycle stepping
US7627771B2 (en) * 2005-10-04 2009-12-01 International Business Machines Corporation Clock control hierarchy for integrated microprocessors and systems-on-a-chip
JP5160039B2 (ja) * 2006-02-10 2013-03-13 ルネサスエレクトロニクス株式会社 半導体装置及びそのテスト回路の追加方法
US20090228751A1 (en) * 2007-05-22 2009-09-10 Tilman Gloekler method for performing logic built-in-self-test cycles on a semiconductor chip and a corresponding semiconductor chip with a test engine
US7752586B2 (en) 2007-11-20 2010-07-06 International Business Machines Corporation Design structure of an integration circuit and test method of the integrated circuit
JP2009222644A (ja) * 2008-03-18 2009-10-01 Toshiba Corp 半導体集積回路、及び設計自動化システム
US8074133B2 (en) * 2008-08-06 2011-12-06 Oracle America, Inc. Method and apparatus for testing delay faults
JP2010091482A (ja) * 2008-10-09 2010-04-22 Toshiba Corp 半導体集積回路装置及びその遅延故障テスト方法
US7917823B2 (en) * 2008-12-30 2011-03-29 Intel Corporation Decoupled clocking in testing architecture and method of testing
JP2011007589A (ja) * 2009-06-25 2011-01-13 Renesas Electronics Corp テスト方法、テスト制御プログラム及び半導体装置
WO2017203656A1 (ja) * 2016-05-26 2017-11-30 オリンパス株式会社 演算装置、画像処理装置および画像処理方法
US10740515B1 (en) * 2018-12-18 2020-08-11 Cadence Design Systems, Inc. Devices and methods for test point insertion coverage
KR20220149220A (ko) 2021-04-30 2022-11-08 삼성전자주식회사 메모리 장치
CN115862052A (zh) * 2023-02-24 2023-03-28 北京芯愿景软件技术股份有限公司 一种自动识别跨时钟电路的方法、装置、设备及存储介质

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5673273A (en) * 1996-04-30 1997-09-30 Tektronix, Inc. Clock controller for embedded test
WO1998026301A1 (en) * 1996-12-13 1998-06-18 Koninklijke Philips Electronics N.V. Integrated circuit comprising a first and a second clock domain and a method for testing such a circuit
US5878055A (en) * 1997-12-09 1999-03-02 International Business Machines Corporation Method and apparatus for verifying a single phase clocking system including testing for latch early mode
CA2225879C (en) * 1997-12-29 2001-05-01 Jean-Francois Cote Clock skew management method and apparatus
EP0965850A1 (de) * 1998-06-17 1999-12-22 Lucent Technologies Inc. Verfahren zum Abtastprüfen für integrierten Schaltkreis mit Mehrfachtaktgeber
US6324652B1 (en) * 1999-01-15 2001-11-27 3Com Corporation Asynchronous switching circuit for multiple indeterminate bursting clocks
US6327684B1 (en) * 1999-05-11 2001-12-04 Logicvision, Inc. Method of testing at-speed circuits having asynchronous clocks and controller for use therewith
KR100448903B1 (ko) * 2000-01-28 2004-09-16 삼성전자주식회사 스캔신호 변환회로를 구비한 반도체 집적회로 장치

Also Published As

Publication number Publication date
DE60207307T2 (de) 2006-07-20
CN100360950C (zh) 2008-01-09
JP3977334B2 (ja) 2007-09-19
US20050076278A1 (en) 2005-04-07
EP1472551A1 (de) 2004-11-03
CN1618026A (zh) 2005-05-18
EP1472551B1 (de) 2005-11-09
DE60207307D1 (de) 2005-12-15
WO2003065065A1 (en) 2003-08-07
US7076709B2 (en) 2006-07-11
JP2005516227A (ja) 2005-06-02

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