ATE289088T1 - Kodierte takte zur verteilung von mehreren taktsignalen zu mehreren geräten eines rechnersystems - Google Patents

Kodierte takte zur verteilung von mehreren taktsignalen zu mehreren geräten eines rechnersystems

Info

Publication number
ATE289088T1
ATE289088T1 AT00989335T AT00989335T ATE289088T1 AT E289088 T1 ATE289088 T1 AT E289088T1 AT 00989335 T AT00989335 T AT 00989335T AT 00989335 T AT00989335 T AT 00989335T AT E289088 T1 ATE289088 T1 AT E289088T1
Authority
AT
Austria
Prior art keywords
encoded
clock signal
several
computer system
clocks
Prior art date
Application number
AT00989335T
Other languages
English (en)
Inventor
Drew G Doblar
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Application granted granted Critical
Publication of ATE289088T1 publication Critical patent/ATE289088T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/06—Clock generators producing several clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Manipulation Of Pulses (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Small-Scale Networks (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Information Transfer Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
AT00989335T 1999-12-30 2000-12-19 Kodierte takte zur verteilung von mehreren taktsignalen zu mehreren geräten eines rechnersystems ATE289088T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/476,721 US6614862B1 (en) 1999-12-30 1999-12-30 Encoded clocks to distribute multiple clock signals to multiple devices in a computer system
PCT/US2000/034602 WO2001050231A2 (en) 1999-12-30 2000-12-19 Encoded clocks to distribute multiple clock signals to multiple devices in a computer system

Publications (1)

Publication Number Publication Date
ATE289088T1 true ATE289088T1 (de) 2005-02-15

Family

ID=23892985

Family Applications (1)

Application Number Title Priority Date Filing Date
AT00989335T ATE289088T1 (de) 1999-12-30 2000-12-19 Kodierte takte zur verteilung von mehreren taktsignalen zu mehreren geräten eines rechnersystems

Country Status (8)

Country Link
US (2) US6614862B1 (de)
EP (1) EP1242860B1 (de)
JP (1) JP2003519426A (de)
KR (1) KR20020075382A (de)
AT (1) ATE289088T1 (de)
AU (1) AU2584801A (de)
DE (1) DE60018110T2 (de)
WO (1) WO2001050231A2 (de)

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JP2001267890A (ja) * 2000-03-22 2001-09-28 Hitachi Ltd クロック発生装置、バスインタフェース制御装置及び情報処理装置
US20020186787A1 (en) * 2001-05-19 2002-12-12 Fischer Michael Andrew Binary waveform divider
US7127631B2 (en) * 2002-03-28 2006-10-24 Advanced Analogic Technologies, Inc. Single wire serial interface utilizing count of encoded clock pulses with reset
US7051235B2 (en) * 2002-08-27 2006-05-23 Sun Microsystems, Inc. Clock distribution architecture having clock and power failure protection
BR0300100A (pt) * 2003-01-10 2004-10-13 Coppe Ufrj Relógio global distribuìdo para clusters de computadores
KR100541653B1 (ko) * 2003-10-16 2006-01-10 삼성전자주식회사 반도체 장치의 신호 송수신 방법
US7353437B2 (en) * 2004-10-29 2008-04-01 Micron Technology, Inc. System and method for testing a memory for a memory failure exhibited by a failing memory
JP4282658B2 (ja) * 2004-12-09 2009-06-24 エルピーダメモリ株式会社 半導体装置
US7478307B1 (en) 2005-05-19 2009-01-13 Sun Microsystems, Inc. Method for improving un-correctable errors in a computer system
US7555085B1 (en) 2005-08-23 2009-06-30 Sun Microsystems, Inc. CDR algorithms for improved high speed IO performance
US7636408B2 (en) * 2006-06-01 2009-12-22 Sun Microsystems, Inc. Reliable startup and steady-state of estimation based CDR and DFE
US8190942B2 (en) * 2008-07-02 2012-05-29 Cradle Ip, Llc Method and system for distributing a global timebase within a system-on-chip having multiple clock domains
US8218702B2 (en) * 2009-02-18 2012-07-10 Oracle America, Inc. System and method of adapting precursor tap coefficient
US8229020B2 (en) * 2009-03-23 2012-07-24 Oracle America, Inc. Integrated equalization and CDR adaptation engine with single error monitor circuit
US9261940B2 (en) * 2011-02-25 2016-02-16 Samsung Electronics Co., Ltd. Memory system controlling peak current generation for a plurality of memories by monitoring a peak signal to synchronize an internal clock of each memory by a processor clock at different times
DE102017109456A1 (de) * 2017-05-03 2018-11-08 Carl Zeiss Microscopy Gmbh Mikroskopsystem und Verfahren zum Betreiben eines Mikroskopsystems
KR102586562B1 (ko) * 2018-05-25 2023-10-11 주식회사 쏠리드 클럭 동기화를 수행하는 통신 노드 및 통신 시스템
US10871796B1 (en) * 2019-08-06 2020-12-22 Xilinx, Inc. Global clock and a leaf clock divider

Family Cites Families (15)

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Publication number Priority date Publication date Assignee Title
FR1527160A (fr) 1967-04-19 1968-05-31 Commissariat Energie Atomique Caisson en béton précontraint
US3725793A (en) 1971-12-15 1973-04-03 Bell Telephone Labor Inc Clock synchronization arrangement employing delay devices
FR2324180A1 (fr) * 1975-09-10 1977-04-08 Materiel Telephonique Systeme de transmission de signaux d'horloge et de signaux auxiliaires
DE3751571T2 (de) * 1986-05-20 1996-04-11 Mitsubishi Electric Corp Verfahren zur Synchronisation der Echtzeituhren in einem Datenübertragungssystem.
JPH07114348B2 (ja) 1987-12-11 1995-12-06 日本電気株式会社 論理回路
JPH07120225B2 (ja) 1988-04-15 1995-12-20 富士通株式会社 半導体回路装置
US4989175A (en) 1988-11-25 1991-01-29 Unisys Corp. High speed on-chip clock phase generating system
US5058132A (en) 1989-10-26 1991-10-15 National Semiconductor Corporation Clock distribution system and technique
US5307381A (en) 1991-12-27 1994-04-26 Intel Corporation Skew-free clock signal distribution network in a microprocessor
US5256994A (en) 1992-09-21 1993-10-26 Intel Corporation Programmable secondary clock generator
TW418329B (en) * 1994-08-24 2001-01-11 Ibm Integrated circuit clocking technique and circuit therefor
US5822381A (en) * 1995-05-05 1998-10-13 Silicon Graphics, Inc. Distributed global clock system
JP3085258B2 (ja) * 1997-09-10 2000-09-04 日本電気株式会社 クロック信号分配回路
JP3433071B2 (ja) * 1997-10-29 2003-08-04 富士通株式会社 クロック周波数同期装置
US6288589B1 (en) * 1997-11-20 2001-09-11 Intrinsity, Inc. Method and apparatus for generating clock signals

Also Published As

Publication number Publication date
US7065170B2 (en) 2006-06-20
KR20020075382A (ko) 2002-10-04
DE60018110D1 (de) 2005-03-17
US6614862B1 (en) 2003-09-02
AU2584801A (en) 2001-07-16
WO2001050231A3 (en) 2002-02-21
EP1242860A2 (de) 2002-09-25
JP2003519426A (ja) 2003-06-17
DE60018110T2 (de) 2006-01-05
WO2001050231A2 (en) 2001-07-12
EP1242860B1 (de) 2005-02-09
US20040013215A1 (en) 2004-01-22

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Legal Events

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RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties