ATE205614T1 - Parallele prüfung eines cpu-cachespeichers sowie befehlseinheit - Google Patents
Parallele prüfung eines cpu-cachespeichers sowie befehlseinheitInfo
- Publication number
- ATE205614T1 ATE205614T1 AT96921674T AT96921674T ATE205614T1 AT E205614 T1 ATE205614 T1 AT E205614T1 AT 96921674 T AT96921674 T AT 96921674T AT 96921674 T AT96921674 T AT 96921674T AT E205614 T1 ATE205614 T1 AT E205614T1
- Authority
- AT
- Austria
- Prior art keywords
- command unit
- cpu cache
- internal cache
- cache
- parallel checking
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
- G01R31/31905—Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Tests Of Electronic Circuits (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/491,157 US5539878A (en) | 1995-06-16 | 1995-06-16 | Parallel testing of CPU cache and instruction units |
PCT/US1996/010516 WO1997000478A1 (en) | 1995-06-16 | 1996-06-17 | Parallel testing of cpu cache and instruction units |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE205614T1 true ATE205614T1 (de) | 2001-09-15 |
Family
ID=23951026
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT96921674T ATE205614T1 (de) | 1995-06-16 | 1996-06-17 | Parallele prüfung eines cpu-cachespeichers sowie befehlseinheit |
Country Status (6)
Country | Link |
---|---|
US (2) | US5539878A (de) |
EP (1) | EP0834124B1 (de) |
JP (1) | JP3165158B2 (de) |
AT (1) | ATE205614T1 (de) |
DE (1) | DE69615187T2 (de) |
WO (1) | WO1997000478A1 (de) |
Families Citing this family (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5539878A (en) * | 1995-06-16 | 1996-07-23 | Elonex Technologies, Inc. | Parallel testing of CPU cache and instruction units |
US5680544A (en) * | 1995-09-05 | 1997-10-21 | Digital Equipment Corporation | Method for testing an on-chip cache for repair |
KR100230454B1 (ko) * | 1997-05-28 | 1999-11-15 | 윤종용 | 다중처리 시스템의 캐시메모리 검사방법 |
US6748492B1 (en) | 2000-08-07 | 2004-06-08 | Broadcom Corporation | Deterministic setting of replacement policy in a cache through way selection |
US6732234B1 (en) * | 2000-08-07 | 2004-05-04 | Broadcom Corporation | Direct access mode for a cache |
US6848024B1 (en) | 2000-08-07 | 2005-01-25 | Broadcom Corporation | Programmably disabling one or more cache entries |
TW591378B (en) * | 2001-02-22 | 2004-06-11 | Hitachi Ltd | Memory test method, information recording medium and semiconductor integrated circuit |
US6748495B2 (en) | 2001-05-15 | 2004-06-08 | Broadcom Corporation | Random generator |
US7266587B2 (en) * | 2002-05-15 | 2007-09-04 | Broadcom Corporation | System having interfaces, switch, and memory bridge for CC-NUMA operation |
DE602007010039D1 (de) * | 2007-02-16 | 2010-12-02 | Freescale Semiconductor Inc | System und rechnerprogrammprodukt zum testen einer logischen schaltung |
US20090055805A1 (en) * | 2007-08-24 | 2009-02-26 | International Business Machines Corporation | Method and System for Testing Software |
JP5293062B2 (ja) * | 2008-10-03 | 2013-09-18 | 富士通株式会社 | コンピュータ装置、メモリ診断方法、及びメモリ診断制御プログラム |
JP5509568B2 (ja) * | 2008-10-03 | 2014-06-04 | 富士通株式会社 | コンピュータ装置、プロセッサ診断方法、及びプロセッサ診断制御プログラム |
US8136001B2 (en) * | 2009-06-05 | 2012-03-13 | Freescale Semiconductor, Inc. | Technique for initializing data and instructions for core functional pattern generation in multi-core processor |
JP6662566B2 (ja) | 2011-06-02 | 2020-03-11 | プレジデント・アンド・フェロウズ・オブ・ハーバード・カレッジ | エキソビボ組織培養システムのための方法および使用 |
US8769355B2 (en) | 2011-06-27 | 2014-07-01 | Freescale Semiconductor, Inc. | Using built-in self test for preventing side channel security attacks on multi-processor systems |
WO2013003112A1 (en) | 2011-06-27 | 2013-01-03 | The Jackson Laboratory | Methods and compositions for treatment of cancer and autoimmune disease |
US9448942B2 (en) | 2012-08-20 | 2016-09-20 | Freescale Semiconductor, Inc. | Random access of a cache portion using an access module |
US9092622B2 (en) | 2012-08-20 | 2015-07-28 | Freescale Semiconductor, Inc. | Random timeslot controller for enabling built-in self test module |
CA2974369A1 (en) | 2015-01-20 | 2016-07-28 | The Children's Medical Center Corporation | Anti-net compounds for treating and preventing fibrosis and for facilitating wound healing |
JP5956040B1 (ja) | 2015-09-07 | 2016-07-20 | Dmg森精機株式会社 | 工作機械 |
US9542290B1 (en) | 2016-01-29 | 2017-01-10 | International Business Machines Corporation | Replicating test case data into a cache with non-naturally aligned data boundaries |
US10169180B2 (en) | 2016-05-11 | 2019-01-01 | International Business Machines Corporation | Replicating test code and test data into a cache with non-naturally aligned data boundaries |
KR102562067B1 (ko) * | 2016-05-23 | 2023-08-01 | 주식회사 디엔솔루션즈 | 롱보링바 매거진 및 이를 포함하는 공작기계 |
US10055320B2 (en) * | 2016-07-12 | 2018-08-21 | International Business Machines Corporation | Replicating test case data into a cache and cache inhibited memory |
US10223225B2 (en) | 2016-11-07 | 2019-03-05 | International Business Machines Corporation | Testing speculative instruction execution with test cases placed in memory segments with non-naturally aligned data boundaries |
US10261878B2 (en) | 2017-03-14 | 2019-04-16 | International Business Machines Corporation | Stress testing a processor memory with a link stack |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4553201A (en) * | 1983-03-28 | 1985-11-12 | Honeywell Information Systems Inc. | Decoupling apparatus for verification of a processor independent from an associated data processing system |
US4891811A (en) * | 1987-02-13 | 1990-01-02 | International Business Machines Corporation | Efficient address test for large memories |
WO1989000728A1 (en) * | 1987-07-17 | 1989-01-26 | Ivor Catt | Integrated circuits |
US5155844A (en) * | 1990-02-14 | 1992-10-13 | International Business Machines Corporation | Background memory test during system start up |
US5398325A (en) * | 1992-05-07 | 1995-03-14 | Sun Microsystems, Inc. | Methods and apparatus for improving cache consistency using a single copy of a cache tag memory in multiple processor computer systems |
US5479413A (en) * | 1994-06-06 | 1995-12-26 | Digital Equipment Corporation | Method for testing large memory arrays during system initialization |
US5539878A (en) * | 1995-06-16 | 1996-07-23 | Elonex Technologies, Inc. | Parallel testing of CPU cache and instruction units |
-
1995
- 1995-06-16 US US08/491,157 patent/US5539878A/en not_active Expired - Lifetime
-
1996
- 1996-06-17 WO PCT/US1996/010516 patent/WO1997000478A1/en active IP Right Grant
- 1996-06-17 JP JP50340397A patent/JP3165158B2/ja not_active Expired - Fee Related
- 1996-06-17 AT AT96921674T patent/ATE205614T1/de not_active IP Right Cessation
- 1996-06-17 EP EP96921674A patent/EP0834124B1/de not_active Expired - Lifetime
- 1996-06-17 DE DE69615187T patent/DE69615187T2/de not_active Expired - Fee Related
- 1996-07-23 US US08/685,041 patent/US5940588A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP3165158B2 (ja) | 2001-05-14 |
DE69615187D1 (de) | 2001-10-18 |
DE69615187T2 (de) | 2002-07-04 |
EP0834124A4 (de) | 2000-04-19 |
EP0834124A1 (de) | 1998-04-08 |
EP0834124B1 (de) | 2001-09-12 |
WO1997000478A1 (en) | 1997-01-03 |
US5539878A (en) | 1996-07-23 |
JPH10511790A (ja) | 1998-11-10 |
US5940588A (en) | 1999-08-17 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
UEP | Publication of translation of european patent specification | ||
REN | Ceased due to non-payment of the annual fee |