ATE200715T1 - Verbesserung eines herstellungsverfahrens einer speicherkarte - Google Patents

Verbesserung eines herstellungsverfahrens einer speicherkarte

Info

Publication number
ATE200715T1
ATE200715T1 AT96946394T AT96946394T ATE200715T1 AT E200715 T1 ATE200715 T1 AT E200715T1 AT 96946394 T AT96946394 T AT 96946394T AT 96946394 T AT96946394 T AT 96946394T AT E200715 T1 ATE200715 T1 AT E200715T1
Authority
AT
Austria
Prior art keywords
cavity
adhesion means
module
improvement
production method
Prior art date
Application number
AT96946394T
Other languages
English (en)
Inventor
Vincent Permingeat
Original Assignee
Gemplus Card Int
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gemplus Card Int filed Critical Gemplus Card Int
Application granted granted Critical
Publication of ATE200715T1 publication Critical patent/ATE200715T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07743—External electrical contacts
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07745—Mounting details of integrated circuit chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01087—Francium [Fr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Credit Cards Or The Like (AREA)
  • Multi-Process Working Machines And Systems (AREA)
  • Diaphragms For Electromechanical Transducers (AREA)
  • Adornments (AREA)
AT96946394T 1996-08-05 1996-08-05 Verbesserung eines herstellungsverfahrens einer speicherkarte ATE200715T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
PCT/FR1996/001246 WO1998006062A1 (fr) 1996-08-05 1996-08-05 Perfectionnement a un procede de realisation de cartes a memoire et cartes ainsi obtenues
CA 2262481 CA2262481A1 (fr) 1996-08-05 1996-08-05 Perfectionnement a un procede de realisation de cartes a memoire et cartes ainsi obtenues

Publications (1)

Publication Number Publication Date
ATE200715T1 true ATE200715T1 (de) 2001-05-15

Family

ID=25680827

Family Applications (1)

Application Number Title Priority Date Filing Date
AT96946394T ATE200715T1 (de) 1996-08-05 1996-08-05 Verbesserung eines herstellungsverfahrens einer speicherkarte

Country Status (9)

Country Link
US (1) US6223989B1 (de)
EP (1) EP0917687B1 (de)
JP (1) JP2001505329A (de)
AT (1) ATE200715T1 (de)
AU (1) AU707828B2 (de)
CA (1) CA2262481A1 (de)
DE (1) DE69612574T2 (de)
ES (1) ES2159061T3 (de)
WO (1) WO1998006062A1 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3687783B2 (ja) * 1997-11-04 2005-08-24 エルケ ツァケル コンタクトレスチップカードを製造する方法およびコンタクトレスチップカード
FR2793330B1 (fr) * 1999-05-06 2001-08-10 Oberthur Card Systems Sas Procede de montage d'un microcircuit dans une cavite d'une carte formant support et carte ainsi obtenue
FR2800087A1 (fr) * 1999-10-26 2001-04-27 Gemplus Card Int Procede et moyens pour l'amelioration du collage entre materiaux polymeres, notamment pour carte a puce
FR2801709B1 (fr) * 1999-11-29 2002-02-15 A S K Carte a puce sans contact ou hybride contact-sans contact permettant de limiter les risques de fraude
FR2801708B1 (fr) 1999-11-29 2003-12-26 A S K Procede de fabrication d'une carte a puce sans contact avec un support d'antenne en materiau fibreux
FR2823888B1 (fr) * 2001-04-24 2005-02-18 Gemplus Card Int Procede de fabrication d'une carte sans contact ou hybride et carte obtenue
DE102006050564A1 (de) 2006-10-26 2008-04-30 Grönemeyer Medical GmbH & Co. KG Modulare Operationstischauflage
FR2968432B1 (fr) * 2010-12-06 2012-12-28 Oberthur Technologies Procédé d'encartage d'un module dans une carte a microcircuit
US20120304531A1 (en) 2011-05-30 2012-12-06 Shell Oil Company Liquid fuel compositions
US8649820B2 (en) 2011-11-07 2014-02-11 Blackberry Limited Universal integrated circuit card apparatus and related methods
USD703208S1 (en) 2012-04-13 2014-04-22 Blackberry Limited UICC apparatus
US8936199B2 (en) 2012-04-13 2015-01-20 Blackberry Limited UICC apparatus and related methods
USD701864S1 (en) 2012-04-23 2014-04-01 Blackberry Limited UICC apparatus
DE102019200659A1 (de) * 2019-01-18 2020-07-23 Te Connectivity Germany Gmbh Elektrische Verbindungsanordnung mit zwei verschweißten Leitern und einer Schicht Cyanacrylat-Klebstoff zwischen den Leitern sowie Verfahren hierzu
CN110126261B (zh) * 2019-06-11 2021-04-13 深圳市深科达智能装备股份有限公司 显示或触控模组3d打印胶层方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2579799B1 (fr) * 1985-03-28 1990-06-22 Flonic Sa Procede de fabrication de cartes a memoire electronique et cartes obtenues suivant ledit procede
US4871405A (en) * 1988-03-30 1989-10-03 Director General, Agency Of Industrial Science And Technology Method of bonding a semiconductor to a package with a low and high viscosity bonding agent
US4903118A (en) * 1988-03-30 1990-02-20 Director General, Agency Of Industrial Science And Technology Semiconductor device including a resilient bonding resin
US5169056A (en) * 1992-02-21 1992-12-08 Eastman Kodak Company Connecting of semiconductor chips to circuit substrates
US5776278A (en) * 1992-06-17 1998-07-07 Micron Communications, Inc. Method of manufacturing an enclosed transceiver
DE4229639C1 (de) * 1992-09-04 1993-12-09 Tomas Meinen Verfahren und Vorrichtung zur Herstellung von IC-Karten
JPH07117385A (ja) * 1993-09-01 1995-05-09 Toshiba Corp 薄型ｉｃカードおよび薄型ｉｃカードの製造方法
DE4444789C3 (de) * 1994-12-15 2001-05-10 Ods Landis & Gyr Gmbh & Co Kg Verfahren zum Herstellen von Chipkarten, Chipkarte und Vorrichtung zum Durchführen des Verfahrens
US5671525A (en) * 1995-02-13 1997-09-30 Gemplus Card International Method of manufacturing a hybrid chip card

Also Published As

Publication number Publication date
ES2159061T3 (es) 2001-09-16
EP0917687B1 (de) 2001-04-18
CA2262481A1 (fr) 1998-02-12
US6223989B1 (en) 2001-05-01
JP2001505329A (ja) 2001-04-17
WO1998006062A1 (fr) 1998-02-12
AU4688097A (en) 1998-02-25
AU707828B2 (en) 1999-07-22
DE69612574T2 (de) 2001-10-18
EP0917687A1 (de) 1999-05-26
DE69612574D1 (de) 2001-05-23

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Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties