ATE156609T1 - Verfahren und anordnung zur kontrolle der umwandlung virtueller adressen in physikalische adressen in einem computersystem - Google Patents

Verfahren und anordnung zur kontrolle der umwandlung virtueller adressen in physikalische adressen in einem computersystem

Info

Publication number
ATE156609T1
ATE156609T1 AT90300954T AT90300954T ATE156609T1 AT E156609 T1 ATE156609 T1 AT E156609T1 AT 90300954 T AT90300954 T AT 90300954T AT 90300954 T AT90300954 T AT 90300954T AT E156609 T1 ATE156609 T1 AT E156609T1
Authority
AT
Austria
Prior art keywords
translation buffer
memory
virtual
physical
addresses
Prior art date
Application number
AT90300954T
Other languages
German (de)
English (en)
Inventor
Ricky C Hetherington
David A Webb Jr
David B Fite
John E Murray
Tryggve Fossum
Dwight P Manley
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Application granted granted Critical
Publication of ATE156609T1 publication Critical patent/ATE156609T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
  • Image Input (AREA)
AT90300954T 1989-02-03 1990-01-30 Verfahren und anordnung zur kontrolle der umwandlung virtueller adressen in physikalische adressen in einem computersystem ATE156609T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US30654489A 1989-02-03 1989-02-03
AU53950/90A AU632558B2 (en) 1989-02-03 1990-04-27 Method and apparatus for controlling the conversion of virtual to physical memory addresses in a digital computer system

Publications (1)

Publication Number Publication Date
ATE156609T1 true ATE156609T1 (de) 1997-08-15

Family

ID=25630274

Family Applications (1)

Application Number Title Priority Date Filing Date
AT90300954T ATE156609T1 (de) 1989-02-03 1990-01-30 Verfahren und anordnung zur kontrolle der umwandlung virtueller adressen in physikalische adressen in einem computersystem

Country Status (7)

Country Link
US (1) US5349651A (enExample)
EP (1) EP0381447B1 (enExample)
JP (1) JPH02232753A (enExample)
AT (1) ATE156609T1 (enExample)
AU (1) AU632558B2 (enExample)
CA (1) CA1325288C (enExample)
DE (1) DE69031183T2 (enExample)

Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6336180B1 (en) 1997-04-30 2002-01-01 Canon Kabushiki Kaisha Method, apparatus and system for managing virtual memory with virtual-physical mapping
US5423014A (en) * 1991-10-29 1995-06-06 Intel Corporation Instruction fetch unit with early instruction fetch mechanism
JPH0667980A (ja) * 1992-05-12 1994-03-11 Unisys Corp ４ブロックキャッシュメモリへのアクセスを最適化するためのキャッシュ論理システムおよびメインフレームコンピュータの高速キャッシュメモリへのアクセス時のダブルミスを防ぐ方法
US5586291A (en) * 1994-12-23 1996-12-17 Emc Corporation Disk controller with volatile and non-volatile cache memories
DE69616718D1 (de) * 1995-05-26 2001-12-13 Nat Semiconductor Corp Vorrichtung und verfahren zur bestimmung von adressen fehlausgerichteter daten
US6061773A (en) * 1996-05-03 2000-05-09 Digital Equipment Corporation Virtual memory system with page table space separating a private space and a shared space in a virtual memory
US5960463A (en) * 1996-05-16 1999-09-28 Advanced Micro Devices, Inc. Cache controller with table walk logic tightly coupled to second level access logic
US6175906B1 (en) * 1996-12-06 2001-01-16 Advanced Micro Devices, Inc. Mechanism for fast revalidation of virtual tags
AUPO648397A0 (en) 1997-04-30 1997-05-22 Canon Information Systems Research Australia Pty Ltd Improvements in multiprocessor architecture operation
US6414687B1 (en) 1997-04-30 2002-07-02 Canon Kabushiki Kaisha Register setting-micro programming system
US6707463B1 (en) 1997-04-30 2004-03-16 Canon Kabushiki Kaisha Data normalization technique
US6289138B1 (en) 1997-04-30 2001-09-11 Canon Kabushiki Kaisha General image processor
AUPO647997A0 (en) * 1997-04-30 1997-05-22 Canon Information Systems Research Australia Pty Ltd Memory controller architecture
US6246396B1 (en) 1997-04-30 2001-06-12 Canon Kabushiki Kaisha Cached color conversion method and apparatus
US6061749A (en) * 1997-04-30 2000-05-09 Canon Kabushiki Kaisha Transformation of a first dataword received from a FIFO into an input register and subsequent dataword from the FIFO into a normalized output dataword
KR100231707B1 (ko) * 1997-08-04 2000-01-15 정선종 통신 장비의 디엠에이 처리 방법 및 그 장치
US6157986A (en) * 1997-12-16 2000-12-05 Advanced Micro Devices, Inc. Fast linear tag validation unit for use in microprocessor
US6263408B1 (en) * 1999-03-31 2001-07-17 International Business Machines Corporation Method and apparatus for implementing automatic cache variable update
US6233668B1 (en) 1999-10-27 2001-05-15 Compaq Computer Corporation Concurrent page tables
US6628294B1 (en) 1999-12-31 2003-09-30 Intel Corporation Prefetching of virtual-to-physical address translation for display data
US6615300B1 (en) * 2000-06-19 2003-09-02 Transmeta Corporation Fast look-up of indirect branch destination in a dynamic translation system
US9131899B2 (en) 2011-07-06 2015-09-15 Apple Inc. Efficient handling of misaligned loads and stores
US7404064B2 (en) * 2004-04-07 2008-07-22 Stmicroelectronics S.A. Method and device for calculating addresses of a segmented program memory
US10621092B2 (en) 2008-11-24 2020-04-14 Intel Corporation Merging level cache and data cache units having indicator bits related to speculative execution
US9672019B2 (en) 2008-11-24 2017-06-06 Intel Corporation Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads
US8775153B2 (en) * 2009-12-23 2014-07-08 Intel Corporation Transitioning from source instruction set architecture (ISA) code to translated code in a partial emulation environment
US9921967B2 (en) * 2011-07-26 2018-03-20 Intel Corporation Multi-core shared page miss handler
WO2013048468A1 (en) 2011-09-30 2013-04-04 Intel Corporation Instruction and logic to perform dynamic binary translation
US9292453B2 (en) 2013-02-01 2016-03-22 International Business Machines Corporation Storing a system-absolute address (SAA) in a first level translation look-aside buffer (TLB)
US9405551B2 (en) 2013-03-12 2016-08-02 Intel Corporation Creating an isolated execution environment in a co-designed processor
US9891936B2 (en) 2013-09-27 2018-02-13 Intel Corporation Method and apparatus for page-level monitoring
KR102329269B1 (ko) * 2013-10-21 2021-11-22 에프엘씨 글로벌 리미티드 최종 레벨 캐시 시스템 및 이에 대응하는 방법
CN116166179A (zh) * 2021-11-25 2023-05-26 华为技术有限公司 数据存储系统、智能网卡及计算节点
CN117971719B (zh) * 2024-03-28 2024-06-28 北京微核芯科技有限公司 一种提前传递数据的方法及其装置

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4264953A (en) * 1979-03-30 1981-04-28 Honeywell Inc. Virtual cache
US4654777A (en) * 1982-05-25 1987-03-31 Tokyo Shibaura Denki Kabushiki Kaisha Segmented one and two level paging address translation system
US4525778A (en) * 1982-05-25 1985-06-25 Massachusetts Computer Corporation Computer memory control
US4586130A (en) * 1983-10-03 1986-04-29 Digital Equipment Corporation Central processing unit for a digital computer
US4587610A (en) * 1984-02-10 1986-05-06 Prime Computer, Inc. Address translation systems for high speed computer memories
US4731740A (en) * 1984-06-30 1988-03-15 Kabushiki Kaisha Toshiba Translation lookaside buffer control system in computer or virtual memory control scheme
US4991081A (en) * 1984-10-31 1991-02-05 Texas Instruments Incorporated Cache memory addressable by both physical and virtual addresses
US4933835A (en) * 1985-02-22 1990-06-12 Intergraph Corporation Apparatus for maintaining consistency of a cache memory with a primary memory
US4774653A (en) * 1985-08-07 1988-09-27 Hewlett-Packard Company Hybrid hardware/software method and apparatus for virtual memory address translation using primary and secondary translation buffers
US5241638A (en) * 1985-08-12 1993-08-31 Ceridian Corporation Dual cache memory
US4694395A (en) * 1985-11-25 1987-09-15 Ncr Corporation System for performing virtual look-ahead memory operations
US4785398A (en) * 1985-12-19 1988-11-15 Honeywell Bull Inc. Virtual cache system using page level number generating CAM to access other memories for processing requests relating to a page
US5029072A (en) * 1985-12-23 1991-07-02 Motorola, Inc. Lock warning mechanism for a cache
US4727485A (en) * 1986-01-02 1988-02-23 Motorola, Inc. Paged memory management unit which locks translators in translation cache if lock specified in translation table
US4727486A (en) * 1986-05-02 1988-02-23 Honeywell Information Systems Inc. Hardware demand fetch cycle system interface
US5230045A (en) * 1986-11-12 1993-07-20 Xerox Corporation Multiple address space system including address translator for receiving virtual addresses from bus and providing real addresses on the bus
US4802085A (en) * 1987-01-22 1989-01-31 National Semiconductor Corporation Apparatus and method for detecting and handling memory-mapped I/O by a pipelined microprocessor
US4851991A (en) * 1987-02-24 1989-07-25 Digital Equipment Corporation Central processor unit for digital data processing system including write buffer management mechanism
US4831520A (en) * 1987-02-24 1989-05-16 Digital Equipment Corporation Bus interface circuit for digital data processor
US4825412A (en) * 1988-04-01 1989-04-25 Digital Equipment Corporation Lockout registers
US5239635A (en) * 1988-06-06 1993-08-24 Digital Equipment Corporation Virtual address to physical address translation using page tables in virtual memory

Also Published As

Publication number Publication date
DE69031183D1 (de) 1997-09-11
JPH02232753A (ja) 1990-09-14
CA1325288C (en) 1993-12-14
EP0381447B1 (en) 1997-08-06
JPH0564815B2 (enExample) 1993-09-16
DE69031183T2 (de) 1998-03-12
AU5395090A (en) 1991-12-19
US5349651A (en) 1994-09-20
EP0381447A3 (en) 1992-05-13
EP0381447A2 (en) 1990-08-08
AU632558B2 (en) 1993-01-07

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RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties