AT513649A3 - Method and apparatus for precise clock synchronization in a distributed computer system with a time signal line - Google Patents

Method and apparatus for precise clock synchronization in a distributed computer system with a time signal line Download PDF

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Publication number
AT513649A3
AT513649A3 ATA1223/2012A AT12232012A AT513649A3 AT 513649 A3 AT513649 A3 AT 513649A3 AT 12232012 A AT12232012 A AT 12232012A AT 513649 A3 AT513649 A3 AT 513649A3
Authority
AT
Austria
Prior art keywords
time signal
computer system
distributed computer
timer
signal line
Prior art date
Application number
ATA1223/2012A
Other languages
German (de)
Other versions
AT513649A2 (en
Original Assignee
Fts Computertechnik Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fts Computertechnik Gmbh filed Critical Fts Computertechnik Gmbh
Priority to ATA1223/2012A priority Critical patent/AT513649A3/en
Publication of AT513649A2 publication Critical patent/AT513649A2/en
Publication of AT513649A3 publication Critical patent/AT513649A3/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/08—Speed or phase control by synchronisation signals the synchronisation signals recurring cyclically
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0644—External master-clock

Abstract

Die vorliegende Erfindung legt ein innovatives Verfahren offen, wie in einem zeitgesteuerten verteilten Computersystem von einem Zeitgeber eine genaue Zeitbasis in den verteilten Komponenten des Systems bei einer minimalen Belastung der Komponenten und des Kommunikationssystems aufgebaut werden kann. Zu diesem Zweck werden neben den Nachrichtenkommunikationskanälen zwischen den Komponenten zusätzlich Zeitsignalleitungen realisiert. Der Uhrenstand wird von dem Zeitgeber mittels Synchronisationsnachrichten über das Nachrichtenkommunikationssystem den Endsystemen periodisch mitgeteilt. Der Uhrengang des Zeitgebers wird den Endsystemen durch periodische Zeitimpulse, die mit den Synchronisationsnachrichten synchronisiert sind, auf den zusätzlichen Zeitsignalleitungen übermittelt.The present invention discloses an innovative method of how, in a timed distributed computer system, a timer can establish an accurate time base in the distributed components of the system with minimal stress on the components and the communication system. In addition to the message communication channels between the components, additional time signal lines are realized for this purpose. The clock status is communicated periodically by the timer by means of synchronization messages via the message communication system to the end systems. The clock of the timer is transmitted to the end systems by periodic timing pulses synchronized with the synchronization messages on the additional time signal lines.

ATA1223/2012A 2012-11-16 2012-11-16 Method and apparatus for precise clock synchronization in a distributed computer system with a time signal line AT513649A3 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
ATA1223/2012A AT513649A3 (en) 2012-11-16 2012-11-16 Method and apparatus for precise clock synchronization in a distributed computer system with a time signal line

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
ATA1223/2012A AT513649A3 (en) 2012-11-16 2012-11-16 Method and apparatus for precise clock synchronization in a distributed computer system with a time signal line

Publications (2)

Publication Number Publication Date
AT513649A2 AT513649A2 (en) 2014-06-15
AT513649A3 true AT513649A3 (en) 2015-12-15

Family

ID=50885070

Family Applications (1)

Application Number Title Priority Date Filing Date
ATA1223/2012A AT513649A3 (en) 2012-11-16 2012-11-16 Method and apparatus for precise clock synchronization in a distributed computer system with a time signal line

Country Status (1)

Country Link
AT (1) AT513649A3 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE20121466U1 (en) * 2001-07-26 2003-02-27 Motorola Inc Clock synchronization for FlexRay (RTM) automotive communication system has node subset, message reception, time and clock rate deviation measurement, off-set and clock rate correction value calculation and node clock adjustment
WO2006007619A2 (en) * 2004-07-19 2006-01-26 Technische Universität Wien Decentralised fault-tolerant clock pulse generation in vlsi chips
WO2008139275A1 (en) * 2007-05-11 2008-11-20 Freescale Semiconductor, Inc. System and method for secure real time clocks

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE20121466U1 (en) * 2001-07-26 2003-02-27 Motorola Inc Clock synchronization for FlexRay (RTM) automotive communication system has node subset, message reception, time and clock rate deviation measurement, off-set and clock rate correction value calculation and node clock adjustment
WO2006007619A2 (en) * 2004-07-19 2006-01-26 Technische Universität Wien Decentralised fault-tolerant clock pulse generation in vlsi chips
WO2008139275A1 (en) * 2007-05-11 2008-11-20 Freescale Semiconductor, Inc. System and method for secure real time clocks

Also Published As

Publication number Publication date
AT513649A2 (en) 2014-06-15

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Effective date: 20160515