AT359561B - Schaltungsanordnung mit je einer eingangs- -ladungsverschiebe- und ausgangsstufe nach dem charge-coupled-device-prinzip - Google Patents

Schaltungsanordnung mit je einer eingangs- -ladungsverschiebe- und ausgangsstufe nach dem charge-coupled-device-prinzip

Info

Publication number
AT359561B
AT359561B AT819674A AT819674A AT359561B AT 359561 B AT359561 B AT 359561B AT 819674 A AT819674 A AT 819674A AT 819674 A AT819674 A AT 819674A AT 359561 B AT359561 B AT 359561B
Authority
AT
Austria
Prior art keywords
charge
circuit arrangement
output stage
coupled device
stage according
Prior art date
Application number
AT819674A
Other languages
German (de)
English (en)
Other versions
ATA819674A (de
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag filed Critical Siemens Ag
Publication of ATA819674A publication Critical patent/ATA819674A/de
Application granted granted Critical
Publication of AT359561B publication Critical patent/AT359561B/de

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C19/00Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/282Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements with charge storage in a depletion layer, i.e. charge coupled devices [CCD]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42396Gate electrodes for field effect devices for charge coupled devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/762Charge transfer devices
    • H01L29/765Charge-coupled devices
    • H01L29/768Charge-coupled devices with field effect produced by an insulated gate
    • H01L29/76808Input structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Solid State Image Pick-Up Elements (AREA)
AT819674A 1973-11-07 1974-10-11 Schaltungsanordnung mit je einer eingangs- -ladungsverschiebe- und ausgangsstufe nach dem charge-coupled-device-prinzip AT359561B (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19732355715 DE2355715B2 (de) 1973-11-07 1973-11-07 Ladungsverschiebeanordnung nach dem charge-coupled-device-prizip

Publications (2)

Publication Number Publication Date
ATA819674A ATA819674A (de) 1980-04-15
AT359561B true AT359561B (de) 1980-11-25

Family

ID=5897465

Family Applications (1)

Application Number Title Priority Date Filing Date
AT819674A AT359561B (de) 1973-11-07 1974-10-11 Schaltungsanordnung mit je einer eingangs- -ladungsverschiebe- und ausgangsstufe nach dem charge-coupled-device-prinzip

Country Status (11)

Country Link
JP (1) JPS5081076A (fr)
AT (1) AT359561B (fr)
BE (1) BE821949A (fr)
CA (1) CA1048154A (fr)
CH (1) CH587534A5 (fr)
DE (1) DE2355715B2 (fr)
FR (1) FR2250202B1 (fr)
GB (1) GB1471427A (fr)
IT (1) IT1025363B (fr)
NL (1) NL7414426A (fr)
SE (1) SE402173B (fr)

Also Published As

Publication number Publication date
DE2355715B2 (de) 1977-04-14
SE402173B (sv) 1978-06-19
FR2250202B1 (fr) 1979-02-23
FR2250202A1 (fr) 1975-05-30
JPS5081076A (fr) 1975-07-01
GB1471427A (en) 1977-04-27
BE821949A (fr) 1975-03-03
CH587534A5 (fr) 1977-05-13
IT1025363B (it) 1978-08-10
ATA819674A (de) 1980-04-15
CA1048154A (fr) 1979-02-06
NL7414426A (nl) 1975-05-12
SE7413860L (fr) 1975-05-09
DE2355715A1 (de) 1975-05-22

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Legal Events

Date Code Title Description
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