AT292069B - Circuit arrangement for memory - Google Patents

Circuit arrangement for memory

Info

Publication number
AT292069B
AT292069B AT995568A AT995568A AT292069B AT 292069 B AT292069 B AT 292069B AT 995568 A AT995568 A AT 995568A AT 995568 A AT995568 A AT 995568A AT 292069 B AT292069 B AT 292069B
Authority
AT
Austria
Prior art keywords
memory
circuit arrangement
arrangement
circuit
Prior art date
Application number
AT995568A
Other languages
German (de)
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE19671549053 external-priority patent/DE1549053B2/en
Application filed by Siemens Ag filed Critical Siemens Ag
Application granted granted Critical
Publication of AT292069B publication Critical patent/AT292069B/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
AT995568A 1967-10-13 1968-10-11 Circuit arrangement for memory AT292069B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19671549053 DE1549053B2 (en) 1967-10-13 1967-10-13 Circuit arrangement for monitoring write-in processes in memories

Publications (1)

Publication Number Publication Date
AT292069B true AT292069B (en) 1971-08-10

Family

ID=5676611

Family Applications (1)

Application Number Title Priority Date Filing Date
AT995568A AT292069B (en) 1967-10-13 1968-10-11 Circuit arrangement for memory

Country Status (3)

Country Link
AT (1) AT292069B (en)
BE (1) BE722204A (en)
FR (1) FR1588320A (en)

Also Published As

Publication number Publication date
FR1588320A (en) 1970-04-10
BE722204A (en) 1969-04-11

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Legal Events

Date Code Title Description
ELJ Ceased due to non-payment of the annual fee