AT273544B - Circuit arrangement for a digital buffer memory - Google Patents

Circuit arrangement for a digital buffer memory

Info

Publication number
AT273544B
AT273544B AT131268A AT131268A AT273544B AT 273544 B AT273544 B AT 273544B AT 131268 A AT131268 A AT 131268A AT 131268 A AT131268 A AT 131268A AT 273544 B AT273544 B AT 273544B
Authority
AT
Austria
Prior art keywords
buffer memory
circuit arrangement
digital buffer
digital
arrangement
Prior art date
Application number
AT131268A
Other languages
German (de)
Inventor
Claus Dipl Ing Tellar
Original Assignee
Kapsch Telephon Telegraph
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kapsch Telephon Telegraph filed Critical Kapsch Telephon Telegraph
Priority to AT131268A priority Critical patent/AT273544B/en
Priority to DE19681774563 priority patent/DE1774563A1/en
Application granted granted Critical
Publication of AT273544B publication Critical patent/AT273544B/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/4067—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the bipolar type

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Electronic Switches (AREA)
AT131268A 1968-02-12 1968-02-12 Circuit arrangement for a digital buffer memory AT273544B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
AT131268A AT273544B (en) 1968-02-12 1968-02-12 Circuit arrangement for a digital buffer memory
DE19681774563 DE1774563A1 (en) 1968-02-12 1968-07-16 Circuit arrangement for a digital buffer memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
AT131268A AT273544B (en) 1968-02-12 1968-02-12 Circuit arrangement for a digital buffer memory

Publications (1)

Publication Number Publication Date
AT273544B true AT273544B (en) 1969-08-11

Family

ID=3511158

Family Applications (1)

Application Number Title Priority Date Filing Date
AT131268A AT273544B (en) 1968-02-12 1968-02-12 Circuit arrangement for a digital buffer memory

Country Status (2)

Country Link
AT (1) AT273544B (en)
DE (1) DE1774563A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4259731A (en) * 1979-11-14 1981-03-31 Motorola, Inc. Quiet row selection circuitry

Also Published As

Publication number Publication date
DE1774563A1 (en) 1972-03-09

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