AR244896A1 - Aparato para controlar la ejecucion de instrucciones en forma canalizada. - Google Patents

Aparato para controlar la ejecucion de instrucciones en forma canalizada.

Info

Publication number
AR244896A1
AR244896A1 AR90317264A AR31726490A AR244896A1 AR 244896 A1 AR244896 A1 AR 244896A1 AR 90317264 A AR90317264 A AR 90317264A AR 31726490 A AR31726490 A AR 31726490A AR 244896 A1 AR244896 A1 AR 244896A1
Authority
AR
Argentina
Prior art keywords
management apparatus
apparatus included
processing unit
pipelined processing
logic management
Prior art date
Application number
AR90317264A
Other languages
English (en)
Original Assignee
Bull Hn Information Syst
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bull Hn Information Syst filed Critical Bull Hn Information Syst
Application granted granted Critical
Publication of AR244896A1 publication Critical patent/AR244896A1/es

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3818—Decoding for concurrent execution
    • G06F9/3822—Parallel decoding, e.g. parallel decode units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G06F9/3873—Variable length pipelines, e.g. elastic pipeline
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3889—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
AR90317264A 1989-06-30 1990-06-28 Aparato para controlar la ejecucion de instrucciones en forma canalizada. AR244896A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/374,881 US5150468A (en) 1989-06-30 1989-06-30 State controlled instruction logic management apparatus included in a pipelined processing unit

Publications (1)

Publication Number Publication Date
AR244896A1 true AR244896A1 (es) 1993-11-30

Family

ID=23478566

Family Applications (1)

Application Number Title Priority Date Filing Date
AR90317264A AR244896A1 (es) 1989-06-30 1990-06-28 Aparato para controlar la ejecucion de instrucciones en forma canalizada.

Country Status (5)

Country Link
US (1) US5150468A (es)
EP (1) EP0405495B1 (es)
AR (1) AR244896A1 (es)
DE (1) DE69033131T2 (es)
PT (1) PT94556A (es)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5280595A (en) * 1990-10-05 1994-01-18 Bull Hn Information Systems Inc. State machine for executing commands within a minimum number of cycles by accomodating unforseen time dependency according to status signals received from different functional sections
JP2532300B2 (ja) * 1990-10-17 1996-09-11 三菱電機株式会社 並列処理装置における命令供給装置
US5459845A (en) * 1990-12-20 1995-10-17 Intel Corporation Instruction pipeline sequencer in which state information of an instruction travels through pipe stages until the instruction execution is completed
US5574872A (en) * 1991-12-10 1996-11-12 Intel Corporation Method and apparatus for controlling the saving of pipelines in pipelined processors during trap handling
US5848289A (en) * 1992-11-27 1998-12-08 Motorola, Inc. Extensible central processing unit
US5542059A (en) * 1994-01-11 1996-07-30 Exponential Technology, Inc. Dual instruction set processor having a pipeline with a pipestage functional unit that is relocatable in time and sequence order
US5884057A (en) * 1994-01-11 1999-03-16 Exponential Technology, Inc. Temporal re-alignment of a floating point pipeline to an integer pipeline for emulation of a load-operate architecture on a load/store processor
US5673426A (en) * 1995-02-14 1997-09-30 Hal Computer Systems, Inc. Processor structure and method for tracking floating-point exceptions
US5835753A (en) * 1995-04-12 1998-11-10 Advanced Micro Devices, Inc. Microprocessor with dynamically extendable pipeline stages and a classifying circuit
US5797019A (en) * 1995-10-02 1998-08-18 International Business Machines Corporation Method and system for performance monitoring time lengths of disabled interrupts in a processing system
US5691920A (en) * 1995-10-02 1997-11-25 International Business Machines Corporation Method and system for performance monitoring of dispatch unit efficiency in a processing system
US5752062A (en) * 1995-10-02 1998-05-12 International Business Machines Corporation Method and system for performance monitoring through monitoring an order of processor events during execution in a processing system
US5949971A (en) * 1995-10-02 1999-09-07 International Business Machines Corporation Method and system for performance monitoring through identification of frequency and length of time of execution of serialization instructions in a processing system
US5729726A (en) * 1995-10-02 1998-03-17 International Business Machines Corporation Method and system for performance monitoring efficiency of branch unit operation in a processing system
US5751945A (en) * 1995-10-02 1998-05-12 International Business Machines Corporation Method and system for performance monitoring stalls to identify pipeline bottlenecks and stalls in a processing system
US5748855A (en) * 1995-10-02 1998-05-05 Iinternational Business Machines Corporation Method and system for performance monitoring of misaligned memory accesses in a processing system
US6003126A (en) * 1997-07-01 1999-12-14 International Business Machines Special instruction register including allocation field utilized for temporary designation of physical registers as general registers
US8082467B2 (en) * 2009-12-23 2011-12-20 International Business Machines Corporation Triggering workaround capabilities based on events active in a processor pipeline
US9104399B2 (en) * 2009-12-23 2015-08-11 International Business Machines Corporation Dual issuing of complex instruction set instructions
US9135005B2 (en) * 2010-01-28 2015-09-15 International Business Machines Corporation History and alignment based cracking for store multiple instructions for optimizing operand store compare penalties
US8495341B2 (en) * 2010-02-17 2013-07-23 International Business Machines Corporation Instruction length based cracking for instruction of variable length storage operands
US8938605B2 (en) * 2010-03-05 2015-01-20 International Business Machines Corporation Instruction cracking based on machine state
US8464030B2 (en) 2010-04-09 2013-06-11 International Business Machines Corporation Instruction cracking and issue shortening based on instruction base fields, index fields, operand fields, and various other instruction text bits
US8645669B2 (en) 2010-05-05 2014-02-04 International Business Machines Corporation Cracking destructively overlapping operands in variable length instructions
CN113760364B (zh) * 2020-06-03 2022-06-17 广东高云半导体科技股份有限公司 逻辑器件的控制器

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4179736A (en) * 1977-11-22 1979-12-18 Honeywell Information Systems Inc. Microprogrammed computer control unit capable of efficiently executing a large repertoire of instructions for a high performance data processing unit
US4200927A (en) * 1978-01-03 1980-04-29 International Business Machines Corporation Multi-instruction stream branch processing mechanism
US4519033A (en) * 1982-08-02 1985-05-21 Motorola, Inc. Control state sequencer
WO1985000453A1 (en) * 1983-07-11 1985-01-31 Prime Computer, Inc. Data processing system
US4685058A (en) * 1983-08-29 1987-08-04 Amdahl Corporation Two-stage pipelined execution unit and control stores
GB8421066D0 (en) * 1984-08-18 1984-09-19 Int Computers Ltd Microprogram control
JPS61110256A (ja) * 1984-11-02 1986-05-28 Hitachi Ltd 複数の演算部を有するプロセツサ
CA1250667A (en) * 1985-04-15 1989-02-28 Larry D. Larsen Branch control in a three phase pipelined signal processor
US4714994A (en) * 1985-04-30 1987-12-22 International Business Machines Corp. Instruction prefetch buffer control
US4890218A (en) * 1986-07-02 1989-12-26 Raytheon Company Variable length instruction decoding apparatus having cross coupled first and second microengines
JPS6398737A (ja) * 1986-10-15 1988-04-30 Mitsubishi Electric Corp デ−タ処理装置
JP2695157B2 (ja) * 1986-12-29 1997-12-24 松下電器産業株式会社 可変パイプラインプロセッサ
US4855947A (en) * 1987-05-27 1989-08-08 Amdahl Corporation Microprogrammable pipeline interlocks based on the validity of pipeline states
US4894772A (en) * 1987-07-31 1990-01-16 Prime Computer, Inc. Method and apparatus for qualifying branch cache entries

Also Published As

Publication number Publication date
DE69033131D1 (de) 1999-07-08
EP0405495B1 (en) 1999-06-02
DE69033131T2 (de) 2000-02-03
US5150468A (en) 1992-09-22
EP0405495A3 (en) 1992-07-22
EP0405495A2 (en) 1991-01-02
PT94556A (pt) 1992-03-31

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