AR013943A1 - TIMER GENERATOR AND SYSTEM TO GENERATE A TIMING SIGNAL TO BE USED IN A NETWORK OF DATA COMMUNICATIONS, AND METHOD TO CONTROL THE TIMING OF A DATA TRANSMISSION SYSTEM - Google Patents

TIMER GENERATOR AND SYSTEM TO GENERATE A TIMING SIGNAL TO BE USED IN A NETWORK OF DATA COMMUNICATIONS, AND METHOD TO CONTROL THE TIMING OF A DATA TRANSMISSION SYSTEM

Info

Publication number
AR013943A1
AR013943A1 ARP980104014A AR013943A1 AR 013943 A1 AR013943 A1 AR 013943A1 AR P980104014 A ARP980104014 A AR P980104014A AR 013943 A1 AR013943 A1 AR 013943A1
Authority
AR
Argentina
Prior art keywords
timing
network
timing signal
generate
control
Prior art date
Application number
Other languages
Spanish (es)
Original Assignee
Dsc Telecom Lp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dsc Telecom Lp filed Critical Dsc Telecom Lp
Publication of AR013943A1 publication Critical patent/AR013943A1/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H04J3/0688—Change of the master or reference, e.g. take-over or failure of the master
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H04J3/0691—Synchronisation in a TDM node

Abstract

Se ofrece un generador de temporizacion (86, 100) para usar en un sistema de comunicaciones. El generador de sincronizacion (86, 100) incluye circuitosde reloj (106) para generar una senal de temporizacion local. Los circuitos de interfase de temporizacion de red (104) están conectados a los circuitosde reloj (106) y recibe una senal de temporizacion de red. La senal de temporizacion de red se transmite a los circuitos de reloj (106), que emitenla senal de temporizacion local. Loscircuitos de salida de temporizacion del conmutador (114, 132) acoplados a los circuitos de reloj (106) reciben lasenal de temporizacion local y generan una senal de salida de temporizacion del conmutador.A timing generator (86, 100) is offered for use in a communications system. The synchronization generator (86, 100) includes clock circuits (106) to generate a local timing signal. The network timing interface circuits (104) are connected to the clock circuits (106) and receive a network timing signal. The network timing signal is transmitted to the clock circuits (106), which emit the local timing signal. The switch timing output circuits (114, 132) coupled to the clock circuits (106) receive the local timing signal and generate a switch timing output signal.

ARP980104014 1997-08-13 1998-08-13 TIMER GENERATOR AND SYSTEM TO GENERATE A TIMING SIGNAL TO BE USED IN A NETWORK OF DATA COMMUNICATIONS, AND METHOD TO CONTROL THE TIMING OF A DATA TRANSMISSION SYSTEM AR013943A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US91069897A 1997-08-13 1997-08-13

Publications (1)

Publication Number Publication Date
AR013943A1 true AR013943A1 (en) 2001-01-31

Family

ID=25429197

Family Applications (1)

Application Number Title Priority Date Filing Date
ARP980104014 AR013943A1 (en) 1997-08-13 1998-08-13 TIMER GENERATOR AND SYSTEM TO GENERATE A TIMING SIGNAL TO BE USED IN A NETWORK OF DATA COMMUNICATIONS, AND METHOD TO CONTROL THE TIMING OF A DATA TRANSMISSION SYSTEM

Country Status (5)

Country Link
AR (1) AR013943A1 (en)
AU (1) AU8679398A (en)
CO (1) CO4790201A1 (en)
PE (1) PE103299A1 (en)
WO (1) WO1999009687A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7170907B1 (en) 2002-02-15 2007-01-30 Marvell Semiconductor Israel Ltd. Dynamic alignment for data on a parallel bus

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2623042A1 (en) * 1987-11-09 1989-05-12 Js Telecommunications BASIC TIME CIRCUIT
FR2638591B1 (en) * 1988-11-03 1990-11-30 Telephonie Ind Commerciale SYNCHRONIZATION ARRANGEMENT FOR A PRIVATE DIGITAL AUTOMATIC SWITCH CONNECTED TO AN ISDN NETWORK
US5577075A (en) * 1991-09-26 1996-11-19 Ipc Information Systems, Inc. Distributed clocking system
US5436890A (en) * 1993-12-30 1995-07-25 Dsc Communications Corporation Integrated multi-rate cross-connect system
SE506739C2 (en) * 1995-09-29 1998-02-09 Ericsson Telefon Ab L M Operation and maintenance of clock distribution networks with redundancy

Also Published As

Publication number Publication date
AU8679398A (en) 1999-03-08
CO4790201A1 (en) 1999-05-31
WO1999009687A1 (en) 1999-02-25
PE103299A1 (en) 1999-10-24

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