KR100286280B1 - Power and timing control circuit - Google Patents

Abstract

PURPOSE: A power and timing control circuit is provided to synchronize a spread code to information data and to insert control data for power control and symbol timing control, by including the power and timing control circuit in a CDMA transmitter system. CONSTITUTION: A processor(100) controls all functions required in controlling power and timing, and a control memory(110) provides data to a corresponding block according to a command of the processor. A PN code generator(120) generates a PN code using an initial value from the memory and a synchronous signal from a clock and synchronous signal generator part(150). A walsh code generator(130) generates a walsh code using the initial value and the synchronous signal. A code converter(140) generates a Gold code by converting the outputs of the PN code generator and the walsh code generator properly, or makes to use only the walsh code or the PN code. The clock and synchronous signal generator part provides a clock used in each block using a system clock, and provides the synchronous signal. A data control part(160) performs a puncturing function inserting power control information into transmission data at a proper timing.

Description

Power and Timing Control Circuits

The present invention relates to a power and timing control circuit for generating a spreading code in synchronization with information data and for inserting control data for power control and symbol timing control in a transmitter for portable communication using a CDMA system.

Accordingly, an object of the present invention is to include a power and timing control circuit in a CDMA transmission system so as to synchronize spreading code with information data and insert control data for power control and symbol timing control.

1 is a block diagram showing the configuration of a power and timing control circuit according to the present invention;

〈Description of the symbols for the main parts of the drawings〉

100: processor 110: control memory

120: PN code generator 130: Walsh code generator

140: code converter 150: clock and synchronization signal generator

160: data control unit

The present invention relates to power and timing control circuits included in a CDMA transmission system.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

1 illustrates a configuration of a power and timing control circuit according to the present invention. The power and timing control circuit includes a processor 100 for controlling all functions necessary for power control and timing control, and a code initial value provided by the processor. The control memory 110 stores the control information and provides data to the corresponding block according to a processor command, and generates a PN code using an initial value provided from the memory, and a synchronization signal provided from a clock and a synchronization signal generator. PN code generator 120 to generate Walsh code using the initial value provided from the memory and the synchronization signal provided from the clock and the synchronization signal generator, Walsh code generator 130, PN code generator output and Walsh code A code that converts the generator output appropriately to generate a Gold code or to use only Walsh code or PN code. Clock and synchronization to generate and provide the clock used in each block by using the transformer 140 and the system clock provided from the processor, and to generate and provide a synchronization signal according to the data transmission timing for the purpose of synchronizing code. The signal generator 150 and the data controller 160 perform a puncturing function for inserting power control information into the transmission data at an appropriate timing.

As described above, the operation of the power control and timing control circuit consisting of a processor, a control memory, a PN code generator, a Walsh code generator, a code converter, a clock and synchronization signal generator, and a data controller is performed as follows. The processor transmits and stores the code initial value and power control information for generating the PN code and Walsh code to the memory, and instructs the memory to transmit the initial value and the control information to the corresponding block when transmitting the information data. When the control memory instructed by the processor provides a clock necessary for system operation, the control memory stores the code initial value transmitted from the processor and the control information for performing the power control function, and then stores the data in each block according to the command of the integrated circuit. The clock and sync signal generator generates and provides a clock of the rate required in each block by using the system clock provided from the processor and synchronizes the PN code and Walsh code with the data transmission timing. Create and provide it to PN clock generator and Walsh clock generator. Next, the PN clock generator receiving the data from the control memory generates a code in accordance with the synchronization signal provided by the clock and the synchronization signal generator by using the initial value of the PN code among the received data, and receives the data from the memory. The Walsh code generator generates Walsh codes according to the synchronization signals provided by the clock and synchronization signal generator by using Walsh code initial values among the provided data. The code converter receiving the PN code and Walsh code from the PN code generator and the Walsh code generator converts the output of the PN code and Walsh code to the data control unit appropriately and provides the function of using the PN code or Walsh code alone. do. The data controller to which data is transmitted from the above-described processor, the control memory, the code converter, the clock, and the synchronization signal generator outputs the control information by performing a puncturing function of inserting power control information into the transmitted data at an appropriate timing.

By operating as described above, the power control and timing control circuit of the present invention can generate the spreading code in synchronization with the information data and insert control data for power control and symbol timing control.

According to the present invention, the power control and timing control circuit generates codes at the time when the processor stores the code initial value and information necessary for power control in the control memory and transmits the information data to spread the transmission data and transmit the information for power control. It can be inserted into the data and sent. In addition, the code initial value that can be used may be stored in a plurality of control memories, and may be used variably in synchronization with the transmission data when necessary, and a separate bit may not be transmitted by inserting power control information into the transmission data. Also, depending on the processor's requirements, only PN code or Walsh code may be used.

The power control and timing control circuit of the present invention can provide a PN code or Walsh code and a GOLD code combining the two codes used for spectrum spreading, channel separation, device classification, or scramble, without modifying the circuit. The memory available to the system and the control memory can be used as spare memory for other purposes.

Claims (1)

Transmitting and storing code initial value and power control information for generating PN code and Walsh code in memory, and transmitting initial value and control information to corresponding block when transmitting the information The processor 100 instructing the processor, the memory 110 for storing the code initial value and control information provided by the processor and providing data to the block in accordance with the transfer command of the processor, and the system provided by the processor Generate and provide a clock of a rate used in each block by using a clock, and generate and provide a synchronization signal to generate the PN code and the Walsh code by exactly matching the data transmission timing. The code 150, the clock initial value and the clock and sync signal generator provided in the memory The Walsh code using the PN code generator 120 generating the PN code using the received synchronization signal, the code initial value provided from the memory, and the synchronization signal provided from the clock and synchronization signal generator. Walsh code generator 130 for generating a code, a code converter 140 for properly converting the output of the PN code generator and the output of the Walsh code generator to the data control unit without transmission delay, and transmits for the power control And a data control unit (160) which performs a puncturing function of inserting appropriate timing into power control information.