AR008905A1 - Decodificador para una senal electromagnetica codificada de acuerdo con un codigo bch - Google Patents
Decodificador para una senal electromagnetica codificada de acuerdo con un codigo bchInfo
- Publication number
- AR008905A1 AR008905A1 ARP970105028A ARP970105028A AR008905A1 AR 008905 A1 AR008905 A1 AR 008905A1 AR P970105028 A ARP970105028 A AR P970105028A AR P970105028 A ARP970105028 A AR P970105028A AR 008905 A1 AR008905 A1 AR 008905A1
- Authority
- AR
- Argentina
- Prior art keywords
- alpha
- multipliers
- circuit
- decoder
- electromagnetic signal
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
- H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
- G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
- G06F7/724—Finite field arithmetic
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Pure & Applied Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Mathematical Physics (AREA)
- Computational Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Algebra (AREA)
- Probability & Statistics with Applications (AREA)
- Error Detection And Correction (AREA)
- Detection And Correction Of Errors (AREA)
Abstract
Un decodificador de Reed-Solomon incluye un circuito de multiplicacion de campo de Galois optimizado. El circuito tiene una pluralidad demultiplicadores, conectados en una cadena lineal en donde el primer multiplicando del primer multiplicador es la magnitud A, y el segundomultiplicando es una constante. El circuito opera en una combinacion lineal de valores alfa que se suman a alfa j, cada multiplicador en la cadena generaun valor alfa sucesivo. Una pluralidad de selectores activan las salidas de los multiplicadores de acuerdo con la magnitud alfa j. Un circuito sumador demanera preferible realizado como una red logica de compuerta XOR, se conecta a los selectores para sumar las salidas activadas de los multiplicadores paraformar el producto final.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GBGB9622539.6A GB9622539D0 (en) | 1996-10-30 | 1996-10-30 | Galois field multiplier for reed-solomon decoder |
Publications (1)
Publication Number | Publication Date |
---|---|
AR008905A1 true AR008905A1 (es) | 2000-02-23 |
Family
ID=10802135
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ARP970105028A AR008905A1 (es) | 1996-10-30 | 1997-10-29 | Decodificador para una senal electromagnetica codificada de acuerdo con un codigo bch |
Country Status (13)
Country | Link |
---|---|
US (1) | US5818855A (es) |
EP (1) | EP0840461A3 (es) |
JP (1) | JPH10177497A (es) |
KR (1) | KR19980033277A (es) |
CN (1) | CN1181664A (es) |
AR (1) | AR008905A1 (es) |
AU (1) | AU699253B2 (es) |
CA (1) | CA2199114A1 (es) |
GB (1) | GB9622539D0 (es) |
ID (1) | ID18695A (es) |
IL (1) | IL122018A0 (es) |
SG (1) | SG65026A1 (es) |
TW (1) | TW375853B (es) |
Families Citing this family (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3233860B2 (ja) * | 1996-10-25 | 2001-12-04 | 松下電器産業株式会社 | リードソロモン復号器 |
US5905664A (en) * | 1997-04-04 | 1999-05-18 | National Semiconductor Corp. | Circuit for determining, in parallel, the terms of a remainder that results from dividing two binary polynomials |
US6044390A (en) * | 1998-04-16 | 2000-03-28 | V L S I Technology, Inc. | Recursive lookahead-based 2n -bit serial multipliers over Galois Field GF (2m) |
US6378105B1 (en) | 1999-05-24 | 2002-04-23 | Oak Technology, Inc. | Reed-Solomon multiplication method |
US6446233B1 (en) | 1999-09-10 | 2002-09-03 | Lsi Logic Corporation | Forward error correction apparatus and methods |
US6760742B1 (en) | 2000-02-18 | 2004-07-06 | Texas Instruments Incorporated | Multi-dimensional galois field multiplier |
US6996133B2 (en) * | 2000-04-18 | 2006-02-07 | Zenith Electronics Corporation | Digital communication system for transmitting and receiving robustly encoded data |
US6701478B1 (en) * | 2000-12-22 | 2004-03-02 | Nortel Networks Limited | System and method to generate a CRC (cyclic redundancy check) value using a plurality of CRC generators operating in parallel |
US7187698B2 (en) * | 2001-03-13 | 2007-03-06 | Zenith Electronics Corporation | Robust digital communication system |
US7003715B1 (en) | 2001-03-30 | 2006-02-21 | Cisco Technology, Inc. | Galois field multiply accumulator |
US7124064B1 (en) * | 2001-03-30 | 2006-10-17 | Cisco Technology, Inc. | Automatic generation of hardware description language code for complex polynomial functions |
US7447982B1 (en) | 2001-03-30 | 2008-11-04 | Cisco Technology, Inc. | BCH forward error correction decoder |
US6983414B1 (en) | 2001-03-30 | 2006-01-03 | Cisco Technology, Inc. | Error insertion circuit for SONET forward error correction |
FR2854747A1 (fr) * | 2003-05-09 | 2004-11-12 | St Microelectronics Sa | Dispositif et procede d'addition-comparaison-selection- ajustement dans un decodeur |
US7995667B2 (en) * | 2004-02-13 | 2011-08-09 | Broadcom Corporation | Reduced latency concatenated reed solomon-convolutional coding for MIMO wireless LAN |
US7228490B2 (en) * | 2004-02-19 | 2007-06-05 | Quantum Corporation | Error correction decoder using cells with partial syndrome generation |
CN1561005B (zh) * | 2004-02-20 | 2010-12-08 | 汇智系统股份有限公司 | 快速纠双错bch码译码器 |
US7366969B2 (en) * | 2004-10-07 | 2008-04-29 | Cisco Technology, Inc. | System and method for implementing a Reed Solomon multiplication section from exclusive-OR logic |
US7209070B2 (en) * | 2004-10-07 | 2007-04-24 | Honeywell International, Inc. | System and method for enhanced situational awareness of terrain in a vertical situation display |
CN100440738C (zh) * | 2005-12-16 | 2008-12-03 | 北京中星微电子有限公司 | BCH编码中Galois扩域运算的快速实现方法 |
CN101567696B (zh) * | 2009-05-22 | 2013-01-23 | 北京大学 | 一种参数可变的bch码编码器及译码器 |
CN103138770B (zh) * | 2010-01-12 | 2016-09-28 | 北京忆恒创源科技有限公司 | 有限域平方计算电路 |
EP2434650A1 (en) * | 2010-09-23 | 2012-03-28 | Panasonic Corporation | Reed-Solomon encoder with simplified Galois field multipliers |
CN103345379B (zh) * | 2013-06-09 | 2016-09-07 | 暨南大学 | 一种复数乘法器及其实现方法 |
US9954553B1 (en) * | 2015-06-05 | 2018-04-24 | Altera Corporation | Circuitry and methods for continuous parallel decoder operation |
US11012094B2 (en) | 2018-12-13 | 2021-05-18 | Ati Technologies Ulc | Encoder with mask based galois multipliers |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3872430A (en) * | 1973-11-23 | 1975-03-18 | Paul Emile Boudreau | Method and apparatus of error detection for variable length words using a polynomial code |
US4162480A (en) * | 1977-01-28 | 1979-07-24 | Cyclotomics, Inc. | Galois field computer |
US4559625A (en) * | 1983-07-28 | 1985-12-17 | Cyclotomics, Inc. | Interleavers for digital communications |
US4633470A (en) * | 1983-09-27 | 1986-12-30 | Cyclotomics, Inc. | Error correction for algebraic block codes |
JPS60186942A (ja) * | 1984-02-24 | 1985-09-24 | Victor Co Of Japan Ltd | デイジタル乗算回路 |
US4797848A (en) * | 1986-04-18 | 1989-01-10 | Hughes Aircraft Company | Pipelined bit-serial Galois Field multiplier |
US4833678A (en) * | 1987-07-22 | 1989-05-23 | Cyclotomics, Inc. | Hard-wired serial Galois field decoder |
US4847801A (en) * | 1987-10-26 | 1989-07-11 | Cyclotomics, Inc. | Compact galois field multiplier |
US4928280A (en) * | 1988-04-29 | 1990-05-22 | International Business Machines Corporation | Fast processor for multi-bit error correction codes |
SE466822B (sv) * | 1990-06-15 | 1992-04-06 | Mastrovito Edoardo | Anordning foer multiplikation av tvaa element i en galoiskropp |
GB9301704D0 (en) * | 1993-01-28 | 1993-03-17 | Signal Processors Ltd | New digital modem design techniques |
US5465261A (en) * | 1993-08-03 | 1995-11-07 | National Semiconductor Corporation | RAM based architecture for ECC circuits |
US5668831A (en) * | 1995-06-07 | 1997-09-16 | Discovision Associates | Signal processing apparatus and method |
-
1996
- 1996-10-30 GB GBGB9622539.6A patent/GB9622539D0/en active Pending
-
1997
- 1997-02-18 US US08/801,544 patent/US5818855A/en not_active Expired - Lifetime
- 1997-03-04 CA CA002199114A patent/CA2199114A1/en not_active Abandoned
- 1997-10-03 AU AU39918/97A patent/AU699253B2/en not_active Ceased
- 1997-10-03 EP EP97420182A patent/EP0840461A3/en not_active Withdrawn
- 1997-10-14 SG SG1997003735A patent/SG65026A1/en unknown
- 1997-10-21 JP JP9325121A patent/JPH10177497A/ja active Pending
- 1997-10-22 CN CN97121151A patent/CN1181664A/zh active Pending
- 1997-10-24 IL IL12201897A patent/IL122018A0/xx unknown
- 1997-10-29 AR ARP970105028A patent/AR008905A1/es unknown
- 1997-10-29 KR KR1019970055933A patent/KR19980033277A/ko not_active Application Discontinuation
- 1997-10-30 ID IDP973557A patent/ID18695A/id unknown
- 1997-11-06 TW TW086116571A patent/TW375853B/zh active
Also Published As
Publication number | Publication date |
---|---|
SG65026A1 (en) | 1999-05-25 |
EP0840461A2 (en) | 1998-05-06 |
AU699253B2 (en) | 1998-11-26 |
EP0840461A3 (en) | 2000-03-08 |
GB9622539D0 (en) | 1997-01-08 |
CA2199114A1 (en) | 1998-04-30 |
KR19980033277A (ko) | 1998-07-25 |
CN1181664A (zh) | 1998-05-13 |
TW375853B (en) | 1999-12-01 |
AU3991897A (en) | 1998-05-07 |
US5818855A (en) | 1998-10-06 |
IL122018A0 (en) | 1998-03-10 |
JPH10177497A (ja) | 1998-06-30 |
ID18695A (id) | 1998-04-30 |
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