WO2022091331A1

WO2022091331A1 - Frequency detector

Info

Publication number: WO2022091331A1
Application number: PCT/JP2020/040784
Authority: WO
Inventors: 勝己高橋; 將白石
Original assignee: 三菱電機株式会社
Priority date: 2020-10-30
Filing date: 2020-10-30
Publication date: 2022-05-05
Also published as: JP7204064B2; JPWO2022091331A1

Abstract

A frequency detector comprising an FFT device for calculating N Fourier transform results from N items of sampling data, and a detector for detecting an index which is the order of a frequency at which amplitude is at maximum, wherein the frequency detector further comprises a correction computing device comprising two input systems, a FIFO-type memory for delaying which is connected to one of the two input systems, an adder-subtracter for adding/subtracting N items of sampling data from the input system in which the FIFO-type memory is interposed and N other items of sampling data from the other input system, a phase generator for generating a phase and converting the phase to a complex number, and a multiplier for multiplying the data added/subtracted by the adder-subtracter by the complex number converted from the phase, the frequency detector performing the Fourier transform result calculation two or more times for the data outputted from the multiplier, comparing the corresponding amplitudes for a plurality of indexes detected from the Fourier transform results, and selecting the index having the larger amplitude.

Description

Frequency detector

The present disclosure technique relates to a device that detects a frequency in real time using a fast Fourier transform (hereinafter referred to as "FFT").

Frequency detection using FFT is used in a wide range of fields. For example, Patent Document 1 discloses applications such as Doppler radar and Doppler sonar, and discloses a technique for obtaining a Doppler frequency by FFTing a reflected echo signal.

Further, Patent Document 1 provides a technique for adding zero data to a digital data string so as to reach the reference sample number, with the sample number required for the fast Fourier transform as the reference sample number in order to satisfy the required frequency resolution. It is disclosed.

Japanese Unexamined Patent Publication No. 2012-247304

The technique disclosed in Patent Document 1 has a problem that the processing speed is halved and the circuit scale is doubled when the double resolution is obtained. An object of the present disclosure technique is to provide a frequency detector that increases the resolution while maintaining the processing speed and suppressing the increase in the circuit scale.

The frequency detector according to the present disclosure technique detects an FFT device that calculates N Fourier transform results from N sampling data, and an index that is the order of the frequencies having the maximum amplitude among the Fourier transform results. A frequency detector comprising a detector, two input systems in which an input line is branched into two, a Fourier type memory connected to one of the two input systems to cause a delay, and the above. An adder / subtractor that adds / subtracts N sampling data from an input system with a Fourier type memory and another N sampling data from another input system, generates a phase, and converts the generated phase into a complex number. A correction calculator further comprising a phase generator for multiplying the data added / subtracted by the addition / subtractor with the complex number converted from the phase by the phase generator, and an output from the multiplier. The calculation of the Fourier transform result is performed twice or more for the obtained data, the corresponding amplitudes of the plurality of indexes detected from the respective Fourier transform results are compared, and the index having the larger amplitude is selected.

Since the frequency detector according to the present disclosure technique has the above configuration, it is possible to obtain the result of Fourier transform with double resolution in the vicinity of the peak frequency without increasing the number of sampling points in order to double the frequency resolution. .. Therefore, it is possible to realize a frequency detector that increases the resolution while maintaining the processing speed and suppressing the increase in the circuit scale.

FIG. 1 is a block diagram showing a configuration of a frequency detector according to the first embodiment. FIG. 2 is a block diagram showing a configuration of a correction calculator in the frequency detector according to the second embodiment. FIG. 3 is a block diagram showing a configuration of a correction calculator in the frequency detector according to the third embodiment. FIG. 4 is a block diagram showing a configuration of a correction calculator in the frequency detector according to the fourth embodiment. FIG. 5 is a block diagram showing a configuration of a correction calculator in the frequency detector according to the fifth embodiment. FIG. 6 is a block diagram showing a configuration of the frequency detector according to the sixth embodiment. FIG. 7 is a block diagram showing a configuration of the frequency detector according to the seventh embodiment. FIG. 8 is a timing chart showing the processing timing of the frequency detector according to the fourth embodiment. FIG. 9 is a block diagram showing a configuration of the frequency detection device according to the ninth embodiment.

The form for implementing the disclosed technique will be clarified by the following description along with the drawings.

Embodiment 1.
FIG. 1 is a block diagram showing a configuration of a frequency detector 1 according to the first embodiment. The frequency detector 1 detects an input line 2 for receiving input data, an output line 3 for sending out a detection result, a correction calculator 4 for correcting the input data, an FFT device 5 for performing an FFT, and a maximum peak. A detector 6 and a selector 7 for selecting an output value are provided. Here, the FFT device 5 may perform a discrete Fourier transform.

The operation of the frequency detector 1 will be clarified by the following specific example. Specifically, the case where the number of sample data is N and the resolution is doubled is illustrated. The N sample data are transmitted to the correction calculator 4 via the input line 2. The correction calculator 4 corrects the transmitted N sample data and outputs the corrected data to the FFT device 5. The internal operation of the correction calculator 4 will be described later. The FFT device 5 Fourier transforms the sent N sample data, and also outputs the N Fourier transform results to the detector 6. Assuming that N sampling data are {x ₀ , x ₁ , ..., X _N-1 }, the FFT device 5 has N Fourier transform calculation results {F (f ₀ ), F (f ₁ ), ... F ( f _N-1 )} is calculated. Here, f ₀ , f ₁ , ... f _N-1 are frequencies arranged in ascending order, and the Fourier transform calculation result F (.) Is a complex number.

The detector 6 first calculates the absolute value of the complex number which is the result of the Fourier transform calculation. The absolute value of a complex number is the distance from the origin when the complex number is plotted on the complex plane. For example, the absolute value of the Fourier transform calculation result F (f ₁ ) is represented by using the symbol | · | of the absolute value, such as | F (f ₁ ) |. Further, | F (f ₁ ) | is called "amplitude" at the frequency f ₁ . The detector 6 detects an index of the peak frequency having the maximum amplitude and the frequency having the maximum amplitude among the frequencies having the maximum amplitude (hereinafter referred to as “peak frequency”). The index means the order in which the frequencies of the FFT results are arranged in ascending order. More specifically, the index is the symbols f ₀ , f ₁ , ... f _N-1 , and the subscripts 0, 1, ... N-1 representing the frequency. The detector 6 outputs the detected index and amplitude to the selector 7.

The selector 7 first doubles the transmitted index. Next, the selector 7 counts the first receipt as the 0th and adds 1 to the odd-numbered received index. Further, for the indexes received for the last two times, the corresponding amplitudes of each are compared, and the index having the larger amplitude is selected. Finally, the selector 7 outputs the selected index or the frequency corresponding to the index to the output line 3. By the above operation, the frequency detector 1 can output the peak frequency having the maximum amplitude.

The correction calculator 4 has an input of an input line 2, and is composed of a FIFO type memory 8, an addition / subtractor 9, a multiplier 10, and a phase generator 11. Further, the correction calculator 4 constitutes the frequency detector 1 and is arranged in front of the FFT device 5.

The FIFO type memory 8 of the correction calculator 4 stores N sampling data transmitted from the input line 2. The FIFO type memory 8 newly stores N sampling data and starts output at the same time, and keeps holding N data at all times.

The adder / subtractor 9 of the correction calculator 4 adds / subtracts the N sampling data transmitted from the input line 2 and the N data output from the FIFO type memory 8. Specifically, the addition / subtractor 9 switches between addition and subtraction with N additions and subtractions as one unit. For the subtraction here, the value of the input line 2 is subtracted from the output value of the FIFO type memory 8.

The multiplier 10 of the correction calculator 4 multiplies the value output from the adder / subtractor 9 by the complex number output from the phase generator 11.

The phase generator 11 of the correction calculator 4 generates a phase φ and outputs a complex number satisfying exp (jφ) = cos (φ) + j · sin (φ). The phase φ to be generated is 0 for the first N pieces, 0 for the next N pieces, and the phase increment α = π / N. That is, the generated φ is a value obtained by the following equation.
From the first N n = 0 to N-1, φ _n = 0 ... (1A)
Next N pieces from n = 0 to N-1, φ _n = nπ / N ... (1B)
The above processing of the phase generator 11 is repeated with 2N times as one unit.

When the phase φ generated by the phase generator 11 is 0, the FFT device 5 Fourier transforms N sampling data transmitted from the input line 2 as it is like a normal Fourier transform. The intention of giving the phase φ generated by the phase generator 11 in the equation (1B) requires explanation, and details thereof will be described here. The discrete Fourier transform performed by the FFT device 5 is given by the following equation (2).

However, here, k represents an index.
On the other hand, the phase generator 11 generates the phase φ given by the equation (1B) and inputs θ _n = exp (−jnφ) to each of the input signals x = {x ₀ , x ₁ , ..., X _N-1 }. When multiplied, the Fourier transform performed by the FFT device 5 becomes the following equation (3).

Compared to the uncorrected Fourier transform, the phase increment of the basic harmonic of the Fourier transform is 2π / N, the phase increment of the k harmonic is 2kπ / N, and the phase increment of the k + 1 harmonic is 2 (k + 1) π / N. Is. That is, it can be seen that the phase increment α = π / N of the phase generator 11 represented by the equation (1B) is half the phase increment of the k-fold wave and the k + 1-fold wave in the Fourier transform without correction. The phase increment is the increment of the shoulder of the exponential function when n is increased by one, but in other words, it corresponds to the frequency of the signal used in the Fourier transform.

The operating principle of the selector 7 will be clarified by the following specific example. As described above, the selector 7 selects any one of the two latest transmitted indexes. In a specific example, the index first transmitted from the detector 6 is m, and the index transmitted next is p. Further, the amplitude when the index is _m is Am, and the amplitude when the index is _p is Ap. The selector 7 converts the transmitted index {m, p} into the index {2m, 2p + 1}. Next, the selector 7 compares _Am and _Ap of the amplitude, and selects the index corresponding to the one having the larger amplitude. For example, if _Ap is larger, 2p + 1 is selected as an index, and the corresponding frequency is obtained using the following formula.
Frequency = Sampling frequency of input data x Index ÷ 2N ・・・ (4)
Therefore, the frequency of the peak whose index is 2p + 1 can be obtained by sampling frequency × (2p + 1) ÷ 2N.

By providing the above configuration, the frequency detector according to the first embodiment doubles the frequency resolution without reducing the processing speed and doubling the circuit scale as compared with the conventional frequency detector. Can be.

The processing speed and circuit scale in the effect of the invention need a little explanation, so they will be described here. The processing speed here refers to the throughput. Further, in general, the circuit scale of an FFT device capable of real-time processing doubles as the number of points doubles. Therefore, the circuit scale of the correction calculator 4 is sufficiently smaller than that of the FFT device 5, except in a special case where the number of sample points is small. The specific difference in circuit scale differs depending on the device such as FPGA, the configuration of the circuit provided by the vendor, the tool for synthesizing the circuit, and the like. That is, the frequency detector in the present disclosed technique can have a smaller circuit scale than the configuration of the FFT device that doubles the points without slowing down the processing speed.

In addition, the resolution of the frequency detector requires a little explanation, so it will be described here. The resolution is a value obtained by "input sampling frequency / FFT score". Therefore,
If the sampling frequency is kept as it is, the sampling time is doubled, and the number of sampling points is doubled, the resolution is doubled. The frequency detector according to the first embodiment outputs a result equivalent to the result obtained by doubling the FFT score under certain conditions by doubling the sampling time. The constant condition is that the received signal does not fluctuate in two different integration intervals.

Embodiment 2.
As the frequency detector according to the first embodiment, the one in which the correction calculator 4 includes one FIFO type memory 8 is described. However, in the present disclosed technique, only one FIFO type memory 8 shows the minimum required number, and is not limited to this. The frequency detector according to the second embodiment includes a plurality of FIFO type memories 8 (8a, 8b) and a plurality of phase rotators 13 (13a, 13b, 13c) in a subsequent stage.

The overall configuration of the frequency detector according to the second embodiment is the same as the overall configuration of the first embodiment (see FIG. 1). In the description of the second embodiment, the same reference numerals are used for the components common to the first embodiment. Further, the description overlapping with the first embodiment will be omitted as appropriate.

FIG. 2 is a block diagram showing a configuration of a correction calculator 4 in the frequency detector according to the second embodiment. The correction calculator 4 of the second embodiment includes an input line 2 for receiving input data, a plurality of FIFA type memories 8 (8a, 8b) for temporarily holding data, a multiplier 10 for performing multiplication operations, and a phase. The phase generator 11 for generating the above, the output line 12, the plurality of phase rotors 13 (13a, 13b, 13c) for rotating the phase, and the adder 14 for performing the addition calculation are provided.

The operation of the correction calculator 4 of the second embodiment will be clarified by the following specific example. The technique according to the second embodiment is intended to triple the resolution. The operation of the frequency detector according to the second embodiment is the same as that of the first embodiment except for the operation of the selector 7.

The operation of the frequency detector 1 according to the second embodiment will be clarified by the following specific example. Specifically, the case where the number of sample data is N and the resolution is tripled is illustrated. The N sample data are transmitted to the correction calculator 4 of the frequency detector 1 via the input line 2. The correction calculator 4 corrects the transmitted N sample data and outputs the corrected data to the FFT device 5. The internal operation of the correction calculator 4 will be described later. The FFT device 5 Fourier transforms the sent N sample data, and also outputs the N Fourier transform results to the detector 6. The detector 6 selects an index having the maximum amplitude from the results of N Fourier operations, and outputs the value of the amplitude corresponding to the selected index to the selector 7.

The selector 7 first triples the transmitted index. Next, the selector 7 counts the first receipt as the 0th, and adds the remainder obtained by dividing the number in the order of receipt by 3 to the received index. Further, for the indexes received for the last three times, the corresponding amplitudes of each are compared, and the index having the maximum amplitude is selected. Finally, the selector 7 outputs the selected index or the frequency corresponding to the index to the output line 3. By the above operation, the frequency detector 1 can output the peak frequency having the maximum amplitude.

The plurality of FIFO type memories 8 (8a, 8b) of the correction calculator 4 store N sampling data transmitted from the input line 2, respectively. Each of the plurality of FIFO type memories 8 (8a, 8b) newly stores N sampling data and starts output at the same time, and keeps holding N data at all times.

The correction calculator 4 includes a plurality of phase rotators 13 (13a, 13b) arranged after each of the plurality of FIFO type memories 8 (8a, 8b). In addition to the above, the correction calculator 4 includes a phase rotator 13 (13c) directly connected to the input line 2. The phase rotator 13 (13a, 13b, 13c) exerts an action of rotating the phase with respect to the input value. Specific matters such as the amount of rotation will be described later.

The adder / subtractor 9 of the correction calculator 4 adds three values output by each of the phase rotators 13 (13a, 13b, 13c). That is, the adder / subtractor 9 according to the second embodiment further includes an adder / subtractor input, and further adds / subtracts N sampling data.

The multiplier 10 of the correction calculator 4 multiplies the value output from the adder / subtractor 9 by the complex number output from the phase generator 11. This multiplication result becomes the correction result of the correction calculator 4.

The phase generator 11 of the correction calculator 4 generates a phase φ and outputs a complex number satisfying exp (jφ) = cos (φ) + j · sin (φ). The generated phase φ is given by the following mathematical formula.
Phase φ = ((n div N) mod 3) x (x mod N) x 2π ÷ (3N)
... (5)
However, n represents the sampling number, and div and mod represent the quotient and the surplus in the division of integers, respectively.
By the above operation, the correction calculator 4 corrects the input value.

The plurality of phase rotators 13 (13a, 13b, 13c) included in the correction calculator 4 operate as follows.
The phase rotator 13a arranged after the FIFO type memory 8a is just a name of a phase rotator and does not actually rotate the phase. The phase in which the phase rotator 13a rotates may be rephrased as 0 [rad]. The phase rotator 13a can be replaced with a delay circuit. Further, the phase rotator 13a may be configured to be eliminated by changing the number of holdings of the FIFO type memory 8a.
The phase rotator 13b arranged after the FIFO type memory 8b rotates the phase given by the following equation.
From the first N n = 0 to N-1, φ _n = 0 ... (6A)
Next N pieces from n = 0 to N-1, φ _n = 2π / 3 ... (6B)
From the last N n = 0 to N-1, φ _n = 4π / 3 ... (6C)
The phase rotator 13c directly connected to the input line 2 rotates the phase given by the following equation.
From the first N n = 0 to N-1, φ _n = 0 ... (7A)
Next N pieces from n = 0 to N-1, φ _n = 4π / 3 ... (7B)
From the last N n = 0 to N-1, φ _n = 8π / 3 ... (7C)

The operating principle of the selector 7 will be clarified by the following specific example. As described above, the selector 7 selects any one of the transmitted indexes for the last three times. In a specific example, the index transmitted first from the detector 6 is m, the index transmitted next is p, and the index transmitted last is q. Further, the amplitude when the index is _m is Am, the amplitude when the index is _p is Ap, and the amplitude when the index is q is A _q . The selector 7 converts the transmitted index {m, p, q} into the index {3m, 3p + 1, 3q + 2}. Next, the selector 7 compares the amplitudes _Am , _Ap , and _Aq , and selects the index corresponding to the maximum amplitude. For example, if A _q is the maximum, 3q + 2 is selected as an index, and the corresponding frequency is obtained using the following formula.
Frequency = Sampling frequency of input data x Index ÷ 3N ・・・ (8)
Therefore, the frequency of the peak whose index is 3q + 2 can be obtained by sampling frequency × (3q + 2) ÷ 3N.

By providing the above configuration, the frequency detector according to the second embodiment keeps the number of sampling points at N, does not reduce the processing speed as compared with the conventional frequency detector, and has a circuit scale of 3. The frequency resolution can be tripled without doubling.

The frequency detector according to the second embodiment shows an example in which the frequency resolution is tripled, but the present invention is not limited to this, and the frequency resolution can be generalized to be L times. When the frequency resolution is multiplied by L, the equation regarding the phase of the phase rotators 13 (13a, 13b, 13c, ...) In the L range can be generalized as follows.
From the first N n = 0 to N-1, φ _n = 0 ... (9A)
Next N pieces from n = 0 to N-1, φ _n = i × 2π / L ・・・ (9B)
Next N pieces from n = 0 to N-1, φ _n = i × 4π / L ... (9C)
…
From the last N n = 0 to N-1, φ _n = i × 2 (L-1) π / L ... (9D)
However, i is a serial number (from 0 to L-1) of the phase calculator.

Embodiment 3.
The frequency detector according to the third embodiment includes another correction calculator 4 different from the frequency detector according to the above-described embodiment. FIG. 3 is a block diagram showing the configuration of the correction calculator 4 of the frequency detector according to the third embodiment.

The overall configuration of the frequency detector according to the third embodiment is the same as the overall configuration of the first embodiment (see FIG. 1). In the description of the third embodiment, the same reference numerals are used for the components common to the above-described embodiments. Further, the description overlapping with the above-described embodiment will be omitted as appropriate.

As shown in FIG. 3, the correction calculator 4 of the third embodiment performs a multiplication operation with an input line 2 for receiving input data and a plurality of FIFA type memories (8, 22) for temporarily holding the data. It includes a multiplier 10, a phase generator 11 that generates a phase, an output line 12, an adder / subtractor 21 that performs both addition and subtraction, and a selector 23 that switches inputs.

The operation of the correction calculator 4 of the third embodiment will be clarified by the following specific example. The technique according to the third embodiment is intended to double the resolution in an embodiment different from that described above. The operation of the frequency detector according to the third embodiment is the same as that of the above-described embodiment except for the operation of the correction calculator 4.

The addition / subtractor 21 of the correction calculator 4 starts addition and subtraction at the same time as the output from the FIFO type memory 8 starts. As shown in FIG. 3, the adder / subtractor 21 has two output lines, an output line for an addition result and an output line for a subtraction result. The adder / subtractor 21 pauses N times after repeating the addition / subtraction N times after the start. After that, the addition / subtractor 21 switches between addition / subtraction and pause every N times.

The second FIFO type memory 22 of the correction calculator 4 is connected to the subtraction result output line of the adder / subtractor 21 and stores the subtraction result. The second FIFO type memory 22 starts output at the same time as storing Nd units, and continues output until it becomes empty. However, d is an integer value obtained by dividing the delay time generated by the multiplier 10 by the data input interval s.

The multiplier 10 of the correction calculator 4 multiplies the value output from the second FIFO type memory 22 by the complex number output from the phase generator 11. The result of the multiplication is transmitted to the selector 23 of the correction calculator 4.

The phase generator 11 of the correction calculator 4 generates a phase φ and outputs a complex number satisfying exp (jφ) = cos (φ) + j · sin (φ) to the multiplier 10. The generated phase φ is set to 0 for the first time, π / N is added each time the phase is sent, and the phase is returned to 0 every N times.

The selector 23 of the correction calculator 4 has two input lines, one is an output line for the addition result of the addition / subtractor 21, and the other is an output line of the multiplier 10. The selector 23 selects the addition result of the adder / subtractor 21 N times, and then selects the multiplication result of the multiplier 10 N times. After that, the selector 23 switches the selection destination every N times. By the above operation, the correction calculator 4 corrects the input value.

By providing the above configuration, the frequency detector according to the third embodiment keeps the number of sampling points at N, does not reduce the processing speed as compared with the conventional frequency detector, and doubles the circuit scale. The frequency resolution can be doubled without causing it. In addition, once every two times, the same result as the result obtained by doubling the sampling points can be obtained. It should be noted that the same result is obtained at the odd-numbered output starting from 0.

Embodiment 4.
The frequency detector according to the fourth embodiment includes another correction calculator 4 different from the frequency detector according to the above-described embodiment. FIG. 4 is a block diagram showing the configuration of the correction calculator 4 of the frequency detector according to the fourth embodiment.

The overall configuration of the frequency detector according to the fourth embodiment is the same as the overall configuration of the first embodiment (see FIG. 1). In the description of the fourth embodiment, the same reference numerals are used for the components common to the above-described embodiments. Further, the description overlapping with the above-described embodiment will be omitted as appropriate.

As shown in FIG. 4, the correction calculator 4 of the fourth embodiment includes an input line 2 that receives input data, a plurality of FIFA type memories 8 that temporarily hold the data, and a multiplier 10 that performs a multiplication operation. , The phase generator 11 that generates the phase, the output line 12, the adder / subtractor 21 that performs both addition and subtraction, the

selectors

23 and 25 that switch the input, and the

delayers

24 and 26 that delay the input for a short time. To prepare for.

The operation of the correction calculator 4 of the fourth embodiment will be clarified by the following specific example. The technique according to the fourth embodiment is intended to double the resolution in a different embodiment from that of the previous embodiment. The operation of the frequency detector according to the fourth embodiment is common to the operation shown in the third embodiment. There are two differences from the operation shown in the third embodiment. The first difference is that the FIFO type memory 8 and the second FIFO type memory 22 in the third embodiment are integrated into the FIFO type memory 8 in the fourth embodiment. The second difference is that with the integration of the FIFO type memory 8, the delay amount is adjusted for each of the

delay devices

24 and 26, and the selector 25 is configured to select the data to be output to the FIFO type memory 8. be.

The delay device 24 of the correction calculator 4 delays the data from the input line 2. The delay amount is set to be equal to the delay amount generated by the adder / subtractor 21.

The selector 25 of the correction calculator 4 selects the output from the delay device 24 at the first N times, and selects the subtraction result of the adder / subtractor 21 at the next N times. After that, the selector 25 switches the selection destination every N times.

The FIFO type memory 8 of the correction calculator 4 stores the data transmitted from the selector 25. The FIFO type memory 8 starts output at the same time as storing N-e pieces of data, and continues to hold N-e pieces of data. However, here, e is an integer value obtained by dividing the delay amount of the adder / subtractor 21 by the data input interval s on the input line 2.

The addition / subtractor 21 of the correction calculator 4 starts the addition / subtraction process at the same time as the output from the FIFO type memory 8 starts. After starting the process, the adder / subtractor 21 performs N times of addition / subtraction, and then pauses for N times. After that, the addition / subtractor 21 switches between addition / subtraction and pause every N times.

The delay device 26 of the correction calculator 4 delays the output of the addition result of the addition / subtraction device 21. The delay amount is a value obtained by dividing the difference in delay generated between the multiplier 10 and the adder / subtractor 21 by the data input interval s.

The multiplier 10 of the correction calculator 4 multiplies the output from the FIFO type memory 8 by 1, the next N pieces are multiplied by the complex number output by the phase generator 11, and the result of the multiplication is selected. Output to 23. After that, the multiplier 10 switches the value to be multiplied for each N pieces of data between 1 and a complex number.

The phase generator 11 of the correction calculator 4 generates N phase φ corresponding to N data, and multiplies N complex numbers obtained by exp (jφ) = cos (φ) + j · sin (φ). Output to the device 10. The phase φ to be generated has an initial value of 0, is added by π / N each time one phase is output, and is returned to 0 every time it is sent N times. Note that the output of the complex number to the multiplier 10 matches the timing at which the multiplier 10 multiplies.

The selector 23 of the correction calculator 4 selects the addition result of the addition / subtractor 21 N times, and then selects the multiplication result of the multiplier 10 N times. After that, the selector 23 switches the selection destination every N times. By the above operation, the correction calculator 4 corrects the input data.

By providing the above configuration, the frequency detector according to the fourth embodiment keeps the number of sampling points at N, does not reduce the processing speed as compared with the conventional frequency detector, and doubles the circuit scale. The frequency resolution can be doubled without causing it. In addition, once every two times, the same result as the result obtained by doubling the sampling points can be obtained. That is, the frequency detector according to the fourth embodiment realizes the same result as the frequency detector according to the third embodiment in a configuration in which the number of FIFO type memories is reduced.

The operation of the frequency detector according to the fourth embodiment will be clarified by using the timing chart. FIG. 8 is a timing chart showing the processing timing of the frequency detector according to the fourth embodiment. The band of each row of the timing chart of FIG. 8 is obtained by dividing the data into N pieces. The top square wave in the timing chart of FIG. 8 is a clock signal. Further, in FIG. 8, “INPUT / 2” indicates each data on the input line 2, “Delay / 24” indicates the output of the delay device 24, “SEL / 25” indicates the output of the selector 25, and “FIFO /”. "8" is the output of the FIFA type memory 8, "Add / 21" is the addition result of the adder / subtractor 21, "Sub / 21" is the subtraction result of the adder / subtractor 21, and "Delay / 26" is the output of the delay device 26. , "Multiply / 10" indicates the output of the multiplier 10, and "OUTPUT / 12" indicates each data on the output line 12. The timing chart of FIG. 8 shows that the frequency detector according to the fourth embodiment can continue processing in the FIFO type memory 8 and the output line 12 without causing data duplication or vacancy. ..

Embodiment 5.
The frequency detector according to the fifth embodiment includes another correction calculator 4 different from the frequency detector according to the above-described embodiment. FIG. 5 is a block diagram showing the configuration of the correction calculator 4 of the frequency detector according to the fifth embodiment.

The overall configuration of the frequency detector according to the fifth embodiment is the same as the overall configuration of the first embodiment (see FIG. 1). In the description of the fifth embodiment, the same reference numerals are used for the components common to the above-mentioned embodiments. Further, the description overlapping with the above-described embodiment will be omitted as appropriate.

As shown in FIG. 5, the correction calculator 4 of the fifth embodiment includes a memory controller 15 that controls the external memory 16. The external memory 16 and the memory controller 15 operate and function in the same manner as the FIFO type memory 8 in the correction calculator 4 of the first embodiment.

By providing the above configuration, the frequency detector according to the fifth embodiment has a smaller circuit scale than the frequency detector according to the first embodiment when an external memory can be used, and the first embodiment has a smaller circuit scale. The same effect as such a frequency detector can be obtained.

Embodiment 6.
The frequency detector according to the above-described embodiment has shown a configuration of one system in which the number of input lines is set to the minimum necessary one, but the present invention is not limited to this. The frequency detector according to the sixth embodiment is configured with two inputs. FIG. 6 is a block diagram showing a configuration of the frequency detector according to the sixth embodiment.
That is, the frequency detector according to the sixth embodiment is configured to newly increase the input system and input directly to the adder / subtractor instead of the adder / subtractor input to which the FIFO type memory is connected, and each input system. Was configured to input N sampling data with different sampling timings.

As shown in FIG. 6, the frequency detector according to the sixth embodiment includes input lines 2 (2a, 2b) that receive input data of two systems. Compared with the configuration of the first embodiment, it can be seen that the FIFO type memory 8 in the frequency detector of the first embodiment disappears, and that portion is one of the two systems. The input lines 2 (2a, 2b) are intended to handle the input data by N sampling data, respectively, with the timings shifted by N samples.

The operating principle of the frequency detector according to the sixth embodiment is the same as the operating principle of the frequency detector according to the first embodiment. The difference is that there are two input systems. The input line 2b is a point in which the input line 2a handles N sample data and then handles the next N sample data.

By providing the above configuration, the frequency detector according to the sixth embodiment can increase the reduced resolution (restore the resolution) by doubling the sampling rate. The frequency detection device according to the sixth embodiment can be applied even when the sampling rate does not change. This is nothing but a configuration in which the FIFO type memory 8 of FIG. 1 is moved to the front stage of the present device (the input line 2a side outside the device). In this case, if the input data string from 0 to N-1 and the input data string from N to 2N-1 are made the same on the input line 2 (2a, 2b) in a 2N cycle, the third embodiment is performed. The same output as the frequency detector is obtained.

Embodiment 7.
The frequency detector according to the sixth embodiment has two input systems, but the number of input systems may be further increased. The frequency detector according to the seventh embodiment is characterized in that the number of input systems is increased to three. FIG. 7 is a block diagram showing a configuration of the frequency detector according to the seventh embodiment.

As shown in FIG. 7, the frequency detector according to the seventh embodiment includes input lines 2 (2a, 2b, 2c) that receive input data of three systems. Compared with the configuration of the second embodiment, it can be seen that the FIFO type memory 8 in the frequency detector of the second embodiment disappears, and that portion is one of the three systems. The input lines 2 (2a, 2b, 2c) are intended to handle the input data by N sampling data, respectively, with the timings shifted by N samples.

The operating principle of the frequency detector according to the seventh embodiment is the same as the operating principle of the frequency detector according to the second embodiment. The difference is that there are three input systems. The input line 2b handles the next N sample data after the input line 2a handles N sample data. Further, the input line 2c handles N sample data after the input line 2b handles N sample data.

By providing the above configuration, the frequency detector according to the seventh embodiment can increase the reduced resolution (restore the resolution) by triple the sampling rate. Further, the frequency detection device according to the seventh embodiment shows that the input system has three systems, but the frequency detection device is not limited to this. The disclosed technique can generalize an input system to one having 3 or more L input systems.

Embodiment 8.
The frequency detection device according to the above-described embodiment has been described for the operation of detecting the peak frequency of the maximum amplitude. Similar to the conventional frequency detection device, there may be a plurality of peak frequencies to be detected at the same time. The configuration of the frequency detection device according to the eighth embodiment is the same as the configuration according to the first embodiment (see FIG. 1). The operation when detecting a plurality of peak frequencies is clarified by the detector 6 and the selector 7 and the operation according to a specific example.

A specific example of the eighth embodiment detects three frequencies at the same time. The detector 6 detects one or more peak frequencies and outputs the detected index to the selector 7. The detector 6 performs the following operation on the output index. The detector 6 first doubles the received index. Next, the detector 6 counts the first receipt as the 0th and adds 1 to the odd-numbered received index. The selector 7 integrates these two indexes if there are two indexes in which the difference between the indexes becomes 1 at the stage of the output by the detector 6 among the indexes output for the last two times. After the integration process, the three indexes are converted into frequencies in descending order of amplitude, and the converted frequency values are output to the output line 3.

By providing the above configuration, the frequency detector according to the eighth embodiment keeps the number of sampling points at N, does not reduce the processing speed as compared with the conventional frequency detector, and doubles the circuit scale. It is possible to double the frequency resolution and detect a plurality of peak frequencies at the same time without causing the problem.

In the specific example of the eighth embodiment, the number of peak frequencies to be detected is fixed at 3, but the number is not limited to this. The peak frequency to be detected may be determined by the amplitude threshold value or may be determined by combining the amplitude threshold value and the number condition.

Embodiment 9.
The frequency detector according to the above-described embodiment has been described on the premise that a dedicated processing circuit is used, but the present invention is not limited to this. The frequency detector according to the ninth embodiment adopts a configuration in which the function of the frequency detector according to the above-described embodiment is realized by using a general processor. FIG. 9 is a block diagram showing a configuration of the frequency detection device according to the ninth embodiment.

As shown in FIG. 9, the frequency detector 31 according to the ninth embodiment has an input line 32 for receiving data, an output line 33 for outputting a detection result, an input / output device 34 for input / output to / from the outside, data, and the like. It includes a memory 35 for storing and a processor 36 for performing arithmetic processing such as Fourier transform.

The input / output device 34 outputs N sampling data received via the input line 32 to the memory 35. The N sampling data of the even number, which is counted with the first as 0, is named data EVEN. The N sampling data of the odd number of times is named data ODD.

The processor 36 performs a correction operation on the data stored in the memory 35 (step ST1). The correction operation is the addition of data EVEN and data ODD.

The processor 36 performs a Fourier transform on N sampling data (step ST2). The N Fourier transform results are indexed in ascending order of frequency.

The processor 36 calculates an absolute value for N complex numbers of the Fourier transform result (step ST3). This absolute value is already the total amplitude.

The processor 36 selects the index having the maximum amplitude and doubles the index (step ST4).

When the selection is performed twice or more, the processor 36 outputs an index having a large amplitude among the latest two times to the memory 35 (step ST5). The output value may be the frequency corresponding to the index instead of the index.

When the processor 36 outputs the above value to the memory, the input / output device 34 outputs the value to the output line 33.

The frequency detector sends N new sampling data from the input line 32. The new N sampling data are stored in the memory 35 via the input / output device 34. In the example here, it is assumed that the storage in the memory 35 is an even-numbered event, and N sampling data are set as data EVEN (data is replaced).

The processor 36 performs a correction operation on the data stored in the memory 35 (step ST6). The correction operation is the subtraction of the data ODD from the data EVEN and the phase multiplication to the subtraction result. The phase in this phase multiplication is increased by π / N with the initial value set to 0.

After that, the processor 36 executes the processes from step ST2 to step ST5. Then, after replacing the N sampling data with the data ODD, the processor 36 executes step ST6. The above is a one-round flow performed by the processor 36, and the processor 36 repeats this.

As described above, the frequency detection device according to the above-described embodiment can also be realized by using a general processor. In addition, this processor may be substituted by various accelerators.

Frequency detector 1, 31;

Input line

2, 2a, 2b, 2c, 32;

Output line

3, 12, 33; Correction processor 4; FFT device 5; Detector 6; Selector 7;

FIFO type memory

8, 8a , 8b; adder / subtractor 9, 21; multiplier 10; phase generator 11;

phase rotator

13, 13a, 13b, 13c; adder 14; memory controller 15; external memory 16; second FIFA type memory 22;

selector

23, 25;

Delayer

24, 26; Input / output device 34; Memory 35; Processor 36.

Claims

An FFT device that calculates N Fourier transform results from N sampling data,
Among the Fourier transform results, a detector that detects an index that is in the order of frequencies at which the amplitude becomes maximum, and a detector.
It is a frequency detector equipped with
Two input systems that split the input line into two,
A FIFO type memory connected to one of the above two input systems to cause a delay,
An adder / subtractor that adds / subtracts N sampling data from an input system intervening in the FIFO type memory and another N sampling data from another input system.
A phase generator that generates a phase and converts the generated phase into a complex number,
A correction arithmetic unit including a multiplier for multiplying the data added / subtracted by the addition / subtractor by the complex number converted from the phase by the phase generator, and a correction arithmetic unit including the same are further provided.
The Fourier transform result is calculated twice or more for the data output from the multiplier, and the corresponding amplitudes of the plurality of indexes detected from the Fourier transform results are compared, and the amplitude is larger. A frequency detector characterized by selecting an index.
The adder / subtractor of the correction calculator further includes an adder / subtractor input, and further adds / subtracts N sampling data.
The frequency detector according to claim 1, further comprising a phase rotator for rotating the phase at each of the plurality of adder / subtractor inputs of the adder / subtractor.
The addition / subtractor of the correction calculator has two output lines, an output line for an addition result and an output line for a subtraction result.
The output line for the subtraction result is connected to the second FIFO type memory for delaying, and further connected to the multiplier in the subsequent stage.
The output line for the addition result and the output line of the multiplier are connected to the selector, respectively.
The frequency detector according to claim 1, wherein the selector switches the selection destination every N times.
The correction calculator further comprises a delay circuit.
The frequency detector according to claim 3, wherein the second FIFO type memory connected to the subtraction result output line is integrated with the FIFO type memory.
The frequency detector according to any one of claims 1 to 4, wherein the correction calculator includes a memory controller for controlling an external memory instead of the FIFO type memory.
Instead of the adder / subtractor input to which the FIFO type memory is connected, a new input system is added and configured to directly input to the adder / subtractor.
The frequency detector according to claim 2, wherein each input system is configured to input N sampling data having different sampling timings.
The process of calculating the N Fourier transform results from the N sampling data is executed.
A frequency detector including a processor that executes a process of detecting an index of the order of frequencies at which the amplitude becomes maximum among the Fourier transform results.
The processor performs a correction operation on the data stored in the memory, and
A step of performing a Fourier transform on the N sampling data subjected to the correction operation, and
The step of calculating the absolute value for the N complex numbers of the Fourier transform result, and
The step of selecting the index with the maximum absolute value and doubling the index,
If the selection is performed more than once, the step to output the index with the larger amplitude out of the last two times, and
A frequency detector characterized by performing a process consisting of.