WO2022091329A1

WO2022091329A1 - Frequency detector

Info

Publication number: WO2022091329A1
Application number: PCT/JP2020/040780
Authority: WO
Inventors: 勝己高橋; 將白石
Original assignee: 三菱電機株式会社
Priority date: 2020-10-30
Filing date: 2020-10-30
Publication date: 2022-05-05

Abstract

A frequency detector according to this disclosure comprises an FFT device for calculating N Fourier transform results from N items of sampling data and a detector for detecting an index that is the order of a frequency from among the Fourier transform results that has the greatest amplitude. The frequency detector comprises an adjacency calculator having a phase multiplier and accumulator, and the adjacency calculator calculates the amplitude of an intermediate frequency between the frequency corresponding to the index and the frequency corresponding to an index before or after the index.

Description

Frequency detector

The present disclosure technique relates to a device that detects a frequency in real time using a fast Fourier transform (hereinafter referred to as "FFT").

Frequency detection using FFT is used in a wide range of fields. For example, Patent Document 1 discloses applications such as Doppler radar and Doppler sonar, and discloses a technique for obtaining a Doppler frequency by FFTing a reflected echo signal.

Further, Patent Document 1 provides a technique for adding zero data to a digital data string so as to reach the reference sample number, with the sample number required for the fast Fourier transform as the reference sample number in order to satisfy the required frequency resolution. It is disclosed.

Japanese Unexamined Patent Publication No. 2012-247304

The technique disclosed in Patent Document 1 has a problem that the processing speed is halved and the circuit scale is doubled when the double resolution is obtained. An object of the present disclosure technique is to provide a frequency detector that increases the resolution while maintaining the processing speed and suppressing the increase in the circuit scale.

The frequency detector according to the present disclosure technique detects an FFT device that calculates N Fourier transform results from N sampling data, and an index of the Fourier transform results in the order of frequencies having the maximum amplitude. A frequency detector comprising a detector, wherein the frequency detector further comprises an adjacency calculator having a phase multiplier and an accumulator, wherein the adjacency calculator has a frequency corresponding to the index and the index. Calculate the amplitude at a frequency in the middle of the frequency corresponding to the index before or after.

Since the frequency detector according to the present disclosure technique has the above configuration, it is possible to obtain the result of the Fourier transform with double resolution in the vicinity of the peak frequency without performing the 2N Fourier transform from the N sampling data. can. Therefore, it is possible to realize a frequency detector that increases the resolution while maintaining the processing speed and suppressing the increase in the circuit scale.

FIG. 1 is a block diagram showing a configuration of a frequency detector according to the first embodiment. FIG. 2 is a block diagram showing a configuration of an adjacent calculator in the frequency detector according to the first embodiment. FIG. 3 is a block diagram showing a configuration of an adjacent calculator in the frequency detector according to the second embodiment. FIG. 4 is a block diagram showing a configuration of the frequency detector according to the fifth embodiment. FIG. 5 is a block diagram showing a configuration of the frequency detector according to the sixth embodiment. FIG. 6 is a reference diagram showing the processing timing of the frequency detector according to the sixth embodiment. FIG. 7 is a block diagram showing a configuration of the frequency detector according to the seventh embodiment.

The form for implementing the disclosed technique will be clarified by the following description along with the drawings.

Embodiment 1.
FIG. 1 is a block diagram showing a configuration of a frequency detector 1 according to the first embodiment. The frequency detector 1 includes an input line 2 that receives input data, an output line 3 that sends out detection results, an FFT device 4 that performs FFT, a detector 5 that detects signals, and First-In First-that temporarily holds data. It is composed of a FIFO type memory 6 which is an Out type memory, an adjacency calculator 7 for calculating an adjacent frequency value, and a selector 8 for selecting a detection result. The FFT device 4 may be one that carries out a discrete Fourier transform.

The operation of the frequency detector 1 will be clarified by the following specific example. Specifically, the case where the number of sample data is N and the resolution is doubled is illustrated. The N sample data are sent to the FFT device 4 and the FIFO type memory 6 via the input line 2. The FFT device 4 Fourier transforms the sent N sample data, and also outputs the N Fourier transform results to the detector 5. Assuming that N sampling data are {x ₀ , x ₁ , ..., X _N-1 }, the FFT device 4 has N Fourier transform calculation results {F (f ₀ ), F (f ₁ ), ... F ( f _N-1 )} is calculated. Here, f ₀ , f ₁ , ... f _N-1 are frequencies arranged in ascending order, and the Fourier transform calculation result F (.) Is a complex number.

The FIFO type memory 6 stores N sent sample data. The detector 5 first calculates the absolute value of the complex number which is the result of the Fourier transform calculation. The absolute value of a complex number is the distance from the origin when the complex number is plotted on the complex plane. For example, the absolute value of the Fourier transform calculation result F (f ₁ ) is represented by using the symbol | · | of the absolute value, such as | F (f ₁ ) |. Further, | F (f ₁ ) | is called "amplitude" at the frequency f ₁ . The detector 5 detects an index of the peak frequency having the maximum amplitude and the frequency having the maximum amplitude among the frequencies having the maximum amplitude (hereinafter referred to as “peak frequency”). The index means the order in which the frequencies of the FFT results are arranged in ascending order. More specifically, the index is the symbols f ₀ , f ₁ , ... f _N-1 , and the subscripts 0, 1, ... N-1 representing the frequency. As will be clarified later, the detector 5 dares to double the index and output it to the selector 8. That is, the detector 5 assigns the FFT results to 0, 1, ... In ascending order of frequency, and when the peak frequency at which the amplitude is maximum is fm, the detector 5 doubles _m to 2 m as a new index. Is output to the selector 8.

The detector 5 outputs an adjacent index adjacent to the doubled index as described above to the adjacent calculator 7 and the selector 8. Adjacent indicators will be clarified in the details below. The selector 8 selects the data having the larger amplitude from the data consisting of the peak frequency transmitted from the detector 5 and the adjacent calculator 7 and the amplitude at the peak frequency and the corresponding index, and selects the corresponding peak frequency. Output to output line 3. By the above operation, the frequency detector 1 can output the peak frequency having the maximum amplitude.

Adjacent indicators are clarified by the following detailed examples. In a specific example, it is assumed that the peak frequency at which the amplitude is maximum is fm as a result of the Fourier transform calculation. In this case, the detector 5 considers that the index 2m indicates that the candidate for the peak frequency having the maximum amplitude is 0, 1 out of 2N, and is at or near the 2mth. That is, 2m-1 and 2m + 1 out of 2N can be considered as candidates for the adjacent index. Therefore, the detector 5 counts as 0, 1 among the N calculation results, and is the amplitude of the m-1st calculation result | F (fm _-1 ) | and the amplitude of the m + 1st calculation result. Compare with a certain | F (fm _{+ 1} ) |. The selector 8 defines 2m-1 if the former is large and 2m + 1 if the latter is large as an adjacent index in 2N. The adjacency index sent by the detector 5 to the adjacency calculator 7 is 2 m + 1 in this specific example.

FIG. 2 is a block diagram showing a configuration of an adjacent calculator 7 in the frequency detector 1 according to the first embodiment. The adjacency calculator 7 includes a phase multiplier 9 that multiplies the input by the phase, and a calculator 10 that accumulates the inputs.

The operation of the adjacency calculator 7 will be clarified by the following specific example. In a specific example, the adjacency index is set to 2 m + 1 as described above. The phase multiplier 9 receives the adjacency index 2m + 1 from the detector 5 and calculates the phase increment α [rad]. The phase increment α is calculated by the following formula.
α = (2m + 1) × π / N ・・・ (1)
Compared with the Fourier transform performed by the FFT device 4, the phase increment of the basic harmonic of the Fourier transform is 2π / N, the phase increment of the m harmonic is 2mπ / N, and the phase increment of the m + 1 harmonic is 2 (m + 1) π. / N. That is, it can be seen that the phase increment α of the phase multiplier 9 represented by the equation (1) is an intermediate value between the m-fold wave and the m + 1-fold wave in the FFT device 4.

The phase multiplier 9 multiplies the input by the phase and outputs the multiplication result to the accumulator 10. At this time, the initial value of the phase is set to 0, and the phase increment α is added to the phase. Multiplying the input by phase becomes clear using a concrete example. Assuming that the input signal x entering the input line 2 is {x ₀ , x ₁ , ..., X _N-1 }, for example, multiplying x ₀ by the phase φ actually calculates x ₀ × θ. It means that you are. However, θ here is a complex number satisfying θ = exp (jφ) = cos (φ) + j · sin (φ).

The accumulator 10 sequentially receives the results from the phase multiplier 9 and outputs the absolute values of N accumulation results. The absolute value here is the distance from the origin when the complex number is plotted on the complex plane. By the above operation, the adjacency calculator 7 calculates the amplitude of the adjacency index and outputs the value to the selector 8.

The meaning of the adjacent calculator 7 including the phase multiplier 9 and the accumulator 10 becomes clear when compared with the mathematical expression of the discrete Fourier transform performed by the FFT device 4. There are several ways to formulate the discrete Fourier transform, for example:

However, here, k represents an index. The phase multiplier 9 calculates the phase increment α [rad] and multiplies each of the input signals x = {x ₀ , x ₁ , ..., X _N-1 } by θ _n = exp (−jnα) and accumulates. Calculate. The meaning of this becomes clear by comparing mathematical formulas.

In the Fourier transform performed by the FFT device 4, the frequency of the basic harmonic of the series that is the result of the Fourier transform is uniquely determined from the sampling period T and the number of sample points N. That is, the phase of the fundamental harmonic is 0 to 2π in the integration interval from the 0th sampling to just before the Nth sampling. That is, the integration interval is exactly the length of one cycle of the basic harmonics. In the equation (2A), the phase when n = 0 is 0, and the phase when n = N is 2π. Not only the basic harmonics, but also the multiple waves have a phase of 0 to 2π (including an integral multiple of 2π) in the integration interval.

After all, the intent of the present disclosure technique is the intermediate frequency {(f ₀ + f ₁ ) / of the N frequencies {f ₀ , f ₁ , ... f _N-1 } calculated by the FFT device 4. 2, (f ₁ + f ₂ ) / 2, ... (F _N-1 + f _N ) / 2} is also to be calculated. The following very simple example illustrates this. It is assumed that the frequency f ₀ of the fundamental tuning is 2 Hz, the frequency f ₁ of the second harmonic is 4 Hz, and the frequency f ₂ of the third harmonic is 6 Hz in the number of N = 3 samples. Setting the number of sample points to 2N = 6 means that the frequency f ₀ of the new fundamental tuning is 1 Hz, the frequency f ₁ of the second harmonic is 2 Hz, the frequency f ₂ of the third harmonic is 3 Hz, and the frequency of the fourth harmonic. It can be said that the coefficient of the series expansion is obtained by assuming that f ₃ is 4H, the frequency f ₄ of the 5th harmonic is 5Hz, and the frequency f ₅ of the 6th harmonic is 6Hz. Doubling the sample score is equivalent to taking into account just the middle frequencies.
However, since it is not necessary to calculate the frequencies of all the intermediate values, the N frequencies {f ₀ , f ₁ , ... F _N-1 } calculated by the FFT device 4 are adjacent to the frequencies having the maximum amplitude. The calculation is performed only at the frequency of the intermediate value.

The selector 8 can also obtain the corresponding frequency from the information of the index. The corresponding frequency is calculated from the following formula.
Frequency = input sampling frequency x (index + 1) ÷ (2N) ... (4)
Based on the specific example in which the adjacent index in 2N is 2m + 1, the selector 8 receives the index of 2m and 2m + 1, converts the index corresponding to the larger amplitude of the two into a frequency, and outputs the index. The index and frequency are one-to-one interchangeable values. Therefore, the selector 8 may output the index as it is without converting it into a frequency.

By providing the above configuration, the frequency detector according to the first embodiment doubles the frequency resolution without reducing the processing speed and doubling the circuit scale as compared with the conventional frequency detector. Can be.

The processing speed and circuit scale in the effect of the invention need a little explanation, so they will be described here. The processing speed here refers to the throughput. Further, in general, the circuit scale of an FFT device capable of real-time processing doubles as the number of points doubles. Therefore, the circuit scale of the adjacent calculator 7 is sufficiently smaller than that of the FFT device 4, except in a special case where the number of sample points is small. That is, the frequency detector in the present disclosed technique can have a smaller circuit scale than the configuration of the FFT device that doubles the points without slowing down the processing speed.

Also, the resolution of the frequency detector requires a little explanation, so it will be described here. The resolution is a value obtained by "input sampling frequency / FFT score". In Patent Document 1, which is an example of the prior art, instead of the configuration of two FFT devices that sample at alternating timings, the same number of 0s are added to the input data to double the number of FFT points and the resolution is 2. I'm showing it twice.

Embodiment 2.
As the frequency detector according to the first embodiment, the configuration in which the adjacent calculator 7 includes one phase multiplier 9 and one accumulator 10 is described. However, in the present disclosed technique, one phase multiplier 9 and one accumulator 10 only show the minimum required number, and are not limited to this. The frequency detector according to the second embodiment includes a plurality of phase multipliers 9 (9a, 9b, 9c) and a plurality of accumulators 10 (10a, 10b, 10c).

In the description of the second embodiment, the same reference numerals are used for the components common to the first embodiment. Further, the description overlapping with the first embodiment will be omitted as appropriate.

FIG. 3 is a block diagram showing the configuration of the adjacent calculator 7 in the frequency detector according to the second embodiment. The adjacent calculator 7 of the second embodiment includes a plurality of phase multipliers 9 (9a, 9b, 9c) for multiplying an input by a phase, and a plurality of accumulators 10 (10a, 10b, 10c) for accumulating inputs. To prepare for.

The operation of the adjacent calculator 7 of the second embodiment will be clarified by the following specific example. The technique according to the second embodiment considers quadrupling the resolution. The configuration of the frequency detector excluding the adjacent calculator is the same as that of the first embodiment. Further, the operation of the FFT device 4 and the FIFO type memory 6 is the same as that of the first embodiment.

The operation of the frequency detector 1 according to the second embodiment will be clarified by the following specific example. Specifically, the case where the number of sample data is N and the resolution is quadrupled is illustrated. The N sample data are sent to the FFT device 4 and the FIFO type memory 6 via the input line 2. The FFT device 4 Fourier transforms the sent N sample data, and also outputs the N Fourier transform results to the detector 5. The FIFO type memory 6 stores N sent sample data. The detector 5 first converts the Fourier transform result into an absolute value. The detector 5 detects the peak frequency having the maximum amplitude and its index. In the second embodiment, the detector 5 intentionally quadruples the index and outputs it to the selector 8. That is, the detector 5 assigns the FFT results to 1, 2, ... In ascending order of frequency, and when the peak frequency at which the amplitude is maximum is the mth, the detector 8 is set to the selector 8 with 4 m, which is quadrupled, as an index. Output.

The detector 5 outputs an adjacent index adjacent to the index quadrupled as described above to the adjacent calculator 7 and the selector 8. Adjacent indicators will be clarified in the details below. The selector 8 selects the data having a large amplitude from the data consisting of the peak frequency transmitted from the detector 5 and the adjacent calculator 7 and the amplitude at the peak frequency and the corresponding index, and selects the corresponding peak frequency. Output to output line 3. By the above operation, the frequency detector 1 can output the peak frequency having the maximum amplitude.

Adjacent indicators are clarified by the following detailed concrete examples. As a result of performing the Fourier transform in the FFT device 4, it is assumed that the peak frequency at which the amplitude is maximum is fm. In this case, the detector 5 considers that the amplitude becomes maximum at or near the 4mth index out of 4N. Candidates for adjacent indicators are 4m-1 and 4m + 1 out of 4N. Therefore, among the N calculation results, the m-1st amplitude and the m + 1st amplitude are compared, and if the former amplitude is large, 4m-1 is used, and if the latter amplitude is large, 4m + 1 is used. Is defined as. The adjacency index sent by the detector 5 to the adjacency calculator 7 is 4 m + 1 in this specific example.

The operation of the adjacency calculator 7 will be clarified by the following specific example. In a specific example, the adjacent index is 4 m + 1. The phase multiplier 9 (9a, 9b, 9c) receives the adjacency index 4m + 1 from the detector 5 and calculates the phase increment α [rad], respectively. Each phase increment α is calculated by the following formula.
The phase increment α of the phase multiplier 9a can be obtained by the following mathematical formula.
α = (4m + 1) × π / 2N ・・・ (5)
The phase increment α of the phase multiplier 9b can be obtained by the following mathematical formula.
α = (4m + 2) × π / 2N ・・・ (6)
The phase increment α of the phase multiplier 9c can be obtained by the following mathematical formula.
α = (4m + 3) × π / 2N ・・・ (7)

The phase multiplier 9 (9a, 9b, 9c) multiplies the input by the phase and outputs the multiplication result to the accumulator 10 (10a, 10b, 10c), respectively. At this time, the initial value of the phase is set to 0, and the phase increment α is added to the phase.

The accumulator 10 (10a, 10b, 10c) sequentially receives the multiplication results transmitted from the phase multipliers 9 (9a, 9b, 9c), calculates N accumulations, and is a complex number that is the result of the accumulation. The absolute value of, that is, the amplitude is output to the selector 8.

The selector 8 can also obtain the corresponding frequency from the information of the index. The corresponding frequency is calculated from the following formula.
Frequency = Input sampling frequency x (Index + 1) ÷ (4N) ・・・ (8)
Based on the specific example in which the adjacent index in 4N is 4m + 1, the selector 8 receives the indexes of 4m, 4m + 1, 4m + 2, and 4m + 3, and converts the one having the largest amplitude among the four into a frequency and outputs it. .. The index and frequency are one-to-one interchangeable values. Therefore, the selector 8 may output the index as it is without converting it into a frequency.

By providing the above configuration, the frequency detector according to the second embodiment has a frequency resolution that does not reduce the processing speed and does not increase the circuit scale by four times as compared with the conventional frequency detector. It can be quadrupled. Using a more generalized representation, the disclosed technique can improve the frequency resolution by a factor of L by having L-1 pairs of phase multipliers and accumulators.

Since increasing the resolution to L times requires explanation, it is supplemented here. When the resolution is multiplied by L, the change in FIG. 3 is that the adjacent calculator 7 is provided with an L-1 pair of a phase multiplier and a accumulator. The formula for calculating the phase increment α of each phase multiplier in this case is shown below.
α = ((adjacent index mod L) + k) × 2π / (L × N) ・・・ (9)
However, mod is a remainder operator, and k is a serial number possessed by each phase multiplier. This serial number starts from 1. In the case of the adjacent calculator 7 of FIG. 3, the phase multiplier 9a is 1, the phase multiplier 9b is 2, and the phase multiplier 9c is 3. The conversion formula from the index to the frequency in the selector 8 is as follows.
Frequency = input sampling frequency x (index + 1) ÷ (L x N) ... (10)

Embodiment 3.
The frequency detector according to the first embodiment and the second embodiment is configured to output only the result of one peak frequency. The frequency detector according to the third embodiment can detect signals of three different frequencies at the same time. The configuration of the frequency detector according to the third embodiment is the same as that of the frequency detector according to the second embodiment. Further, the operation of the FFT device 4 and the FIFO type memory 6 according to the third embodiment is the same as that of the second embodiment. In the description of the third embodiment, the same reference numerals are used for the components common to the first embodiment or the second embodiment. Further, the description overlapping with the first embodiment or the second embodiment will be omitted as appropriate.

The detector 5 according to the third embodiment selects three indexes having peaks in descending order of amplitude, and outputs a value obtained by doubling each index and the corresponding amplitude to the selector 8. Further, the detector 5 outputs each index adjacent to each peak to the adjacent calculator 7 and the selector 8.

The adjacency calculator 7 receives the adjacency index from the detector 5, calculates the amplitude at the frequency indicated by the adjacency index, and sends the calculated amplitude to the selector 8.

The selector 8 receives the calculation result from the detector 5 and the adjacent calculator 7, selects the one having the larger amplitude at each peak, converts the selected index into a frequency, and sends it to the output line 3. By the above operation, the frequency detector 1 according to the third embodiment can output three peak frequencies. To use a more generalized representation, the frequency detector 1 according to the third embodiment includes as many pairs of phase multipliers and accumulators as the number of selected peaks inside the adjacent calculator 7.

The detector 5 selects three peaks. In each of these, as in the case of the first embodiment, the detector 5 calculates the adjacency index and outputs it to the adjacency calculator 7. The phase multipliers 9a-9c of the adjacency calculator 7 receive three adjacency indices individually. For example, if the adjacency index is "2m + 1,2n-1,2o + 1", the adjacency calculator 7 calculates the increment based on each index, calculates each amplitude, and outputs it to the selector 8. The phase increment α in this specific example can be obtained by the following equation.
Phase increment of phase multiplier 9a α = (2m + 1) × π / N ... (11A)
Phase increment of phase multiplier 9b α = (2n-1) × π / N ... (11B)
Phase increment of phase multiplier 9c α = (2o + 1) × π / N ... (11C)

By providing the above configuration, the frequency detector according to the third embodiment simultaneously uses a plurality of frequencies without reducing the processing speed and doubling the circuit scale as compared with the conventional frequency detector. It can be detected and the frequency resolution of each can be doubled.

Further, although the above shows the configuration in which the same number of peaks as the number of phase multipliers is selected, the selection is limited by appropriately setting a threshold value for the amplitude of the selected peak frequency, and the number of calculated amplitudes is reduced. May be. In other words, in the frequency detector according to the third embodiment, the number of the plurality of peak frequencies to be detected is set to an upper limit, and the resolution of the individual detection frequency can be set for each order of the magnitude of the amplitude at the peak frequency.

Embodiment 4.
In the frequency detector according to the third embodiment, each of the phase multipliers 9 (9a, 9b, 9c) is configured on the premise of the same resolution. In the frequency detector according to the fourth embodiment, each of the phase multipliers 9 (9a, 9b, 9c) is configured assuming different resolutions. The configuration of the frequency detector according to the fourth embodiment is the same as that of the frequency detector according to the third embodiment. Further, the operation of the FFT device 4 and the FIFO type memory 6 according to the fourth embodiment is the same as that of the third embodiment. In the description of the fourth embodiment, the same reference numerals are used for the components common to the above-described embodiments. Further, the description overlapping with the above-described embodiment will be omitted as appropriate.

The detector 5 according to the fourth embodiment selects two indexes having peaks in descending order of amplitude. The one with the largest amplitude triples the index, and the one with the second largest amplitude doubles the index and outputs it to the selector 8. Further, the detector 5 outputs each index adjacent to each peak to the adjacent calculator 7 and the selector 8.

The selector 8 receives the calculation result from the detector 5 and the adjacent calculator 7, selects the one having the larger amplitude at each peak, converts the selected index into a frequency, and sends it to the output line 3. By the above operation, the frequency detector 1 according to the fourth embodiment can output two peak frequencies. Further, the frequency resolution of the frequency detector 1 according to the fourth embodiment is three times in the vicinity of the maximum amplitude and twice in the vicinity of the second largest amplitude.

The operation of the adjacent calculator 7 according to the fourth embodiment will be clarified by a specific example. In a specific example, the adjacency index received by the adjacency calculator 7 is "3m + 1,2n-1". 3m + 1 is an adjacency index of the maximum amplitude, and 2n-1 is an adjacency index of the second largest amplitude. The frequency detector according to the fourth embodiment divides the phase multiplier and the accumulator in the adjacency calculator 7 into 2: 1 and sets two as the adjacency index of the maximum amplitude and 1 as the adjacency index of the second largest amplitude. Assign a pair. The operation of each set is the same as that of the above-described embodiment. The only difference is the phase increment α of the phase multiplier 9 (9a, 9b, 9c). The phase increment α in this specific example can be obtained by the following equation.
Phase increment of phase multiplier 9a α = (3m + 1) × 2π / 3N ・・・ (12A)
Phase increment of phase multiplier 9b α = (3m + 2) × 2π / 3N ・・・ (12B)
Phase increment of phase multiplier 9c α = (2n-1) × π / N ... (12C)

By providing the above configuration, the frequency detector according to the fourth embodiment simultaneously uses a plurality of frequencies without reducing the processing speed and doubling the circuit scale as compared with the conventional frequency detector. It can be detected and the frequency resolution of each can be improved. Further, the frequency detector according to the fourth embodiment can adjust the degree of improvement in frequency resolution.

The frequency detector according to the third and fourth embodiments doubles or more the resolution of all the detected frequencies, but is not limited to this. The frequency detector according to the present disclosure technique may include a peak in the output that does not improve the resolution. In this case, the detector 5 also outputs the index of the peak that does not improve the resolution to the selector 8, but it is sufficient to transmit only the adjacent index that improves the resolution to the adjacent calculator 7.

Embodiment 5.
The frequency detector according to the above-described embodiment has a FIFO type memory 6 inside, but the frequency detector is not limited to this. The frequency detector according to the fifth embodiment is configured to use an external memory. FIG. 4 is a block diagram showing a configuration of the frequency detector according to the fifth embodiment.

The frequency detector 1 according to the fifth embodiment includes a memory controller 11 instead of the FIFO type memory 6. The memory controller 11 is connected to the external memory 12 and controls the external memory 12.

The frequency detector 1 according to the fifth embodiment uses the external memory 12 to further reduce the circuit scale as compared with the apparatus according to the above-described embodiment.

Embodiment 6.
The frequency detector according to the above-described embodiment has a configuration in which a memory controller 11 for controlling a FIFO type memory 6 or an external memory 12 is provided in front of an adjacent calculator 7. The frequency detector according to the sixth embodiment adopts a configuration in which nothing is provided in front of the adjacent calculator 7 and the input line 2 is directly connected to the adjacent calculator 7. FIG. 5 is a block diagram showing a configuration of the frequency detector according to the sixth embodiment.

As for the frequency detector according to the above-described embodiment, it is guaranteed that the FFT device 4 and the adjacent calculator 7 use the same input data due to the effect of the FIFO type memory 6 provided in front of the adjacent calculator 7. There is. On the other hand, in the frequency detector according to the sixth embodiment, the FIFO type memory 6 provided in the previous stage is intentionally removed, and the "delay in processing speed caused between the FFT device 4 and the detector 5" is positively used. .. As a premise of using the frequency detector according to the present disclosure technique, it is assumed that the signal to be sampled is a periodic signal in a period requiring N samplings, that is, a period obtained by multiplying the sampling period T by N.

FIG. 6 is a reference diagram showing the processing timing of the frequency detector according to the sixth embodiment. When the FFT device 4 has the delay shown in FIG. 6, the adjacent index calculated from the first output result of the FFT device 4 is obtained in the fourth front in the unit of the data block. Therefore, the adjacency calculator 7 cannot calculate the amplitude of the adjacency index for the first to third chunks of data. The adjacent calculator 7 first outputs the amplitude is the amplitude calculated from the fourth (Data # 4) chunk of data. The adjacent index used for the calculation is an index calculated from the first (Data # 1) chunk of data. Therefore, when the adjacent index calculated from the 4th (Data # 4) data block from the detector 5 is received, the two are compared, and if the adjacent indexes match, the amplitude is transmitted to the selector 8 and if they do not match. Outputs "no amplitude" to the selector 8. As a result, the selector 8 outputs the frequency with improved resolution when receiving the amplitude from the adjacent calculator 7, and outputs the frequency with the conventional resolution when receiving "no amplitude".

Since the frequency detector according to the present disclosed technique has a period of the signal to be sampled NT, it is assumed that all data blocks including the phase are the same. That is, the frequency detector according to the sixth embodiment utilizes the above-mentioned property, and the adjacent calculator 7 performs speculative execution. Therefore, by providing the above configuration, the frequency detector according to the sixth embodiment reduces the circuit scale as compared with the one according to the first embodiment in a period in which the frequency fluctuation of the signal to be detected is almost nonexistent. The same effect as that of 1 can be obtained.

Embodiment 7.
The frequency detector according to the above-described embodiment has been described on the premise that a dedicated processing circuit is used, but the present invention is not limited to this. The frequency detector according to the seventh embodiment adopts a configuration that realizes the function of the frequency detector according to the above-described embodiment by using a general processor. FIG. 7 is a block diagram showing a configuration of the frequency detector according to the seventh embodiment.

As shown in FIG. 7, the frequency detector 21 according to the seventh embodiment has an input line 22 for receiving data, an output line 23 for outputting a detection result, an input / output device 24 for input / output to / from the outside, data, and the like. It includes a memory 25 for storing and a processor 26 for performing arithmetic processing such as Fourier transform.

The input / output device 24 outputs N sampling data received via the input line 22 to the memory 25.

The processor 26 performs a Fourier transform on N sampling data stored in the memory 25. The processor 26 performs an absolute value calculation on N complex numbers which are the calculation results of the Fourier transform, and calculates the amplitude at each frequency. The processor 26 selects an index of the frequency having the maximum amplitude. The processor 26 calculates an adjacent index from the selected index having the maximum amplitude. The processor 26 multiplies the N sampling data stored in the memory 25 by the phase and calculates the total sum. As for the phase to be multiplied, the initial value is set to 0, and the phase increment corresponding to the adjacent index is added every time the multiplication is performed. The processor 26 compares the maximum amplitude with the absolute value of the sum, and selects the index corresponding to the larger one. The processor 26 converts the selected index into a frequency, and outputs the value of the frequency to the output line 23 via the input / output device 24.

By the above operation, the frequency detector 21 according to the seventh embodiment can output the frequency having the maximum amplitude.

Frequency detector

1, 21;

Input line

2, 22;

Output line

3, 23; FFT device 4; Detector 5; FIFA type memory 6; Adjacent calculator 7; Selector 8;

Phase multiplier

9, 9a, 9b,

9c Accumulator

10, 10a, 10b, 10c; Memory controller 11; External memory 12; Input / output device 24; Memory 25; Processor 26.

Claims

An FFT device that calculates N Fourier transform results from N sampling data,
Among the Fourier transform results, a detector that detects an index that is in the order of frequencies at which the amplitude becomes maximum, and a detector.
It is a frequency detector equipped with
The frequency detector further comprises an adjacency calculator with a phase multiplier and a accumulator.
The adjacent calculator is a frequency detector that calculates an amplitude at a frequency intermediate between a frequency corresponding to the index and a frequency corresponding to an index before or after the index.
The frequency detector according to claim 1, wherein the adjacent calculator includes a plurality of circuits including the phase multiplier and the accumulator.
The frequency detector according to claim 1, wherein a plurality of peak frequencies having maximum amplitudes are detected.
The frequency detector according to claim 3, wherein the number of the plurality of the peak frequencies to be detected is set to an upper limit, and the resolution of each detection frequency can be set for each order of the magnitude of the amplitude at the peak frequency. Characteristic frequency detector.
The frequency detector according to any one of claims 1 to 4, wherein the frequency detector includes a memory controller for controlling an external memory.
The frequency detector according to any one of claims 1 to 4, wherein the adjacent calculator performs speculative execution.
The process of calculating the N Fourier transform results from the N sampling data is executed.
A frequency detector including a processor that executes a process of detecting an index in the order of frequencies at which the amplitude becomes maximum among the Fourier transform results.
The processor further performs phase multiplication and accumulation,
A frequency detector comprising calculating an amplitude at a frequency intermediate between a frequency corresponding to the index and a frequency corresponding to the index before or after the index.