WO2013023446A1

WO2013023446A1 - Cavity manufacturing method

Info

Publication number: WO2013023446A1
Application number: PCT/CN2012/070732
Authority: WO
Inventors: 张挺; 郑晨焱; 夏佳杰; 谢志峰; 邵凯
Original assignee: 上海先进半导体制造股份有限公司
Priority date: 2011-08-12
Filing date: 2012-01-29
Publication date: 2013-02-21
Also published as: CN102328900A

Abstract

A cavity manufacturing method comprises steps of: providing a silicon substrate (001), and forming a substrate protection layer (002) on the silicon substrate (001); etching the substrate protection layer (002) to form a plurality of windows (003) until the silicon substrate (001) below is exposed; etching the silicon substrate (001) by using the substrate protection layer (002) as a mask, so as to form a plurality of grooves (004) in the silicon substrate (001); forming a side wall protection layer on side walls of the plurality of grooves; continuing to etch the grooves (004) by using the substrate protection layer (002) and the side wall protection layer (004) as masks, so as to form a plurality of deep grooves (007) in the silicon substrate (001); corroding the plurality of deep grooves (007) through wet corrosion, so as to form a cavity (008) inside the silicon substrate (001). The manufacturing method belongs to a front processing technique, does not adopt the expensive back processing technique, and is completely compatible with the conventional COMS manufacturing process. In the manufacturing method, the process temperature is lower than 400 degrees, and the total thickness of the substrate, after the cavity is formed, is greatly reduced. In addition, in the manufacturing method, process requirements are flexible, the whole process is stable and highly accurate, and has low cost.

Description

Method for manufacturing cavity

The present invention relates to the field of microelectromechanical system manufacturing technology, and in particular, to a method of manufacturing a cavity. Background technique

Isolated cavities are required in microelectromechanical systems (MEMS) pressure sensors, microfluidic devices, and other applications. These cavities are important components, some are vacuumed and some are filled with gas or liquid. The cavity has a different effect in different applications. For example, in a pressure sensor, the cavity acts as a background pressure to achieve a pressure comparison.

In order to achieve the fabrication of cavities in the different applications described above, the researchers have proposed various methods, such as MEMS, which are commonly formed by forming a recess on one side of a silicon wafer by a backside process, followed by anodic bonding on the back side. A bond between the silicon wafer and the glass substrate is achieved. In the middle of the bonding process, at high temperatures, the migration of the silicon wafer and the glass substrate ions is achieved by the application of high voltage, and the anodic bonding of the two substrates is achieved, and the bonding temperature generally exceeds 400 degrees. However, first of all, the backside process is incompatible with many traditional CMOS fabrication processes, and the substrate in which the cavity is implemented is thick (the total thickness of the silicon wafer and glass), which is not very suitable in some respects. .

Chinese invention patent (application number: 200610054435.X, application date: 2006.7.13, invention name: manufacturing method of pressure sensor silicon resonance film) discloses a manufacturing method of pressure sensor silicon resonance film, specifically adopting SOI (silicon on insulator) It is bonded to a patterned silicon substrate, and then a silicon resonance film is formed by thinning and wet etching. The use of this method requires the use of expensive SOI sheets and, after the bonding is completed, destructively removes excess portions of the SOI sheet. Therefore, the cost is 4艮. Summary of the invention

The technical problem to be solved by the present invention is to provide a method for manufacturing a cavity which is compatible with a conventional CMOS process, and has a thin total thickness of the substrate after forming the cavity, and the cost is low.

In order to solve the above technical problem, the present invention provides a method for manufacturing a cavity, comprising the steps of: providing a silicon substrate, forming a substrate protective layer on the silicon substrate; Etching the base protective layer to form a plurality of windows until the underlying silicon substrate is exposed; etching the silicon substrate with the substrate protective layer as a mask, forming a plurality of grooves in the silicon substrate; The sidewalls of the plurality of grooves form a sidewall protection layer;

Using the base protective layer and the sidewall protective layer as a mask, continuing to etch the recess to form a plurality of deep trenches in the silicon substrate;

A plurality of the deep trenches are etched by wet etching to form a cavity inside the silicon substrate.

Optionally, after the cavity is formed inside the silicon substrate, the method further includes the steps of:

A filling material is filled between the sidewall protective layers of the plurality of grooves to seal the cavity; wherein the filling material covers the substrate protective layer.

Optionally, after the sealing of the cavity, the method further comprises the steps of:

A reinforcing layer is deposited or spin coated on the filling material covering the base protective layer.

Optionally, after forming the reinforcement layer on the filler material, the method further comprises the steps of:

The reinforcement layer and the underfill material thereunder are sequentially removed by chemical mechanical polishing.

Optionally, after the removing the reinforcing layer and the filling material therebelow, the method further comprises the steps of:

The base protective layer is continued to be removed by chemical mechanical polishing until the silicon substrate is exposed.

Optionally, forming the sidewall protection layer on sidewalls of the plurality of grooves includes the following steps:

Forming an isolation layer by thermal reaction between sidewalls and bottom portions of the plurality of grooves;

The spacer layer at the bottom of the plurality of recesses is removed, and the sidewall protective layer is formed on the sidewalls of the plurality of recesses by the remaining spacer layer.

Optionally, the process of thermally reacting to form the barrier layer comprises a wet oxygen oxidation, a dry oxygen oxidation, and a nitrogen reaction process.

Optionally, the isolation layer at the bottom of the plurality of grooves is removed by a etch back process.

Forming a doped layer at the bottom of the plurality of grooves by ion implantation;

The sidewall protection layer is formed by thermal reaction on sidewalls of the plurality of grooves.

Optionally, the process of thermally reacting the sidewall protective layer comprises a wet oxygen oxidation, a dry oxygen oxidation, and a nitrogen reaction process.

Optionally, the silicon substrate is (111) crystal oriented.

Optionally, the base protective layer is formed by a thermal reaction.

- 2 - Optionally, the base protection layer comprises silicon oxide, silicon nitride, silicon oxynitride or polysilicon.

Optionally, the base protective layer further comprises a metal element, an alloy, a metal oxide or a metal nitride. Optionally, the shape, size and/or arrangement of the plurality of windows are adjustable.

Optionally, the shape, size, arrangement and/or depth of the plurality of grooves are related to the shape, size and/or arrangement of the plurality of said windows.

Optionally, the shape, size, arrangement and/or depth of the plurality of deep grooves are related to the shape, size and/or arrangement of the plurality of said windows.

Optionally, the wet etching method employs an anisotropic etching process to form the cavity inside the silicon substrate.

Optionally, the wet etched solution is a KOH, TMAH, HNA, EDP and/or alkali metal hydroxide solution.

Optionally, the shape and/or depth of the cavity is arbitrary.

Optionally, the process of sealing the cavity is a deposition method, a bonding method or an electroplating method.

Compared with the prior art, the present invention has the following advantages:

The fabrication method of the present invention is a front side process that does not employ an expensive backside process that is fully compatible with conventional CMOS fabrication processes.

The process temperature employed in the present invention is less than 400 degrees, and the total thickness of the substrate after the formation of the cavity is also greatly reduced.

In addition, the invention has relatively flexible process requirements, the entire processing process is stable and reliable, the precision is high, and the cost is low. DRAWINGS

The above and other features, properties and advantages of the present invention will become more apparent from the following description in conjunction with the appended claims

1 is a flow chart showing a method of manufacturing a cavity according to an embodiment of the present invention;

2 to FIG. 11 are schematic cross-sectional structural views showing a manufacturing process of a cavity according to an embodiment of the present invention; and FIGS. 12 to 23 are schematic cross-sectional structural views showing a manufacturing process of a cavity according to another embodiment of the present invention.

- 3 - detailed description

The invention is further described in the following detailed description of the embodiments of the invention, in which A person skilled in the art can make similar promotion and deduction according to the actual application without departing from the connotation of the present invention. Therefore, the scope of the present invention should not be limited by the content of the specific embodiment.

1 is a flow chart of a method of manufacturing a cavity according to an embodiment of the present invention. As shown, the manufacturing method can include the steps of:

Step S101 is performed to provide a silicon substrate, and a base protection layer is formed on the silicon substrate;

Step S102, etching the base protective layer to form a plurality of windows until the underlying silicon substrate is exposed; performing step S103, etching the silicon substrate with the base protective layer as a mask, and forming a plurality of recesses in the silicon substrate;

Step S104, forming sidewall protection layers on sidewalls of the plurality of grooves;

Step S105, using the base protective layer and the sidewall protective layer as a mask, continuing to etch the groove to form a plurality of deep grooves in the silicon base;

Step S106 is performed to etch a plurality of deep trenches by wet etching to form a cavity inside the silicon substrate. First embodiment of a method of manufacturing a cavity

2 to 11 are schematic cross-sectional structural views showing a manufacturing process of a cavity according to an embodiment of the present invention. It is to be noted that these and the following are merely exemplary, and are not intended to be construed as a limitation of the scope of the invention.

As shown in Fig. 2, a silicon substrate 001 is provided, which may be (111) crystal orientation.

As shown in FIG. 3, a base protective layer 002 is formed on the silicon substrate 001, and the base protective layer 002 may be formed by a thermal reaction (for example, thermal oxidation). The base protective layer 002 may include silicon oxide, silicon nitride, silicon oxynitride or polycrystalline silicon, and may even include a metal element, an alloy, a metal oxide or a metal nitride.

As shown in FIG. 4, the base protective layer 002 is etched to form a plurality of windows 003 until the underlying silicon substrate 001 is exposed. Among them, the shape, size and/or arrangement of the plurality of windows 003 are adjustable.

As shown in FIG. 5, the silicon substrate 001 is etched using the base protective layer 002 as a mask, and a plurality of grooves 004 are formed in the silicon substrate 001. The shape, size, arrangement and/or depth of the plurality of grooves 004 and the shape of the plurality of windows 003

- 4 - Shape, size and/or arrangement are related. The top view at this time can be as shown in FIG. 6. Here, the shape, the size, and the arrangement are taken as an example, and it is obvious that those skilled in the art can make arbitrary adjustments as needed, which are not intended to limit the contents of the present invention.

As shown in Fig. 7, the isolation layer 005 is formed by thermal reaction, such as dry oxidation or wet oxidation, on the sidewalls and the bottom of the plurality of grooves 004. It is apparent that nitride can also be formed by the nitrogen reaction process as the separation layer 005.

As shown in FIG. 8, the isolation layer 005 at the bottom of the plurality of recesses 004 is removed by, for example, a etch back process to expose the bottom silicon material 006, and the sidewalls of the plurality of recesses 004 are formed by the remaining isolation layer 005. .

As shown in FIG. 9, the substrate 002 and the sidewall protective layer are used as a mask, and the recess 004 is further etched to form a plurality of deep trenches 007 in the silicon substrate 001. The shape, size, arrangement and/or depth of the plurality of deep grooves 007 are related to the shape, size and/or arrangement of the plurality of windows 003.

As shown in FIG. 10, a plurality of deep trenches 007 are etched by wet etching, and a cavity 008 is formed inside the silicon substrate 001. The wet etching method may employ an anisotropic etching process, and the corroded solution may be KOH. Due to the anisotropic etching of KOH, a structure as shown in Fig. 10 was formed. Because of the protection of the sidewall protective layer and the substrate protective layer 002, a cavity 008 as shown is formed. The wet etching process of this step may employ other types of wet etching solutions such as TMAH, HNA (HF + HNO ₃ + acetic acid), EDP and/or other alkali metal hydroxide containing solutions. The cross-sectional view of the formed cavity 008 is merely illustrative in nature, may be any other shape and/or depth, and may even have rough sidewalls.

As shown in FIG. 11, in the present embodiment, after the cavity 008 is formed inside the silicon substrate 001, a filling material may be filled between the sidewall protective layers of the plurality of grooves 004 to seal the cavity 008. Among them, a part of the filling material covers the base protective layer 002. The process of sealing the cavity 008 may be a deposition method, a bonding method, or a plating method. Second embodiment of a method of manufacturing a cavity

12 to 23 are schematic cross-sectional views showing a manufacturing process of a cavity according to another embodiment of the present invention. It is to be noted that these and the following are merely by way of example, and are not intended to be construed as a limitation.

As shown in Fig. 12, a silicon substrate 101 is provided, which may be (111) crystallographic, and obviously other orientations. As shown in FIG. 13, a base protective layer 102 is formed on the silicon substrate 101, and the base protective layer 102 may be formed by a thermal reaction (for example, thermal oxidation). The base protection layer 102 may include silicon oxide, silicon nitride, silicon oxynitride or polysilicon, and may even include a metal element, an alloy, a metal oxide or a metal nitride.

As shown in FIG. 14, the base protective layer 102 is etched to form a plurality of windows 103 until the underlying silicon substrate 101 is exposed. Among them, the shape, size and/or arrangement of the plurality of windows 103 are adjustable.

As shown in FIG. 15, the silicon substrate 101 is etched using the base protective layer 102 as a mask, and a plurality of grooves 104 are formed in the silicon substrate 101. The shape, size, arrangement and/or depth of the plurality of grooves 104 are related to the shape, size and/or arrangement of the plurality of windows 103.

As shown in Fig. 16, a doping layer 105 is formed at the bottom of the plurality of grooves 104 by ion implantation. The ions implanted, such as N ions, may of course be other types of implanted ions, including but not limited to B, P, As, Sb, and the like. The base protective layer 102 serves not only as a hard mask but also as a protective layer for ion implantation.

As shown in Fig. 17, the side wall protective layer 106 is selectively formed by thermal reaction at the sidewalls of the plurality of grooves 104 by, for example, dry oxidation, wet oxidation or a nitrogen reaction process. After the ion implantation at the bottom of the groove 104, a thin oxide layer is not formed or formed only during the oxidation. On the side wall of the recess 104, since there is no ion implantation, a thick oxide layer, i.e., the sidewall protective layer 106, is formed.

As shown in FIG. 18, with the base protective layer 102 and the sidewall protective layer 106 as a mask, the recess 104 is continuously etched, and a plurality of deep trenches 107 are formed in the silicon substrate 101. The shape, size, arrangement and/or depth of the plurality of deep grooves 107 are related to the shape, size and/or arrangement of the plurality of windows 103.

The above-described injection layer is formed at the bottom of the recess 104 by ion implantation to avoid formation of a thick oxide layer, which is advantageous in facilitating subsequent etching of the deep trench 107.

As shown in Fig. 19, a plurality of deep trenches 107 are etched by wet etching to form a cavity 108 inside the silicon substrate 101. The wet etching method may employ an anisotropic etching process, and the corroded solution may be TMAH. Because of the protection of the sidewall protective layer 106 and the substrate protective layer 102, a cavity 108 is formed as shown. The wet etching process of this step may employ other types of wet etching solutions as described above, such as an alkali metal hydroxide solution. The cross-sectional view of the formed cavity 108 is merely illustrative in nature, may be any other shape and/or depth, and may even have rough sidewalls.

As shown in FIG. 20, in the present embodiment, after the cavity 108 is formed inside the silicon substrate 101, the filling material 109 may be filled between the sidewall protective layers 106 of the plurality of grooves 104 to seal the cavity 108. . Its

- 6 - A portion of the filling material 109 is partially covered on the base protective layer 102. The process of sealing the cavity 108 may be a deposition method, a bonding method, or a plating method.

As shown in FIG. 21, in the embodiment, after the cavity 108 is sealed, a reinforcing layer 110 may be deposited or spin-coated on the filling material 109 covering the base protective layer 102 for reinforcing the filling of the cavity 108. .

As shown in Fig. 22, in the present embodiment, after the reinforcing layer 110 is formed on the filling material 109, the reinforcing layer 110 and the filling material 109 therebelow may be sequentially removed by chemical mechanical polishing.

As shown in Fig. 23, in the present embodiment, after the reinforcing layer 110 and the underlying filling material 109 are removed, the base protective layer 102 can be further removed by chemical mechanical polishing until the silicon substrate 101 is exposed.

After this step, according to the actual selection needs, those skilled in the art can perform further processing on the cavity 108 to form various semiconductor devices and the like, which will not be described herein. The fabrication method of the present invention is a front side process that does not employ an expensive backside process that is fully compatible with conventional CMOS fabrication processes.

In addition, the invention has relatively flexible process requirements, the entire processing process is stable and reliable, the precision is high, and the cost is low.

The present invention has been disclosed in the above preferred embodiments, and is not intended to limit the scope of the invention, and may be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, any modifications, equivalent changes and modifications of the above-described embodiments in accordance with the technical scope of the present invention are intended to be within the scope of the invention as defined by the appended claims.

Claims

Rights request

1. A method of manufacturing a cavity, comprising the steps of:

Providing a silicon substrate on which a base protective layer is formed;

Etching the base protective layer to form a plurality of windows until the underlying silicon substrate is exposed; etching the silicon substrate with the substrate protective layer as a mask, and forming a plurality of recesses in the silicon substrate;

Forming a sidewall protective layer on sidewalls of the plurality of grooves;

2. The method of manufacturing a cavity according to claim 1, further comprising the steps of: forming a cavity inside the silicon substrate:

Filling a filler material between the sidewall protective layers of the plurality of grooves to seal the cavity;

Wherein the filling material covers the base protective layer.

3. The method of manufacturing a cavity according to claim 2, further comprising the steps of: sealing the cavity:

4. The method of manufacturing a cavity according to claim 3, further comprising the steps of: forming a reinforcement layer on the filler material:

5. The method of manufacturing a cavity according to claim 4, further comprising the steps of: removing the reinforcement layer and the filler material therebelow:

- 8 -

The method of manufacturing a cavity according to any one of claims 1 to 5, wherein forming the sidewall protective layer on sidewalls of the plurality of grooves comprises the steps of:

7. The method of manufacturing a cavity according to claim 6, wherein the process of thermally forming the isolation layer comprises a wet oxygen oxidation, a dry oxygen oxidation, and a nitrogen reaction process.

8. The method of manufacturing a cavity according to claim 7, wherein the isolation layer at the bottom of the plurality of grooves is removed by a etch back process.

10. The method of manufacturing a cavity according to claim 9, wherein the process of thermally forming the sidewall protective layer comprises a wet oxygen oxidation, a dry oxygen oxidation, and a nitrogen reaction process.

The method of manufacturing a cavity according to claim 1, wherein the silicon substrate is (11 1 ) crystal oriented.

The method of manufacturing a cavity according to claim 11, wherein the base protective layer is formed by a thermal reaction.

The method of manufacturing a cavity according to claim 12, wherein the base protection layer comprises silicon oxide, silicon nitride, silicon oxynitride or polysilicon.

- 9 -

14. The method of manufacturing a cavity according to claim 13, wherein the base protection layer further comprises a metal element, an alloy, a metal oxide or a metal nitride.

A method of manufacturing a cavity according to claim 14, wherein the shape, size and/or arrangement of the plurality of said windows are adjustable.

16. The method of manufacturing a cavity according to claim 15, wherein a shape, a size, an arrangement, and/or a depth of the plurality of grooves and a shape, a size, and/or a row of the plurality of the windows are Cloth is related.

The method of manufacturing a cavity according to claim 16, wherein a shape, a size, an arrangement, and/or a depth of the plurality of deep grooves and a shape, a size, and/or a row of the plurality of the windows Cloth is related.

The method of manufacturing a cavity according to claim 17, wherein the wet etching method employs an anisotropic etching process to form the cavity inside the silicon substrate.

The method of manufacturing a cavity according to claim 18, wherein the wet etching solution is KOH, TMAH, HNA, EDP and/or an alkali metal hydroxide solution.

20. A method of manufacturing a cavity according to claim 19, wherein the shape and/or depth of the cavity is arbitrary.

The method of manufacturing a cavity according to claim 20, wherein the process of sealing the cavity is a deposition method, a bonding method, or a plating method.

- 10 -