WO2010005281A2

WO2010005281A2 - Method for generating pseudo-random data

Info

Publication number: WO2010005281A2
Application number: PCT/MY2009/000096
Authority: WO
Inventors: Raif Bin Mohamed Noor Beg Ahmad; Mohd Fuad Tengku Aziz Raja; Abu Talib Azhar; Othman Norhaniza; Firdaus Haji Yaacob Wira; Borhan Rozita; Ahmad Anas Syed Omar Syed
Original assignee: Mimos Berhad
Priority date: 2008-07-10
Filing date: 2009-07-09
Publication date: 2010-01-14
Also published as: MY146157A; WO2010005281A3

Abstract

The present invention relates to method for generating a pseudo-random data whereby the said method is accomplished with an additional circuit. The main embodiments of method of the present invention are the act of randomly tapping values from the output based on a plurality of registers which are connected in a linear feedback shift mode and thus providing said values for further processing and generating a single final output.

Description

Method for Generating Pseudo-Random Data

Field of the Invention

The present invention relates to a method for generating random data, more particularly, a method for generating pseudo-random data used for a linear feedback shift register (LFSR) .

Background of Invention

At present, generation of random data has become rather ubiquitous in public and private sectors, whereby the many applications which require generating random data include profitable and security means, such as gaming, simulation and most importantly, cryptographic applications. However, one of the major concerns which typically surfaces in respect to random data generators and its related software which is often faced with is data theft due to low degree of unpredictability.

For the above reason, it is only crucial that various standards and methods have been developed and thus implemented to accomplish non-deterministic data with protected or secured random data generation for a wide variety of daily basis applications, in particular for security from information theft or even undesirable data manipulation. Studies have shown that the effectiveness of a cryptographic system is fundamentally based on the randomness of input or keys which is obtained with the assistance of a random number generator (RNG) . Typically, it is known in the art that RNG are mainly provided in the form of a hardware or software, whereby in software form, mathematical algorithms are deployed to generate random numbers, whilst hardware generators are means that generates random numbers using data normally obtained from noises within a computer circuitry.

In contrast to hardware generators which are considered as truly random number generators (TRNG) , due to its source to extract data is practically random, for software random number generators, random numbers are created from a "seed" value, whereby a person skilled in the art would comprehend that such value may be obtained from various kinds of repetitive motions or operation in the computer, for instance running processes or movements by articles connected to the said computer. Accordingly, in most cases, the sequence of numbers for this method is rather deterministic, in particular if a user is able to predict the algorithm used. Therefore, numbers which are generated by software based RNG may not be truly random, however are pseudo-random. It is further understood in the art that the software based generators for such randomness are known as pseudo-random number generators (PRNG) . An important component in pseudo-random number generators is the internal operation of random number generators, whereby said operation is generally performed by shift registers. In the relevant art, there are at least two main shift registers, those are the non-linear feedback shift register (NLFSR) and linear feedback shift register (LFSR) . Commonly the main function of a shift register is assist in producing the pseudo-random numbers. In comparison, the LFSR is rather prone to cryptanalytic attacks due to its complete linearity of its output than that of the NLFSR. However, LFSRs are generally efficient for both software or hardware designed generators and are known with excellent statistical properties.

It is further known by a person skilled in the art that random number generators are connected by way of a polynomial. Therefore, an outsider would be able to predict the sequence of date upon cracked or obtained the polynomial that connects the said generator. Such event may be highly detrimental for use in security applications.

Proceeding from the above, PRNGs and in particular PRNGs with implementation of LFSR are more often used for non-cryptographic applications, such as gaming, simulations and the like. This is mainly due to the fact that one of the main vulnerabilities of using PRNGs is the inability to provide high degree or uncrackable cryptographic security, a feature more feasible for truly random number generators.

Nevertheless, despite the primary drawback as discussed above, PRNGs are widely known in the art for its production of numbers at a very fast speed. Therefore, it would be highly desirable to develop a method or means that substantially alleviates the tribulation of a PRNG, in particular a PRNG using the efficiencies of an LFSR.

A relatively close example of a method developed particularly as a solution for the above tribulation is as disclosed in United States Patent Application No. 20070230694 (Gordon Rose, et al.) . In this document, there is provided a cryptographically secure pseudo-random number generator, whereby the method enables the subject pseudo-random number generator to obtain one or more unpredictable sources of entropy that provide a "seed", whereby a pseudo-random number is therefore generated based on the modified internal state of the number generator. It is however mentioned that the method may deploy a non-linear feedback shift register with respect to the operations on the internal state and the said "seed".

Proceeding from the prior art described above, it is therefore understood by a person skilled in the art that it would be advantageous develop a method to solve the tribulations of a PRNG having a LFSR operational features and thus improve the security feature of the said PRNG.

It is a primary object of this invention to provide a method for generating pseudo-random data having strengthened predictability of data.

It is yet another object of the invention to provide a method for generating pseudo-random data using LFSR circuit, whereby the invention is able to be configured to interface with a variety of computer bus or receiver and/or transmitters.

It is yet another object of the present invention to provide a method for generating pseudo-random data using LFSR circuit, whereby the said method in accordance with the present invention is non-complicated and is able to interface seamlessly to the desired application.

The present invention satisfies this and other desires, mainly to resolve issues regarding to the security assurance and the unpredictability for pseudo-random data/number generation (PSNG) .

Other objects and features will be apparent from the following detailed description of preferred embodiments. Brief Description of the Drawings

The present invention, the method of operation, together, with features, objects and advantages thereof may be best understood by reference to the following detailed description when read with accompanying drawings in which:

Figure 1 is a schematic diagram showing the circuit of the present invention;

Figure 2 is a block diagram showing the operation of one embodiment of the present invention in collaboration with the LFSR circuit;

Figure 3 is a diagram showing the time interval between pulses in accordance with an embodiment of the present invention;

Figure 4 is a diagram showing the circuit used for detection of pulses and comparison the period or interval between said successive pulses referred herein as tl and t2 which therefore providing the output associated with Table 1 disclosed herein.

Figure 5 shows the output generated in accordance with the present invention. Summary of Invention

The present invention discloses a method for generating pseudo - random data based on a plurality of registers connected in a linear feedback shift register mode, the method comprising the steps of:

i) selecting randomly a plurality of values from said plurality of registers; ii) determining the fixed value for said randomly selected values from step i) ; iii) generating a pulse based on each determined fixed value from step ii) ; iv) determining the time interval between pulses generated from step iii) ; v) comparing the time intervals from step (iv) ; vi) generating a final output from the said comparison step.

Detailed Description of the Present Invention

In addition to the drawings, further understanding of the object, construction, characteristics and functions of the invention, a detailed description with reference to the embodiments is given in the following.

It should be noted that to those skilled that there may be changes in construction and differing embodiments and applications of the invention without departing from the scope of the invention as defined in the appended claims.

Each element, which collaboratively forms the present invention, will be described herewith, in accordance to the presently preferred embodiments of the present invention.

The present invention is in the form of a digital circuit which serves as an extra circuitry that assists in generating pseudo- random data within heightened unpredictability. Therefore, it is understood that there may be inclusion of conventional embodiments in the description purely to elucidate the operational view of the present invention. Further, it is understood that this invention is effectively used in addition to the conventional random data generators . Typically in order to generate random data, the main steps include determination of the connecting polynomial for the selected shift register and thus the generation of random data or numbers based on said polynomial with the assistance of the shift register. The present invention plays a major role in regards to the generation of random data by way of tapping a plurality^" of data from the linear data or output initially generated by the selected register prior to further processing and thus generating random values. This step therefore increases the unpredictability of data.

Accordingly, the essential embodiments of the present invention include tapping or selecting a plurality of values randomly from a plurality of registers; defining values based on the said randomly tapped values, generation of pulses based on the defined value and generation final output based on the time interval between pulses. It is suitably noted that the post processing block or unit (4) is an essential embodiment of the present invention as it aids significantly to further process the output from the register and thus enhances the unpredictability of data. As the present invention is formed by two different circuits, in order to facilitate in synchronizing the actions of the said circuits, there may be included a clock signal.

In general based on the main principle of the present invention, there are provided two inputs, said inputs are the clock signal and reset signal. Both of said inputs are accordingly received by the pulse generator circuit (2) for producing or generating a stream of pulses which are sent or forwarded to the post processing unit or block (4) for further processing and thus generating only one output data or value.

It is further noted that the implementation of post processing block (4) or technique plays a major role in improving the generation of random data or numbers, particularly in the security aspect.

As mentioned briefly, the invention provides two single bits inputs with respect to the operational overview of the present invention, wherein the said inputs are for reset and clock. However, only 1 bit output is generated, the said output is for producing pseudo-random bits.

Figure 4 suitably provides the circuit diagram for the pulses detection and comparison of the tl and t2 output between successive pulses in one embodiment of the present invention, whereby the overall operational view in effect will be described in detail herein, referring collectively also to Figure 1, Figure 2 and Figure 3. The first unit, which is the pulse generator (2) in accordance to the present invention functions mainly as a means for generating a predefined number of registers referred herein as n, preferably connected in a linear feedback shift register mode. It is known in the art that the registers are connected by way of a predetermined polynomial with respect to the said linear feedback shift mode.

In accordance to a preferred embodiment of the present invention, the registers are initialized to a value determined by the user.

It is further known that the register may have a finite number of possible states; therefore it may eventually enter a cycle. As initiated with the said predetermined value, after every clock cycle there the occurrence of random value of n bits.

As shown in Figure 2, from the various points of these registers provided by said pulse generator (2) , a few or a plurality are randomly picked or tapped and sent to the next step for generation of pulses. In the instance that there are three registers selected, represented as n7, n5 and n3, these registers are tested for a defined value. Accordingly, whenever the said registers obtained a value, a pulse is generated.

Upon generation of the said stream of pulses, it is subsequently fed to another essential embodiment of the present invention, which is the post processing block or unit (4) as briefly mentioned earlier. The primary function of the post processing block (4) is carried out by a circuit as shown in Figure 4, whereby it is configured for detection of successive pulses and thus the comparison of time interval between said pulses. In this embodiment, the time interval between two successive pulses which may be referred to as an interval period or duration, are accordingly measured as suitably shown in Figure 2 and Figure 3. The interval duration, may be referred to as tl, and t2, whereby the said period is compared as shown in the table appended shortly below.

As described earlier, the comparison of these pulses intervals are performed by the post processing block (4) , whereby the intervals are obtained as also shown in Figure 3. It should be noted that during this step the processing block (4) detects the successive pulses and thereby compares said successive pulses to generate a single output, which is referred in Figure 4 as "data out". Suitably, in order to efficiently perform the comparison, the processing block (4) is able to recognize the positive edge and thus generates the appropriate output, preferably after two subsequent pulses. Table 1: Comparison of tl and t2

There is further provided a reset signal (RSTA) within the post processing block (4) so as to enable the reset mode of the output signal from the pulse generator (2) .

In the next step, data generated is then forwarded to a PC interface for appropriate translation or conversion, preferably the conventional universal asynchronous receiver/transmitter (UART) .

Data generated with the present invention may be captured and thus observed by various conventional software, for instance a HyperTerminal, RealTerm or any other software which is able to provide compatibility in terms of the interface connection, particularly for a device having RS-232 mechanical characteristics and identification. Accordingly, a sample output obtained with the method of the present invention is provided herewith, referred as Figure 5. It will be realized that the random number generator provided in accordance to the present invention enables the generation of random number of significantly improved security quality than that of the prior art. This is owing to the use of two layers of process subsequent to the linear feedback shift mode which facilitates to strengthen the unpredictability of data.

It is further mentioned that the present invention enables preset able hard coding for the linear feedback shift circuit.

In addition, the simplicity of the implementation whereby it is easily configured to interface UART, USB and PCI therefore creates a solution within the prior art which is more cost effective.

Although the present invention has been described with reference to the preferred embodiments and examples thereof, it is apparent to those skilled in the art that a variety of modifications and changes may be made without departing from the scope of the present invention which is intended to be defined by the appended claims.

Claims

1. A method for generating pseudo -random data based on a plurality of registers connected in a linear feedback shift register mode, the method comprising the steps of:

2. The method as claimed in Claim 1 wherein the registers connected in a LFSR mode is defined by a polynomial.

3. The method as claimed in Claim 1 wherein the method is performed by digital circuit.

4. The method as claimed in Claim 1 wherein the plurality of registers and the steps of selecting random values, determining fixed value and generating of pulses are provided by a pulse generator (2) .

5. The method as claimed in Claim 1 wherein the steps of determining the time interval between pulses, comparing the time intervals and generating an output are provided by a post processing block (4) .

6. The method as claimed in Claim 1 wherein the final output generated upon completion of the comparison step is a string of bits.

7. The method as claimed in Claim 1 wherein different polynomial and different process involved within the circuit generates different stream of pulses.

8. The method as claimed in Claim 1 wherein the final output generated is then passed to an interface device.