CN110045947B - Random number generating unit and device - Google Patents
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- CN110045947B CN110045947B CN201910325522.1A CN201910325522A CN110045947B CN 110045947 B CN110045947 B CN 110045947B CN 201910325522 A CN201910325522 A CN 201910325522A CN 110045947 B CN110045947 B CN 110045947B
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Abstract
The invention provides a random number generation unit and a device, and relates to the technical field of random number generators. The random number generation unit comprises at least one group of physical random source module, a sampling control module and a digital post-processing module, wherein the at least one group of physical random source module, the sampling control module and the digital post-processing module are sequentially and electrically connected, the physical random source module comprises an analog circuit and generates random signals through the analog circuit, the sampling control module is used for sampling the random signals in a system clock domain, and the digital post-processing module is used for processing the sampled random signals according to a preset algorithm to generate random numbers. The random number generating unit provided by the invention has the effects of stronger randomness and better quality of random numbers.
Description
Technical Field
The invention relates to the technical field of random number generators, in particular to a random number generating unit and a random number generating device.
Background
Today, information security is more and more emphasized by many countries and industries due to the rapid development of informatization. Modern cryptographic techniques have developed rapidly in the development of applied technologies such as online shopping, financial securities, government, military countermeasures, and the like. Modern cryptographic techniques mostly implement different encryption and decryption algorithms based on keys, and the generation of the keys comes from a random number generator.
Random number generators fall into two categories: Pseudo-Random Number generators (PRNG: Pseudo Random Number generators) and True Random Number generators (TRNG: True Random Number generators). The pseudo-random number generator is typically implemented based on some given algorithm and initializing a random seed, which when different, generates different random numbers. The disadvantage is that the generated random numbers are the same when the random seeds used are the same. True random number generators typically use some uncertainty in the physical characteristics of the generated random numbers, such as thermal noise, environmental noise, radioactive decay, oscillation, etc. of the circuit.
At present, an oscillation type true random number generator based on digital logic is adopted by a true random number generator and comprises a high-frequency oscillation clock, a low-frequency sampling clock and a digital post-processing unit. The high-frequency oscillation clock can generate certain crosstalk in implementation, so that the generated random number is not strong enough in randomness and not good enough in quality.
In view of the above, how to solve the above problems is the focus of attention of those skilled in the art.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a random number generating unit, so as to solve the problems of the prior art that the randomness of the random number generator is not strong enough and the quality of the random number is not good enough.
Another objective of the present invention is to provide a random number generator, so as to solve the problems of the prior art that the randomness of the random number generator is not strong enough and the quality of the random number is not good enough.
In order to achieve the above purpose, the embodiment of the present invention adopts the following technical solutions:
the invention provides a random number generation unit, which comprises at least one group of physical random source modules, a sampling control module and a digital post-processing module, wherein the at least one group of physical random source modules, the sampling control module and the digital post-processing module are sequentially and electrically connected, the physical random source modules comprise analog circuits, random signals are generated through the analog circuits, the sampling control module is used for sampling the random signals in a system clock domain, and the digital post-processing module is used for processing the sampled random signals according to a preset algorithm to generate random numbers.
Furthermore, the analog circuit comprises at least one high-frequency clock circuit and at least one low-frequency sampling clock circuit to generate a high-frequency oscillation random signal or a low-frequency sampling random signal.
Furthermore, the analog circuit comprises a first high-frequency oscillation random source circuit, a second high-frequency oscillation random source circuit and a low-frequency sampling clock circuit, wherein the first high-frequency oscillation random source circuit and the second high-frequency oscillation random source circuit form two high-frequency clock circuits, and the first high-frequency oscillation random source circuit, the second high-frequency oscillation random source circuit and the low-frequency sampling clock circuit form two low-frequency sampling clock circuits.
Further, the output ends of the first high-frequency oscillation random source circuit and the second high-frequency oscillation random source circuit are both electrically connected to the input end of the low-frequency sampling clock circuit, and the low-frequency sampling clock circuit is configured to sample the first high-frequency oscillation random source circuit and the second high-frequency oscillation random source circuit to generate random signals.
Further, when the analog circuit outputs a low-frequency sampling random signal, the sampling control module is configured to sample a rising edge of the low-frequency sampling clock of each group of the physical random source modules, synchronize a signal of the low-frequency sampling clock to a system clock domain after a falling edge of each path of the sampling clock arrives, and perform exclusive or processing on all the low-frequency sampling random signals.
Further, when the analog circuit outputs a high-frequency oscillation random signal, the sampling control module is configured to sample each path of the high-frequency oscillation random signal by using a system clock domain, and perform xor processing on the sampled random signal.
Further, the random number generation unit further comprises a register unit, the register unit is electrically connected with the sampling control module, the digital post-processing module and each group of physical random source modules respectively, and the register unit is also used for being electrically connected with a CPU.
Further, the register unit includes a random number register, a configuration register and a control register, the random number register, the configuration register and the control register are all used to be electrically connected with the CPU, the random number register is electrically connected with the digital post-processing module, the configuration register and the control register are respectively electrically connected with the at least one set of physical random source module, the sampling control module and the digital post-processing module, the configuration register is used to configure the working modes of the sampling control module and the digital post-processing module after receiving the configuration instruction of the CPU, the control register is used to control the at least one set of physical random source module, the sampling control module and the digital post-processing module to work after receiving the control instruction of the CPU, the random number generated by the digital post-processing module is sent to the random number register, the CPU reads the random number from the random number register.
Further, the random number generation unit further includes an output protection module, the register unit further includes a status register, the output protection module is electrically connected to the digital post-processing module and the status register, the output protection module is configured to receive the random number sent by the digital post-processing module, determine whether the random number is wrong, and transmit a determination result to the status register, and the CPU is configured to determine whether to read the random number from the random number register according to the determination result in the status register.
Furthermore, the output protection module is also preset with a reading time value, and the control register is also used for limiting the number of times that the CPU reads the random number in the random number register within the reading time value to be smaller than a preset value.
Furthermore, the analog circuit further comprises a noise amplifying circuit, and the noise amplifying circuit is electrically connected with the low-frequency sampling clock.
Further, the digital post-processing module includes a linear shift feedback register, and the linear shift feedback register is configured to shift the sampled random signal according to a first primitive polynomial or a second primitive polynomial.
On the other hand, the invention also provides a random number generating device which comprises a random number generating unit.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides a random number generation unit and a device, wherein the random number generation unit comprises at least one group of physical random source modules, a sampling control module and a digital post-processing module, the at least one group of physical random source modules, the sampling control module and the digital post-processing module are sequentially and electrically connected, the physical random source modules comprise analog circuits, random signals are generated through the analog circuits, the sampling control module is used for sampling the random signals in a system clock domain, and the digital post-processing module is used for processing the sampled random signals according to a preset algorithm to generate random numbers. Because the invention generates the random signal through the analog circuit, the crosstalk between the circuits is avoided in the circuit design, thereby achieving the effects of stronger randomness of the random number generating unit and better quality of the random number.
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 shows an interaction diagram of a random number generation unit according to an embodiment of the present invention.
Fig. 2 shows a circuit diagram of a physical random source module provided by an embodiment of the invention.
Fig. 3 shows a circuit diagram of a sampling control module according to an embodiment of the present invention.
Fig. 4 shows a falling edge synthesis timing diagram provided by an embodiment of the present invention.
Fig. 5 is a circuit diagram of another sampling control module according to an embodiment of the present invention.
Fig. 6 shows a primitive polynomial processing diagram of a digital post-processing module provided by an embodiment of the present invention.
Fig. 7 shows another primitive polynomial processing diagram of a digital post-processing module provided by an embodiment of the invention.
Fig. 8 is an interaction diagram of another random number generation unit according to an embodiment of the present invention.
Icon: 100-a random number generating unit; 110-physical random source module; 120-a sampling control module; 121-a first high frequency oscillating random source circuit; 122-a second high frequency oscillating random source circuit; 123-low frequency sampling clock; 130-digital post-processing module; 140-a register unit; 150-CPU; 160-output protection module.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present invention, it is also to be noted that, unless otherwise explicitly specified or limited, the terms "connected" and "connected" are to be interpreted broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art. Some embodiments of the invention are described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.
First embodiment
Referring to fig. 1, an embodiment of the present invention provides a random number generating unit 100, where the random number generating unit 100 includes at least one set of physical random source module 110, a sampling control module 120, a digital post-processing module 130, and a register unit 140, where the at least one set of physical random source module 110, the sampling control module 120, and the digital post-processing module 130 are sequentially electrically connected, and the register unit 140 is electrically connected to the sampling control module 120, the digital post-processing module 130, and each set of physical random source module 110. The physical random source module 110 is configured to generate a random signal, the sampling control module 120 is configured to sample the random signal in a system clock domain, and the digital post-processing module 130 is configured to process the sampled random signal according to a preset algorithm to generate a random number, transmit the random number to the register unit 140, and store the random number through the register unit.
It should be noted that, in this embodiment, the random number generating unit 100 substantially includes a register access interface, and the register access interface is connected to the register unit 140, and meanwhile, the register access interface is used for being connected to a CPU to implement a function that the CPU calls the random number from the register unit 140.
For convenience of description, in this embodiment, the random number generation unit 100 includes 4 sets of physical random source modules 110 for example, but of course, in some other embodiments, more or less sets of physical random source modules 110 may be used to generate the random signal based on actual situations, for example, 3 or 5 sets of physical random source modules 110 are used, and this embodiment is not limited in any way.
In the embodiment, each set of the physical random source modules 110 includes an analog circuit, and generates a random signal through the analog circuit, and the generation of the random signal through the analog circuit can avoid crosstalk between circuits in circuit design, so that the random number generating unit 100 has stronger randomness and better quality of the random number.
In this embodiment, the analog circuit includes at least one high frequency clock circuit and at least one low frequency sampling clock circuit, so as to generate a high frequency oscillation random signal through the high frequency clock circuit or generate a low frequency sampling random signal through the high frequency clock circuit and the low frequency sampling clock circuit, and transmit the generated random signal to the sampling control module 120 for sampling, where each set of physical random source modules 110 can generate a random signal, and thus the randomness of the random number generation unit 100 is gradually improved with the increase of the number of the physical random source modules 110.
Specifically, referring to fig. 2, in the present embodiment, the analog circuits of each set of the physical random source modules 110 include a first high-frequency oscillating random source circuit 121, a second high-frequency oscillating random source circuit 122, and a low-frequency sampling clock, wherein output ends of the first high-frequency oscillating random source circuit 121 and the second high-frequency oscillating random source circuit 122 are electrically connected to an input end of the low-frequency sampling clock circuit, and the low-frequency sampling clock circuit is configured to sample the first high-frequency oscillating random source circuit and the second high-frequency oscillating random source circuit to generate random signals.
The first high-frequency oscillation random source circuit 121 and the second high-frequency oscillation random source circuit 122 each include a plurality of delay units and a selector, wherein the plurality of delay units are sequentially connected in series, and an output end of each delay unit is electrically connected to a port of the selector. The selector can select and conduct different ports after receiving the PRS _ SEL signal, so that oscillation signals generated by different numbers of delay units are received. For example, when the PRS _ SEL signal received by the selector is on for port 10, the oscillation signal received by the selector is the oscillation signal generated by passing through two delay units, and when the PRS _ SEL signal received by the selector is on for port 00, the oscillation signal received by the selector is the oscillation signal generated by passing through four delay units, and the oscillation signals generated by passing through different delay units are different, so that the randomness of the generated random signal can be improved.
After the selector makes a selection, as one implementation, the first and second hf oscillation random source circuits 121 and 122 directly output the generated oscillation signals, i.e., output the hf oscillation random signals (PRS _ PRE _0, PRS _ PRE _1), wherein the hf oscillation clocks avoid crosstalk between circuits in circuit design. As another implementation manner, the analog circuit includes two register modules, oscillation signals output by selectors of the first high-frequency oscillation random source circuit 121 and the second high-frequency oscillation random source circuit 122 are respectively transmitted to the register modules, and the low-frequency sampling clock circuit provides a low-frequency clock signal for the registers, so that sampling of the oscillation signals is realized by using the low-frequency clock signal, and the low-frequency sampling random signals (PRS _1, PRS _0) are output.
The analog circuit further includes a noise amplification circuit electrically connected to the low-frequency sampling clock. By arranging the noise amplification circuit, the phase uncertainty of the low-frequency sampling clock can be increased, and the sampling randomness is further increased. In addition, a voltage stabilizing and filtering circuit is added at the power supply end of the module, and the noise of the power supply and the substrate is shielded as much as possible to reduce the influence of deterministic interference.
Further, in this embodiment, the register unit 140 includes a random number register, a configuration register, and a control register, where the random number register, the configuration register, and the control register are all configured to be electrically connected to the CPU, the random number register is electrically connected to the digital post-processing module 130, the configuration register and the control register are respectively electrically connected to the sampling control module 120 and the digital post-processing module 130, the configuration register is configured to configure the operating modes of at least one set of the physical random source module 110, the sampling control module 120, and the digital post-processing module 130 after receiving a configuration instruction of the CPU, the control register is configured to control the at least one set of the physical random source module 110, the sampling control module 120, and the digital post-processing module 130 to operate after receiving a control instruction of the CPU, and the random number generated by the digital post-processing module 130 is sent to the random number register, the CPU reads the random number from the random number register.
Here, for the physical random source module 110, the operation mode includes outputting a high-frequency oscillation random signal (PRS _ PRE _0, PRS _ PRE _1) or outputting a low-frequency sampling random signal (PRS _1, PRS _0), that is, the configuration register can configure whether the low-frequency sampling clock in the physical random source module 110 samples the oscillation signal. Meanwhile, the control register can control whether each set of physical random source module 110 operates, for example, the control register controls whether it operates by sending an enable signal of PRS _ EN to the first dither random source circuit 121 and the second dither random source circuit 122.
Further, in this embodiment, the configuration register further configures an operation mode of the sampling control module 120 according to the configured operation mode of the physical random source module 110, that is, for the low-frequency sampled random signals (PRS _1 and PRS _0) transmitted by the physical random source module 110, the sampling control module 120 is in a first operation mode, and for the high-frequency oscillating random signals (PRS _ PRE _0 and PRS _ PRE _1) transmitted by the physical random source module 110, the sampling control module 120 is in a second operation mode, which will be described in detail below.
Referring to fig. 3, when the analog circuit outputs the low-frequency sampling random signal, the sampling control module 120 is configured to sample a falling edge of the low-frequency sampling clock of each group of the physical random source modules 110, synchronize the signal of the low-frequency sampling clock to a system clock domain after the falling edge of each low-frequency sampling clock is sampled, that is, after the falling edge of each sampling clock comes, and perform xor processing on all the low-frequency sampling random signals.
Specifically, since the signal needs to be processed in the system clock domain in the subsequent processing of the digital post-processing module 130, the sampling control module 120 needs to complete the sampling of the signal in the clock domain. Accordingly, when the analog circuit outputs the low-frequency sampling random signal, the sampling control module 120 synchronizes the signal of the low-frequency sampling clock to the system clock domain.
The sampling control module 120 includes a plurality of sampling circuits and exclusive-or gates, which are the same as the number of the physical random source modules 110, and this embodiment adopts 4 sampling circuits, and certainly, in some other embodiments, the sampling circuits may also change with the change of the number of the physical random source modules 110, which is not limited in this embodiment.
Each sampling circuit comprises a synchronous circuit, the synchronous circuit is used for detecting a falling edge of a low-frequency clock signal F _ SAMPLE, the output end of the synchronous circuit is connected with an and gate, when 4 synchronous circuits detect the falling edge, the and gate outputs a high-level signal, and after a selector in the sampling circuit receives the high-level signal, the sampling control module 120 synchronizes the low-frequency clock signal to a system clock domain and completes sampling eight low-frequency sampling random signals (each physical random source module 110 generates two low-frequency sampling random signals) in the system clock domain. Then, the random signals sampled by the 4 sampling circuits in the system clock domain are simultaneously output to the xor gate, and after the xor gate is subjected to xor processing of one of 4, the random signals are transmitted to the digital post-processing module 130.
The timing diagram for synthesizing the falling edges of the four low-frequency clock signals is shown in fig. 4, and when the system clock simultaneously acquires the falling edges of the four low-frequency clock signals, the signals are locked for one period to simultaneously latch the four sampling signals, and the sampled signals are synchronized to the system clock domain. Because the four sampling clocks are independent from each other, and the falling edges of the four sampling clocks are unpredictable, after the falling edges of the four sampling clocks are all acquired, the sampled data is used as an input signal of the 8-bit exclusive-OR logic gate.
Referring to fig. 5, when the analog circuit outputs the high-frequency oscillation random signal, the sampling control module 120 is configured to sample each path of the high-frequency oscillation random signal by using the system clock domain, and perform xor processing on the sampled random signal.
Since sampling by the low frequency clock signal is not required when the physical random source module 110 outputs the high frequency oscillation random signal, detection of the falling edge is not required. After receiving the high-frequency oscillation random signal, directly adopting a system clock (500MHz) to sample the high-frequency oscillation random signal, and sampling data
In this embodiment, the digital post-processing module 130 is configured to perform a certain algorithm processing on the xor-processed sampling signal, where the digital post-processing module 130 includes a linear shift feedback register, and the linear shift feedback register is configured to shift the sampled random signal according to the first primitive polynomial or the second primitive polynomial.
Specifically, the digital post-processing module 130 of the present invention adopts a digital post-processing algorithm for processing, wherein, the digital post-processing module 130 supports two primitive polynomials as the polynomial of the linear shift register in a manner of embedding m sequences: are respectively a first primitive polynomial f1(x)＝x193+x173+x159+x113+x65+x22+1 and a second primitive polynomial f2(x)＝x400+x248+1. The post-processing structure diagrams of the linear shift register are respectively shown in fig. 6 and fig. 7. The configuration register can configure the digital post-processing module 130 to process the sampled random signal by using the first primitive polynomial or the second primitive polynomial.
The random output processed by the data post-processing module is transmitted to the random number register, and the CPU can read the random number in the random number register.
The specific work flow of the random generating device provided in this embodiment is that, when the CPU needs to obtain a random number, a configuration signal is first sent to the configuration register, the configuration register configures the working modes of the physical random source module 110, the sampling control module 120, and the digital post-processing module 130, and at the same time, the CPU sends a control instruction to the control register, and controls the physical random source module 110, the sampling control module 120, and the digital post-processing module 130 to start working through the control register, and the random number generated by the physical random source module 110, the sampling control module 120, and the digital post-processing module 130 is stored in the random number register, and the CPU reads the random number from the random number register.
Second embodiment
Referring to fig. 8, another random number generating unit 100 is provided in the embodiment of the present invention, wherein the random number generating unit 100 is substantially the same as the random number generating unit 100 provided in the first embodiment, and therefore, the description of the same parts is omitted in this embodiment.
Specifically, in order to improve the security of the random number generating unit 100 provided in this embodiment, the random number generating unit 100 further includes an output protection module 160, and the register unit 140 further includes a status register, the output protection module 160 is electrically connected to the digital post-processing module 130 and the status register, the output protection module 160 is configured to receive the random number sent by the digital post-processing module 130, determine whether the random number is incorrect, and transmit the determination result to the status register, and the CPU is configured to determine whether to read the random number from the random number register according to the determination result in the status register.
Specifically, the output protection and error detection module is used for performing quality detection and protection on the generated random numbers. The 128-bit random number obtained by the digital post-processing module 130 needs to be subjected to random number error detection, that is, whether the generated random number has a situation that continuous 32 bits are all 0 or all 1 is detected, if all 0 or all 1 occurs, the rng _ gen _ err bit is pulled high, wherein when the rng _ gen _ err outputs a high level, it indicates that the data random number has an error, at this time, the state register is in a random number error state, the CPU is informed that the currently generated true random number has an error, cannot read the random number in the random number register at this time, and needs to discard the random number.
Further, the output protection module 160 is preset with a read time value, and the status register is further configured to limit the number of times that the CPU reads the random number in the random number register within the read time value to be smaller than a preset value.
In order to ensure the safety of the random number, the register for storing the random number is protected by hardware: the obtained random number CPU can only be read once within a predetermined time, that is, the preset value provided in this embodiment is 2, and certainly, in some other embodiments, the value may be set as another number with the set value, which is not limited in this embodiment.
After the random number register receives the random number, the hardware module of the random number generator is set to 1, which indicates that a new 128-bit random number is generated, the 128-bit random number is stored in four random number registers TRNG _ OUTPUT _ 0-TRNG _ OUTPUT _3, the four registers can be read by the CPU only once, after one-time reading, the 4 registers are set to a protection state by the hardware, and the CPU cannot read again. When the ready signal is set to 1 again when a new random number is generated again, the read protection states of the registers TRNG _ OUTPUT _0 to TRNG _ OUTPUT _3 are cleared by the hardware. If the CPU does not actively clear the ready after reading the random number last time, when a new random number is generated, the hardware firstly clears the ready signal and then sets 1 to inform the CPU that the new random number is generated. In addition, a timeout value for allowing the CPU to read the random number register is set in the protection circuit, and when the timer reaches the timeout value, the random number is not allowed to be read by the CPU. For example, the timeout value may be set to a value of 1ms or the like.
Third embodiment
The embodiment of the present invention further provides a random number generating device, where the random number generating device includes a CPU and a random number generating unit as described in the first embodiment or the second embodiment, where the random number generating unit includes a register access interface, the register access interface is connected to the register unit, and the register access interface is connected to the CPU, so as to implement a function of the CPU calling the random number from the register unit. In summary, the present invention provides a random number generating unit and a device, where the random number generating unit includes at least one set of physical random source module, a sampling control module, and a digital post-processing module, the at least one set of physical random source module, the sampling control module, and the digital post-processing module are electrically connected in sequence, the physical random source module includes an analog circuit and generates a random signal through the analog circuit, the sampling control module is configured to sample the random signal in a system clock domain, and the digital post-processing module is configured to process the sampled random signal according to a preset algorithm to generate a random number. Because the invention generates the random signal through the analog circuit, the crosstalk between the circuits is avoided in the circuit design, thereby achieving the effects of stronger randomness of the random number generating unit and better quality of the random number.
It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention. It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
Claims (10)
1. A random number generation unit is characterized by comprising at least one group of physical random source modules, a sampling control module and a digital post-processing module, wherein the at least one group of physical random source modules, the sampling control module and the digital post-processing module are sequentially and electrically connected, the physical random source modules comprise analog circuits and generate random signals through the analog circuits, the sampling control module is used for sampling the random signals in a system clock domain, and the digital post-processing module is used for processing the sampled random signals according to a preset algorithm to generate random numbers;
the analog circuit comprises at least one high-frequency clock circuit and at least one low-frequency sampling clock circuit, and a high-frequency oscillation random signal is generated through the high-frequency clock circuit or a low-frequency sampling random signal is generated through the high-frequency clock circuit and the low-frequency sampling clock circuit;
the analog circuit comprises a first high-frequency oscillation random source circuit, a second high-frequency oscillation random source circuit and a low-frequency sampling clock circuit, wherein the first high-frequency oscillation random source circuit and the second high-frequency oscillation random source circuit respectively comprise a plurality of delay units and selectors, the delay units are sequentially connected in series, and the output end of each delay unit is electrically connected with the port of the selector;
when the analog circuit outputs low-frequency sampling random signals, the sampling control module is used for sampling the falling edge of the low-frequency sampling clock of each group of physical random source modules, synchronizing the signals of the low-frequency sampling clock to a system clock domain after the falling edge of each path of sampling clock comes, and performing exclusive-or processing on all the low-frequency sampling random signals;
when the analog circuit outputs a high-frequency oscillation random signal, the sampling control module is used for sampling each path of the high-frequency oscillation random signal by adopting a system clock domain and carrying out XOR processing on the sampled random signal.
2. The random number generating unit according to claim 1, wherein said first high frequency oscillating random source circuit and said second high frequency oscillating random source circuit constitute a two-way high frequency clock circuit, and said first high frequency oscillating random source circuit, said second high frequency oscillating random source circuit and said low frequency sampling clock circuit constitute a two-way low frequency sampling clock circuit.
3. The random number generating unit of claim 2, wherein the outputs of the first high frequency oscillating random source circuit and the second high frequency oscillating random source circuit are each electrically connected to an input of the low frequency sampling clock circuit, the low frequency sampling clock circuit being configured to sample the first high frequency oscillating random source circuit and the second high frequency oscillating random source circuit to generate random signals.
4. The random number generating unit of claim 1, further comprising a register unit electrically connected to the sampling control module, the digital post-processing module, and each set of the physical random source modules, respectively, the register unit further configured to be electrically connected to a CPU.
5. The random number generating unit according to claim 4, wherein the register unit comprises a random number register, a configuration register and a control register, the random number register, the configuration register and the control register are all configured to be electrically connected to the CPU, the random number register is electrically connected to the digital post-processing module, the configuration register and the control register are electrically connected to the at least one set of physical random source module, the sampling control module and the digital post-processing module, respectively, the configuration register is configured to configure the operation modes of the sampling control module and the digital post-processing module after receiving the configuration instruction of the CPU, the control register is configured to control the at least one set of physical random source module, the sampling control module and the digital post-processing module to operate after receiving the control instruction of the CPU, and the random number generated by the digital post-processing module is sent to the random number register, and the CPU reads the random number from the random number register.
6. The random number generating unit according to claim 5, wherein the random number generating unit further comprises an output protection module, the register unit further comprises a status register, the output protection module is electrically connected to the digital post-processing module and the status register, respectively, the output protection module is configured to receive the random number sent by the digital post-processing module, determine whether the random number is incorrect, and transmit a determination result to the status register, and the CPU is configured to determine whether to read the random number from the random number register according to the determination result in the status register.
7. The random number generation unit of claim 6, wherein the output protection module is further preset with a read time value, and the control register is further configured to limit the number of times the CPU reads the random number in the random number register within the read time value to be less than a preset value.
8. The random number generating unit of claim 1, wherein said analog circuit further comprises a noise amplification circuit, said noise amplification circuit being electrically connected to said low frequency sampling clock.
9. The random number generation unit of claim 1, wherein the digital post-processing module comprises a linear shift feedback register for shifting the sampled random signal according to either the first or second primitive source polynomial.
10. A random number generating apparatus, characterized in that the random number generating apparatus comprises a random number generating unit according to any one of claims 1 to 9.
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