WO2019113844A1

WO2019113844A1 - Method for generating random number, chip, and electronic device

Info

Publication number: WO2019113844A1
Application number: PCT/CN2017/115956
Authority: WO
Inventors: 严可
Original assignee: 深圳市汇顶科技股份有限公司
Priority date: 2017-12-13
Filing date: 2017-12-13
Publication date: 2019-06-20
Also published as: CN110249299A

Abstract

A method for generating a random number, a chip, and an electronic device. The method comprises: obtaining an entropy source, the entropy source comprising a physical random number and information of a chip (S210); generating a random number seed according to the entropy source (S220); and generating a random number according to the random number seed and an encryption algorithm of the chip (S230). The method can improve the quality of a random number generated by a chip.

Description

Method, chip and electronic device for generating random numbers

Technical field

The present invention relates to the field of information technology, and more particularly to a method, a chip and an electronic device for generating a random number by a chip.

Background technique

Random numbers have a wide range of applications in radar systems, secure communication systems, and simulations.

Random numbers are an important part of the cryptosystem and are the cornerstone of many applications such as private key generation, signature, key negotiation, and challenge authentication. In Microsoft's research on cryptosystems such as Bitcoin, Secure Shell (SSH), Transport Layer Security (TLS) and Australian electronic ID cards, random number generation is a weak link in the above applications. Breaking the random number means breaking the entire cryptosystem. Therefore, the quality of random number generation directly determines the security of the cryptosystem.

Embedded security encryption chips are limited by size, power consumption and computing resources, and cannot implement complex physical or chemical entropy sources. Usually, the signal noise of integrated circuits is used to generate physical random numbers, such as direct amplifiers, oscillatory samples, and discrete chaotic systems. The security of the physical random number generated by the above method is affected by the working state of the component, the circuit and the environment, and the security of the generated physical random number is difficult to meet the requirements of the cryptographic system application.

Summary of the invention

The present application provides a method, a chip and an electronic device for generating a random number, which can improve the random number quality of the chip.

In a first aspect, a method of generating a random number is provided, comprising:

Obtaining an entropy source, the entropy source including physical random numbers and chip information;

Generating a random number seed according to the entropy source;

A random number is generated based on the random number seed and the encryption algorithm of the chip.

The technical solution of the embodiment of the present invention uses a physical random number as an entropy source, generates a random number seed by using chip information, and generates a random number based on a chip encryption algorithm, which can improve the random number quality of the chip without adding an additional circuit. Thereby, the efficiency of generating a random number can be improved.

In some possible implementations, generating a random number includes:

A random number is generated based on the random number seed, the historical random number information, and the encryption algorithm.

In some possible implementations, the encryption algorithm is a secure hash algorithm SHA or an advanced encryption standard AES.

In some possible implementation manners, the encryption algorithm value r _k when the kth generation random number is generated according to the following equation is obtained,

r _k =SHA256(r _k-1 ||seed _k )

Wherein, SHA256() represents the SHA function, || represents splicing, r _k-1 represents the encryption algorithm value when the k-1th generation random number is generated, and seed _k represents the random number seed when the kth generation random number is generated;

The kth random number is generated according to r _k .

Among them, AES _key () represents the AES function, || represents splicing, r _k-1 represents the encryption algorithm value when the k-1th generation random number is generated, and seed _k represents the random number seed when the kth generation random number is generated;

The kth random number is generated according to r _k .

In some possible implementations, the kth random number s _k is generated according to the following equation,

Where r _k,i represents the ith block of r _k ,

Indicates XOR.

In some possible implementations, the information of the chip includes at least one of an identifier ID, a name, and a description.

In some possible implementations, the random number seed seed _k when the kth generation of the random number is generated according to the following equation is generated,

Wherein b _i represents the i-th block divided by a predetermined number of bytes, N represents the total number of blocks, || represents splicing, and ID, Name _ID and Description _ID respectively represent the ID, name and description of the chip.

Indicates XOR, and p _k represents the physical random number when the random number is generated for the kth time.

In a second aspect, a chip is provided, comprising:

An entropy source acquiring unit, configured to acquire an entropy source, where the entropy source includes physical random numbers and chip information;

a random number seed generating unit, configured to generate a random number seed according to the entropy source;

And a processing unit, configured to generate a random number according to an encryption algorithm of the random number seed and the chip.

In some possible implementations, the processing unit is specifically configured to generate a random number according to the random number seed, the historical random number information, and the encryption algorithm.

In some possible implementations, the processing unit is specifically configured to: obtain an encryption algorithm value r _k when the kth generation random number is generated according to the following equation,

r _k =SHA256(r _k-1 ||seed _k )

Wherein, SHA256() represents the SHA function, || represents splicing, r _k-1 represents the encryption algorithm value when the k-1th generation of the random number is generated, and seed _k represents the random number seed when the kth generation of the random number is generated;

The kth random number is generated based on the r _k .

Wherein, AES _key () represents an AES function, || represents splicing, r _k-1 represents an encryption algorithm value when k-1th generation of a random number, and seed _k represents a random number seed when a k-th generation of a random number is generated; The kth random number is generated according to r _k .

In some possible implementations, the processing unit is specifically configured to: generate a kth random number s _k according to the following equation,

Where r _k,i represents the ith block of r _k ,

Indicates XOR.

In some possible implementations, the random number seed generating unit is specifically configured to: generate a random number seed seed _k when generating the random number for the kth time according to the following equation,

The exclusive OR is expressed, and p _k represents the physical random number when the random number is generated for the kth time.

In a third aspect, a chip, including a memory and a processor, is provided that can perform the method of the first aspect described above or any possible implementation thereof.

In a fourth aspect, an electronic device is provided, comprising the chip in the second aspect or any possible implementation thereof, or the chip of the third aspect.

In a fifth aspect, a computer storage medium is provided having stored therein program code, the program code being operative to indicate a method of performing the first aspect described above or any possible implementation thereof.

In a sixth aspect, a computer program product comprising instructions, when executed on a computer, causes the computer to perform the method of the first aspect described above or any of its possible implementations.

DRAWINGS

FIG. 1 is a schematic diagram of an application scenario of a technical solution according to an embodiment of the present invention.

2 is a schematic flow chart of a method for generating a random number according to an embodiment of the present invention.

FIG. 3 is a schematic flowchart of a method for generating a random number according to still another embodiment of the present invention.

4 is a schematic structural view of a chip according to an embodiment of the present invention.

FIG. 5 is a schematic structural view of a chip according to still another embodiment of the present invention.

Detailed ways

The technical solutions in the embodiments of the present invention will be described below with reference to the accompanying drawings.

The quality of the random number generation directly determines the security of the cryptosystem. Subsequent processing of physical random numbers is an important means to guarantee the quality of random numbers. Algorithm selection needs to have the characteristics of forward unpredictability, backward unpredictability, independent and identical distribution. The embedded security encryption chip usually has encryption, hash and other arithmetic modules with the above characteristics.

In the embodiment of the present invention, the physical random number is used as the entropy source, supplemented by the information of the embedded security encryption chip (such as ID, device name, etc.), based on the basic computing functions provided by the existing module of the embedded security encryption chip. The existing modules are used to generate random numbers. The generated random numbers have the characteristics of forward unpredictability, backward unpredictability, independent and identical distribution, which can improve the random number quality of the embedded security encryption chip. Moreover, the technical solution of the embodiment of the present invention does not need to add additional circuits, so that fast, efficient, low-cost, high-quality random number generation can be realized.

It should be understood that the present specification describes various embodiments by using an embedded secure encryption chip as an example, but the present invention This is not limited to this, that is, the embedded security encryption chip can also be converted to other chips.

FIG. 1 is a schematic diagram of an application scenario of a technical solution according to an embodiment of the present invention. The electronic device 100 in FIG. 1 may be an electronic device that uses an embedded secure encryption chip.

It should be understood that, although not shown in FIG. 1, the electronic device 100 may include other modules or units in addition to the embedded security encryption chip 120, which is not specifically limited in the present invention.

As shown in FIG. 1, the embedded secure encryption chip 120 can process the input data 110 to obtain output data 130. In some embodiments, the embedded secure encryption chip 120 can encrypt the input data 110 through its internal cryptographic module. In some embodiments, the embedded security encryption chip 120 may also apply the technical solution of the embodiment of the present invention to generate a random number.

2 shows a schematic flow diagram of a method 200 of generating a random number in accordance with an embodiment of the present invention. The method can be performed by the electronic device 100 or the embedded secure encryption chip 120 of FIG.

S210. Acquire an entropy source, where the entropy source includes information of a physical random number and a chip.

An entropy source is obtained in S210, in which a physical random number is utilized, supplemented by information of the chip.

Specifically, the physical random number (circuit noise collected by the physical device) is implemented by using an oscillation sampling method. The jitter of a typical clock is about one thousandth of a clock cycle, so a low-frequency clock is used to sample an independent clock source with a frequency of more than 1000 times to generate a physical random number. In the embodiment of the present invention, optionally, a low frequency 32K clock may be used to sample the high frequency 48M clock in S210, and there is a probability of sampling to a high level or a low level of the high frequency clock to generate 1 bit. 1 or 0 of (bit), by splicing, the generated physical random number is 32 bits. In the embodiment of the present invention, the generation of the random number is 32 bits as an example and is not limited. In the embodiment of the present invention, each time a random number is generated, the physical random number is updated. Therefore, as the number of random number generation increases, the randomness of the physical random number input in the system entropy source is stronger.

The information of the chip may include at least one of an ID, a name, and a description of the chip, which is not limited by the embodiment of the present invention.

S220. Generate a random number seed according to the entropy source.

The random number seed is a random number with the random number (seed) as the initial condition with the random number as the object, by using a true random number (seed) as the initial condition, and then using a certain algorithm to generate the random number. General computer random numbers are pseudo-random numbers. Real random numbers are generated by physical processes rather than computer programs to generate random numbers, for example, based on microscopic phenomena that generate low-level, statistically random "noise" signals, such as thermodynamic noise. , photoelectric effect and quantum phenomenon. These physical processes are theoretically completely unpredictable and have been confirmed by experiments. Random hardware The number generator is usually composed of a transducer, an amplifier, and an analog to digital converter. The transducer is used to convert some effects of the physical process into electrical signals, the amplifier and its circuitry are used to amplify the amplitude of the random disturbance to the macro level, and the analog to digital converter is used to convert the output into a digital, usually Binary zero and one. By repeatedly sampling these random signals, a series of random numbers are generated. When a random seed or random function is stolen, the sequence of random numbers it generates may also be predicted and invalidated. Therefore, the generation of random number seeds has a crucial impact on the generation of random numbers.

Specifically, in S220, in one embodiment of the present invention, information of the chip is first spliced and segmented by a predetermined number of bytes. The information of the chip includes related information such as the ID, name and description of the chip. In one embodiment of the invention, a block of 4 bytes is taken as an example:

(b ₁ ,b ₂ ,...,b _N )=ID||Name _ID ||Description _ID (1)

The random number seed seed _k when generating the random number for the _{kth time} is:

Where b _i denotes the i-th block divided by 4 bytes, N denotes the total number of blocks, || denotes splicing, ID, Name _ID and Description _ID respectively represent the ID, name and description of the chip,

Therefore, the final output random number seed is a random number seed after the physical random number and the chip information are spliced.

It should be understood that the 4 byte block mentioned in this embodiment is only a specific embodiment, specifically, the block is divided according to a preset byte, and the preset byte is not specifically limited in the present invention.

In the embodiment of the present invention, the finally output random number seed is an exclusive OR of the information of the chip spliced by the preset byte and the physical random number when the kth generation of the random number is generated, and each time the random number is generated, The physical random number will be updated, so as the number of generations increases, the randomness of the system gradually increases.

S230. Generate a random number according to an encryption algorithm of the random number seed and the chip.

In the embodiment of the present invention, the existing encryption algorithm of the chip is used to generate a random number, that is, an existing module in the multiplexing chip, so that no additional circuit is needed to implement other algorithms.

Optionally, in S230, a random number may be generated according to the random number seed, the historical random number information, and the chip encryption algorithm.

The historical random number information is information when a random number was previously generated. The historical random number information can be saved for subsequent generation of random numbers, thereby increasing the entropy of the newly generated random numbers.

There may be one or more encryption algorithms in the chip. One embodiment of the present invention may utilize one of the encryption algorithms. The following is a Secure Hash Algorithm (SHA) and high The two encryption algorithms of the Advanced Encryption Standard (AES) are described as an example, but the embodiment of the present invention is not limited thereto.

When the hash module is implemented in the chip, when the SHA algorithm can be implemented, the encryption algorithm value r _k when the k-th generation random number is generated can be obtained according to the following equation.

r _k =SHA256(r _k-1 ||seedk) (3)

Among them, SHA256() represents the SHA function, || represents the splicing, r _k-1 represents the encryption algorithm value when the k-1th generation of the random number is generated, and seed _k represents the random number seed when the k-th generation of the random number is generated.

It can be seen from equation (3) that when calculating the encryption algorithm value r _k when the k-th generation of the random number is generated, the encryption algorithm value r _k-1 when the k-1th generation of the random number is generated is used, and so on, previously generated. All random numbers affect the calculation of the current encryption algorithm value. Therefore, as the number of generations increases, the randomness of the output random number is stronger.

Alternatively, r _k-1 can be saved in the chip. Further, SHA256() is only one of the SHA functions, and is merely by way of example and not limitation in the embodiments of the present invention.

The output of the function SHA2-256 is 256 bits, that is, 8 blocks, each block is 4 bytes, so that the i-th block is r _k,i , then

r _k =(r _k,1 ,r _k,2 ,r _k,3 ,r _k,4 ,r _k,5 ,r _k,6 ,r _k,7 ,r _k,8 ) (4)

The kth random number s _k can be generated according to the following equation:

Where r _k,i represents the ith block of r _k ,

Indicates XOR.

The random number quality was tested using the NIST800-22 random number test tool. The test results are shown in Table 1. (Note: All test items pass before they pass)

Table 1

It can be seen from Table 1 that the technical solution of the embodiment of the present invention can significantly improve the quality of random number generation. Moreover, the technical solution of the embodiment of the present invention does not need to add a new hardware circuit, and generates a random number by using a module that is provided by the security encryption chip, which has high efficiency.

If there are no hash modules in the chip, other modules can be used, such as the AES module. In this case, the encryption algorithm value r _k at the kth generation of the random number can be obtained according to the following equation,

Among them, AES _key () indicates the AES function, || indicates splicing, r _k-1 indicates the encryption algorithm value when the k-1th generation random number is generated, and seed _k indicates the random number seed when the k-th generation random number is generated.

Then, the kth random number s _k can be obtained again according to the above equations (4) and (5).

In the embodiment of the present invention, each newly generated entropy source (newly acquired physical random number) is generated by each random number generation, and the information of the previous entropy source is saved by using the encryption module, so that the generated random number has backward unpredictability. In the embodiment of the present invention, the physical random number is not directly output, and the attacker cannot design the attack algorithm by collecting physical random numbers. The characteristics of the cryptographic module in the embodiment of the present invention ensure that even if the input physical random number does not have the independent and identical distribution property, the generated random number has the independent and identical distribution property. Therefore, the random number generated by the technical solution of the embodiment of the present invention has higher quality.

In addition, in the embodiment of the present invention, no additional complicated circuit is needed, and the basic algorithm based on the existing modules in the chip is used to multiplex the corresponding algorithm, and the random number is generated according to the random number seed and the corresponding algorithm, which can achieve fast, effective, and low cost. , the generation of high quality random numbers.

Therefore, the technical solution of the embodiment of the present invention uses the physical random number as the entropy source, supplements the information of the chip to generate a random number seed, and generates a random number based on the chip encryption algorithm, thereby improving the chip. The quality of the random number and the need to add additional circuitry can increase the efficiency of generating random numbers.

FIG. 3 is a schematic flowchart of a method 300 for generating a random number by a chip according to still another embodiment of the present invention. For a detailed description of the embodiments, reference may be made to the foregoing embodiments, and for brevity, the details are not described below.

310, input information about the chip.

320, input a physical random number.

310, 320 is a source of entropy for obtaining input. For specific description, reference may be made to the related description of S210 in the foregoing embodiment.

330. Generate a random number seed 340 according to the input entropy source. For a detailed description, reference may be made to the related description of S220 in the foregoing embodiment.

350: Generate a random number according to an encryption algorithm of the random number seed and the chip. For a detailed description, reference may be made to the related description of S230 in the foregoing embodiment.

360, the random number generated in the output 350. The previous random number information can be used to generate a random number subsequently.

The method of generating a random number by the chip of the embodiment of the present invention is described in detail above, and the chip and the electronic device of the embodiment of the present invention will be described below. It should be understood that the chip and the electronic device of the embodiments of the present invention may perform the foregoing various methods of the embodiments of the present invention, that is, the specific working processes of the following various products, and may refer to the corresponding processes in the foregoing method embodiments.

FIG. 4 is a schematic structural view of a chip 400 according to an embodiment of the present invention. As shown in FIG. 4, the chip 400 includes:

An entropy source acquiring unit 410, configured to acquire an entropy source; the entropy source includes information of a physical random number and a chip;

a random number seed generating unit 420, configured to generate a random number seed according to the entropy source;

The processing unit 430 is configured to generate a random number according to an encryption algorithm of the random number seed and the chip.

In the embodiment of the present invention, a random number is generated by using a physical random number as an entropy source, supplemented by chip information (such as ID, device name, etc.), and a chip-based encryption algorithm. That is to say, the processing unit 430 multiplexes the existing modules in the chip, and utilizes the existing algorithm to realize fast, efficient, low-cost, high-quality random number generation without adding additional circuits.

Therefore, the chip of the embodiment of the present invention uses the physical random number as the entropy source, supplements the chip information to generate a random number seed, and generates a random number based on the chip encryption algorithm, which can improve the random number quality of the chip without adding an additional circuit. , thereby improving the efficiency of generating random numbers.

In an embodiment of the present invention, the entropy source obtaining unit 410 is specifically configured to:

The information of the chip includes at least one of an identification ID, a name, and a description.

In an embodiment of the present invention, optionally, the random number seed generating unit 420 is specifically configured to:

Generating a random number seed seed _k when generating the random number for the kth time according to the following equation,

In an embodiment of the present invention, the processing unit 430 is specifically configured to:

A random number is generated according to the random number seed, the historical random number information, and the chip encryption algorithm.

In an embodiment of the present invention, optionally, the processing unit 430 may multiplex modules in the chip, and may determine an encryption algorithm according to the corresponding module.

For example, when the chip includes a hash module, the random hash function SHA may be used to process the random number seed and generate a random number of the encryption chip; or

When the chip does not have a hash module, the random number seed can be processed by the advanced encryption standard AES and a random number of the encryption chip is generated.

Processing unit 430 multiplexes existing modules in the chip without adding additional circuitry.

It should be understood that the hash module and the encryption module (AES module) in the embodiment of the present invention are not specifically limited. When other modules exist in the chip, the processing unit 430 may reuse other modules and utilize the algorithm provided by the module.

Alternatively, if the chip has a hash module, the processing unit 430 can multiplex the hash module. In this case, the processing unit 430 is specifically configured to:

Obtaining the encryption algorithm value r _k when the kth generation of the random number is obtained according to the following equation,

r _k =SHA256(r _k-1 ||seed _k )

Generating the kth random number s _k according to the following equation,

Where r _k,i represents the ith block of r _k ,

Indicates XOR.

Alternatively, if there is no hash module in the chip, the processing unit 430 can reuse the AES module. In this case, the processing unit 430 is specifically configured to:

Generating the kth random number s _k according to the following equation,

Where r _k,i represents the ith block of r _k ,

Indicates XOR.

FIG. 5 shows a schematic structural view of a chip 500 according to still another embodiment of the present invention.

As shown in FIG. 5, the chip 500 can include a processor 510 and a memory 520. The memory 520 is for storing computer executable instructions. The processor 510 is configured to access the memory 520 and execute the computer executable instructions to perform the operations in the methods of the various embodiments of the present invention described above.

An embodiment of the present invention further provides an electronic device, which may include the chip of the various embodiments of the present invention described above.

It should be understood that the embedded security encryption chip in the embodiment of the present invention is only an example, and may also be other chips. The encryption module may also be other operation modules, as long as the operation module has forward unpredictability and backward direction. Unpredictability, independent and identical distribution.

It is to be understood that the specific embodiments of the present invention are not intended to limit the scope of the embodiments of the invention.

It should be understood that the formulas in the embodiments of the present invention are only examples, and are not intended to limit the scope of the embodiments of the present invention, and the formulas may be modified, and such modifications are also within the scope of the present invention.

It should also be understood that, in various embodiments of the present invention, the size of the sequence numbers of the processes does not imply a sequence of executions, and the order of execution of the processes should be determined by its function and internal logic, and should not be construed as an embodiment of the present invention. The implementation process constitutes any limitation.

It should also be understood that in the embodiments of the present invention, the term "and/or" is merely an association describing the associated object, indicating that there may be three relationships. For example, A and/or B may indicate that A exists separately, and A and B exist simultaneously, and B cases exist alone. In addition, the character "/" in this article generally indicates that the contextual object is an "or" relationship.

Those of ordinary skill in the art will appreciate that the elements and algorithm steps of the various examples described in connection with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both, for clarity of hardware and software. Interchangeability, the composition and steps of the various examples have been generally described in terms of function in the above description. Whether these functions are implemented in hardware or software Line, depending on the specific application and design constraints of the technical solution. A person skilled in the art can use different methods for implementing the described functions for each particular application, but such implementation should not be considered to be beyond the scope of the present invention.

A person skilled in the art can clearly understand that, for the convenience and brevity of the description, the specific working process of the system, the device and the unit described above can refer to the corresponding process in the foregoing method embodiment, and details are not described herein again.

In the several embodiments provided by the present application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the device embodiments described above are merely illustrative. For example, the division of the unit is only a logical function division. In actual implementation, there may be another division manner, for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, or an electrical, mechanical or other form of connection.

The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the embodiments of the present invention.

In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a standalone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention contributes in essence or to the prior art, or all or part of the technical solution may be embodied in the form of a software product stored in a storage medium. A number of instructions are included to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like. .

The above description is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited. In this regard, any equivalent modifications or alterations are obvious to those skilled in the art within the scope of the present invention, and such modifications and alterations are intended to be included within the scope of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

A method for generating a random number, the method comprising:

Obtaining an entropy source, the entropy source including physical random number and chip information;

Generating a random number seed according to the entropy source;

A random number is generated according to the random number seed and the encryption algorithm of the chip.
The method of claim 1 wherein said generating a random number comprises:

And generating a random number according to the random number seed, the historical random number information, and the encryption algorithm.
The method according to claim 1 or 2, wherein the encryption algorithm is a secure hash algorithm SHA or an advanced encryption standard AES.
The method according to any one of claims 1 to 3, wherein said generating a random number comprises:

Obtaining the encryption algorithm value r k when the kth generation of the random number is obtained according to the following equation,

r k =SHA256(r k-1 ||seed k )

Wherein, SHA256( ) represents a SHA function, || represents a splicing, r k-1 represents an encryption algorithm value when a k-1th generation random number is generated, and seed k represents a random number seed when the kth generation of a random number is generated;

A kth random number is generated based on the r k .
The method according to any one of claims 1 to 3, wherein said generating a random number comprises:

Obtaining the encryption algorithm value r k when the kth generation of the random number is obtained according to the following equation,

Wherein, AES key ( ) represents an AES function, || represents splicing, r k-1 represents an encryption algorithm value when k-1th generation of a random number, and seed k represents a random number seed when a k-th generation of a random number is generated;

A kth random number is generated based on the r k .
The method according to claim 4 or 5, wherein the generating the kth random number according to the r k comprises:

Generating the kth random number s k according to the following equation,

Where r k,i represents the ith block of r k ,
Indicates XOR.
The method according to any one of claims 1 to 6, wherein the information of the chip comprises at least one of an identification ID, a name, and a description.
The method according to any one of claims 1 to 7, wherein the basis The entropy source generates a random number seed, including:

Generating a random number seed seed k when generating the random number for the kth time according to the following equation,

(b 1 ,b 2 ,...,b N )=ID||Name ID ||Description ID

Wherein b i represents the i-th block divided by a predetermined number of bytes, N represents the total number of blocks, || represents splicing, and ID, Name ID and Description ID respectively represent the ID, name and description of the chip.
Indicates XOR, and p k represents the physical random number when the random number is generated for the kth time.
A chip characterized by comprising:

An entropy source acquiring unit, configured to acquire an entropy source, where the entropy source includes a physical random number and information of the chip;

a random number seed generating unit, configured to generate a random number seed according to the entropy source;

And a processing unit, configured to generate a random number according to the encryption algorithm of the random number seed and the chip.
The chip according to claim 9, wherein the processing unit is specifically configured to:

And generating a random number according to the random number seed, the historical random number information, and the encryption algorithm.
The chip according to claim 9 or 10, wherein the encryption algorithm is a secure hash algorithm SHA or an advanced encryption standard AES.
The chip according to any one of claims 9 to 11, wherein the processing unit is specifically configured to:

Obtaining the encryption algorithm value r k when the kth generation of the random number is obtained according to the following equation,

r k =SHA256(r k-1 ||seed k )

Wherein, SHA256( ) represents the SHA function, || represents splicing, r k-1 represents the encryption algorithm value when the k-1th generation of the random number is generated, and seed k represents the random number seed when the kth generation of the random number is generated; The r k generates a kth random number.
The chip according to any one of claims 9 to 11, wherein the processing unit is specifically configured to:

Obtaining the encryption algorithm value r k when the kth generation of the random number is obtained according to the following equation,

Wherein, AES key ( ) denotes an AES function, || denotes splicing, r k-1 denotes an encryption algorithm value when k-1th generates a random number, and seed k denotes a random number seed when kth generates a random number; A kth random number is generated based on the r k .
The chip according to claim 12 or 13, wherein the processing unit is specifically configured to:

Generating the kth random number s k according to the following equation,

Where r k,i represents the ith block of r k ,
Indicates XOR.
The chip according to any one of claims 9 to 14, wherein the information of the chip comprises at least one of an identification ID, a name, and a description.
The chip according to any one of claims 9 to 15, wherein the random number seed generating unit is specifically configured to:

Generating a random number seed seed k when generating the random number for the kth time according to the following equation,

(b 1 ,b 2 ,...,b N )=ID||Name ID ||Description ID

Wherein b i represents the i-th block divided by a predetermined number of bytes, N represents the total number of blocks, || represents splicing, and ID, Name ID and Description ID respectively represent the ID, name and description of the chip.
Indicates XOR, and p k represents the physical random number when the random number is generated for the kth time.
A chip characterized by comprising:

Memory for storing programs;

A processor for executing a program stored in the memory, the processor for performing the method of any one of claims 1-8 when the program is executed.
An electronic device, comprising: the chip according to any one of claims 9-17.