WO2006134539A1

WO2006134539A1 - Serial interface and process for real-time bit error rate testing

Info

Publication number: WO2006134539A1
Application number: PCT/IB2006/051858
Authority: WO
Inventors: Henricus Petronella Maria Derckx; Dolf Ruigt
Original assignee: Koninklijke Philips Electronics N.V.
Priority date: 2005-06-13
Filing date: 2006-06-12
Publication date: 2006-12-21
Also published as: WO2006134539A9

Abstract

A serial interface (IFl, IF2) is intended for being connected to data communication equipments in a communication network and is adapted to transmit and/or receive streams of serial data blocks. This serial interface (IFl, IF2) comprises i) a detection means (DM) for reading at least partly each received stream data block to detect a parity data included in each data block, ii) a control means (CM) for checking the parity of the data contained in each received stream data block (excepted the associated parity data) in order to deliver a computed parity data, iii) a first storing means (Ml) for storing a value representative of the number of parity failures, and iv) a processing means (PM) for comparing each detected parity data to the corresponding computed parity data, in order to deliver a comparison data representative of a parity success or failure, and, in case of comparison data representative of a parity failure, to increment by one the value stored into the first storing means (Ml) and then to carry out a new parity comparison relative to the next stream data block.

Description

SERIAL INTERFACE AND PROCESS FOR REAL-TIME BIT ERROR RATE TESTING

The present invention relates to the domain of data communication equipment, and more precisely to bit error rate (BER) testing of data communication equipments, such as serial interfaces.

Bit error rate testing (BERT) is a well-known method for testing data communication equipments during a test and design phase, or a qualification phase, or a release phase, or else a repairing phase. This kind of test aims at determining if a data communication equipment is adapted to process or transmit and/or receive data streams made of blocks of data bits, taking into account its future application. It may also help to determine the cause of a transmission and/or processing problem.

Various tests may be used for testing various processing or transmission parameters. For instance when a BERT concerns an interface it may consist in determining the ratio (or BER) between the number of data bit transmission errors in a transmitted data stream and the number of bits contained in this transmitted data stream.

Most of these tests are performed in a laboratory by means of a test installation and dedicated BERT equipments, such as pattern generator and data analyzer, which are coupled to the data communication equipments involved in the test, inside the test installation. These dedicated BERT equipments and test installation are generally sophisticated and expensive, and usually require a skilled technician to be operated. Moreover in case of equipment failure a skilled technician must go to the location where the equipment stands to perform in situ tests on it. More they do not allow real-time BERTs.

Several solutions have been proposed to try to reduce the cost of BERTs. One of these solutions is described in the patent document US 6,108,801. It consists in providing, into the equipment to be tested, a BERT pattern generator for generating pseudo-random or repetitive dedicated test patterns (or profiles). When a test has to be performed, the generator transmits one test pattern to a dedicated server connected to the communication network, which transmits it back to the equipment under test in order its generator compare the received test pattern to the one initially transmitted.

Such a solution does not only require the intervention of a dedicated server which introduces additional costs, but also the definition of dedicated test patterns (or profiles) which are not easy to conceive and therefore introduce some more costs. Moreover it does not allow realtime BERTs.

So, the object of this invention is to improve the situation in the case of serial interfaces. For this purpose, it provides a serial interface intended for being connected to data communication equipments in a communication network and adapted to transmit streams of serial data blocks.

This serial interface is characterized in that it comprises:

- a detection means arranged to read at least partly each received stream data block to detect a parity data included in each data block, - a control means arranged to check the parity of the data contained in each received stream data block (excepted the associated parity data) in order to deliver a computed parity data,

- a first storing means for storing a value representative of a number of parity failures, and

- a processing means arranged to compare each detected parity data to the corresponding computed parity data, in order to deliver a comparison data representative of a parity success or failure, and, in case of comparison data representative of a parity failure, to increment by one (1) the value stored into the first storing means and then to carry out a new parity comparison relative to the next stream data block.

The data communication equipment according to the invention may include additional characteristics considered separately or combined, and notably : - it may further comprises a second storing means for storing a value representative of the total number of data bits contained into the received stream data blocks;

>^■ its processing means may be arranged to access to the first and second storing means to read the stored values, and then to divide these values therebetween to deliver a value representative of the bit error rate (BER); - its processing means may implement a logic EXOR (exclusive OR) function for the parity comparison;

- its first and/or second storing means may be arranged to be read out by a remote network equipment;

- its first storing means may be arranged to have its stored value set and/or reset by a remote network equipment;

- its second storing means may be arranged to have its stored value set and/or reset by a remote network equipment;

- it may further comprise a transmission means arranged to incorporate a parity data into each associated stream data block before transmitting it; > the transmission means may be arranged to incorporate the parity data at the driver end of the associated stream data block.

The invention also provides a real-time bit error rate testing method for a serial interface interconnecting first and second data communication equipments of a communication network and adapted to transmit stream of serial data blocks.

This method is characterized in that it consists:

- in incorporating a parity data into each stream data block before transmitting it serially to the serial interface, and

- each time the serial interface receives a stream data block, • in reading at least partly this stream data block to detect its parity data,

• then in checking the parity of the data contained in this received stream data block (excepted its associated parity data) in order to deliver a computed parity data,

• then in comparing the detected parity data to the corresponding computed parity data, in order to deliver a comparison data representative of a parity success or failure, and • in case of comparison data representative of a parity failure, in incrementing by one ( 1 ) a stored value representative of the number of parity failures before carrying out a new parity comparison relative to the next stream data block.

The method according to the invention may include additional characteristics considered separately or combined, and notably : - one may store in the serial interface a value representative of the total number of data bits contained into the stream data blocks it has received;

> one may read the values stored into the serial interface, and then one may divide the number of parity failures by the total number of data bits to determine a value representative of the bit error rate (BER); o one may determine each value representative of the bit error rate in the serial interface; o alternatively one may use a remote network equipment to read out the values stored into the serial interface to determine each value representative of the bit error rate;

- one may carry out the parity comparison by means of a logic EXOR function;

- one may use a remote network equipment to set and/or reset the value representative of the number of parity failures and/or the value representative of the total number of data bits stored in the serial interface; - the serial interface may incorporate each parity data at the driver end of the associated stream data block.

Other features and advantages of the invention will become apparent on examining the detailed specifications hereafter and the appended drawings, wherein: - figure 1 schematically illustrates an example of embodiment of a serial interface according to the invention, and

- figure 2 illustrates an example of data transmission formats according to the invention, adapted to a serial interface according to the invention, the upper diagram SCL representing a serial clock, the intermediate diagram SDO representing a serial data channel n°0 and the lower diagram SD 1 representing a serial data channel n° 1.

The appended drawing may not only serve to complete the invention, but also to contribute to its definition, if need be.

Reference is initially made to figure 1 to describe an example of a serial interface IFl, IF2 according to the invention. In the following description it will be considered that the serial interface is any high speed serial interface comprising first IFl and second IF2 approximately identical parts interconnected through three wires SCL, SDO, SDl. But it is important to notice that the invention is not limited to this type of serial interface. Indeed the serial interface according to the invention may comprise only one part intended for being connected and eventually integrated into a first data communication equipment (for instance a router) and also for being connected to a second data communication equipment (for instance a transmission line).

The first IFl and second IF2 parts of the serial interface are respectively intended to be connected to first and second data communication equipments (not shown). These first and second data communication equipments may be an application engine and a mobile display, for instance. For instance and as illustrated in the example of data transmission format diagrams of figure 2, this serial interface is dedicated to the transmission of a 24 bit RGB video signal (R0-R7, G0-G7, BO- B7) with raw encoding and including separate horizontal synchronization (HS), vertical synchronization (VS) and data enable (DE) bits.

It is important to notice that the invention is not limited to this application. It also applies to camera, modem graphic station and external apparatus links, for instance.

In this example the first wire SCL is dedicated to the serial clock signal transmission from one part of the serial interface (for instance IFl, when the signal to be transmitted comes from the first equipment) to another part of the serial interface (for instance IF2), while the second SDO and third SDl wires are dedicated to serial data signal transmissions. The serial data signals transmitted through the second SDO and third SDl wires are data blocks of streams. Each block is a word defined by a chosen number of bits depending on the data transmission format (and then the protocol).

The first IFl and second IF2 parts of the serial interface being approximately identical, only one of them (for instance IF2) will be described hereafter. According to the invention one determines a parity data from each data block (or word) to be transmitted. For instance the parity data is a parity bit. Each determined parity data is incorporated into its associated data block (or word) before being transmitted.

In the described example and as illustrated in figure 2, each stream data block is shared in first and second parts which are respectively transmitted through the second SDO and third SDl wires (respectively defining serial data channels n°0 and nl °). In this case, each parity data may be, for instance, incorporated at the driver end DR of the first part (SDO) of each stream data block. It is important to notice that the parity data could be incorporated in other locations into the first or second part of the stream data block.

Still according to the invention and as schematically illustrated in figure 1, the serial interface part IF2 (hereafter named "interface IF2") comprises at least a detection module DM, a control module CM, a first storing means Ml, and a processing module PM.

When the interface IF2 is not only dedicated to data reception but also to data transmission, it further comprises (as illustrated) a transmission module TM arranged to determine each parity data associated to each data block to be transmitted and to incorporate each determined parity data into the associated stream data block before transmitting it.

The detection module DM is arranged to read each stream data block (or word) that is received by its interface IF2 in order to detect its parity data and to deliver it on an output.

In the described example, where the parity data is incorporated in the first part of each stream data block coming from SDO, the detection module DM may be arranged to read only the first parts coming from SDO.

The control module CM is arranged to check the parity of the data that are contained in each stream data block (with the exception of the associated parity data) received by its interface IF2 through SDO and SDl in order to deliver a computed parity data on an output.

The processing module PM is connected to the outputs of the detection module DM and control module CM to be fed with each detected parity data and the corresponding computed parity data.

It is arranged to compare each detected parity data to the corresponding computed parity data in order to deliver a comparison data representative of a parity success or failure.

For instance the parity comparison may be implemented by means of a logic EXOR (exclusive OR) function. It is recall that an EXOR function delivers a bit equal to 1 when each of its two inputs is fed with a bit equal to 1, and delivers a bit equal to 0 in all the other situations ((0,1), (1, 0) and (0, 0)). When the processing module PM implements an EXOR function, it delivers a bit (comparison data) equal to 1 in case of parity success (matching between the received parity data and the corresponding computed parity data) and a bit (comparison data) equal to O in case of parity failure. In practical case the data error chance usually stands between 1.10 ¹² and 1.10^"14.

Therefore two data transmission failures in the same stream data block is not likely to happen.

When the outputted comparison data is equal to 1, it means that the corresponding data block has been correctly transmitted and received. Then interface IF2 may carry out a new parity comparison relative to the next received stream data block. When the outputted comparison data is equal to O, it means that the corresponding data block has not been correctly transmitted and received. In other words a transmission error has occurred. Then the processing module PM orders to the first storing means Ml to increment by one (1) the value representative of the number of parity failures it stores.

For instance the first storing means Ml is a shift register. But it could be any other type of storing means, and notably a simple memory.

In case of realtime video (pixel) stream, while the value stored in the first storing means Ml is being incremented by 1, the interface IF2 is already earring out a new parity comparison relative to the next received stream data block.

In order to determine the bit error rate ratio (BER) of the interface IF2, this latter may comprise a second storing means M2 in which the value representative of the total number of received bits is stored.

For instance the second storing means M2 is a register. But it could be any other type of storing means, and notably a simple memory.

The first Ml and second M2 storing means may be two parts of a same storing means. For instance and as illustrated in figure 1 , the value stored into the second storing means

M2 may be controlled by the control module CM. This is practical because the control module CM has to count the number of received bits during the computation of the parity data corresponding to each received stream data block. So, it can easily add the number of bits contained in each received stream data block (excepted the parity data) to the current value stored into the second storing means M2, each time it computes a parity data.

But another module could be in charge of the control of the second storing means M2.

To determine the bit error rate ratio (BER) one has to divide the number of parity failures by the total number of received bits.

For this purpose at least two solutions may be envisaged. A first solution consists in determining the BER inside the interface IF2. For instance the processing module PM may be arranged to access to the first Ml and second M2 storing means in order to read the stored values, which are representative of the number of parity failures and the total number of data bits. After reading these values the processing module PM divides the value representative of the number of parity failures by the value representative of the total number of data bits, and then delivers a value representative of the bit error rate (BER).

This BER value may be stored in a dedicated memory and/or transmitted to a remote dedicated server or network equipment, connected to the communication network.

A second solution consists in using a remote dedicated server or network equipment, connected to the communication network, to read out the values stored into the first Ml and second M2 storing means. After reading out these values the remote server (or network equipment) divides the value representative of the number of parity failures by the value representative of the total number of data bits, and then delivers a value representative of the bit error rate (BER).

Whatever the envisaged solution, a remote dedicated server or network equipment, connected to the communication network, may be used to set and/or reset the values stored into the first Ml and/or second M2 storing means. Thus, network engineers may have a full remote access to the stored values and a flexibility to use them during the whole life of the interface IF2, and more precisely during its test and design phase, its qualification phase, its release phase, and its repairing phase.

In order the first Ml and second M2 storing means could be read out and/or set and/or reset, the serial interface IF2 may be connected to the remote server (or network equipment) by means of a dedicated interface, for instance of the I²C® type (Inter-Integrated Circuit), or SPI® type, or else μ-Wire® type.

The serial interface IFl, IF2, and more precisely its processing module, PM, control module CM, detecting module DM, transmission module TM, first Ml and second M2 memories may be parts of an integrated circuit realized in NMOS, CMOS or bipolar technology or in any technology used in chip industry fabrication. But, the serial interface IFl , IF2, may be also a combination of hardware and software modules.

The invention may also be considered as a real-time bit error rate testing method for a serial interface IFl, IF2 interconnecting first and second data communication equipments of a communication network. This method may be implemented by means of the above described serial interface IFl ,

IF2. The main and optional functions and sub-functions provided by the steps of this method being appreciably identical to those provided by the different means constituting the serial interface, only the steps implementing the main functions of the method will be summarized hereafter. This method consists: - in incorporating a parity data into each stream data block before transmitting it serially to the serial interface IFl, IF2, and

- each time the serial interface IFl , IF2 receives a stream data block,

• in reading at least partly this stream data block to detect its parity data, • then in checking the parity of the data contained in this received stream data block (excepted its associated parity data) in order to deliver a computed parity data,

• then in comparing the detected parity data to the corresponding computed parity data, in order to deliver a comparison data representative of a parity success or failure, and

• in case of comparison data representative of a parity failure, in incrementing by one (1) a stored value representative of the number of parity failures before carrying out a new parity comparison relative to the next stream data block.

Thanks to the invention real-time BERTs may be carried out without any local or remote dedicated test equipment and/or test installation and without any test profile or pattern. This invention only requires that the serial interface has an available parity option or supports a parity data in its data transmission format.

The invention is not limited to the embodiments of serial interface and real-time bit error rate testing method described above, only as examples, but it encompasses all alternative embodiments which may be considered by one skilled in the art within the scope of the claims hereafter.

Claims

REVENDICATIONS

1. Serial interface (IFl , IF2), intended for being connected to data communication

5 equipments in a communication network and adapted to transmit and/or receive streams of serial data blocks, characterized in that it comprises i) a detection means (DM) arranged to read at least partly each received stream data block to detect a parity data included in each data block, ii) a control means (CM) arranged to check the parity of the data contained in each received stream data block, excepted the associated parity data, in order to deliver a computed parity data, iii) a first 0 storing means (Ml) for storing a value representative of a number of parity failures, and iv) a processing means (PM) arranged to compare each detected parity data to the corresponding computed parity data, in order to deliver a comparison data representative of a parity success or failure, and, in case of comparison data representative of a parity failure, to increment by one the value stored into said first storing means (Ml) and then to carry out a new parity comparison 5 relative to a next stream data block.

2. Serial interface according to claim 1 , characterized in that it further comprises a second storing means (M2) for storing a value representative of a total number of data bits contained into the received stream data blocks.

3. Serial interface according to claim 2, characterized in that said processing means (PM) is o arranged to access to said first (Ml) and second (M2) storing means to read said stored values, and then to divide these values therebetween to deliver a value representative of the bit error rate (BER).

4. Serial interface according to one of claims 1 to 3, characterized in that said processing means (PM) implements a logic EXOR function for said parity comparison.

5 5. Serial interface according to one of claims 1 to 4, characterized in that said first (Ml) and/or second (M2) storing means are arranged to be read out by a remote network equipment.

6. Serial interface according to one of claims 1 to 5, characterized in that said first storing means (Ml) is arranged to have its stored value set and/or reset by a remote network equipment.

7. Serial interface according to one of claims 1 to 6, characterized in that said second 0 storing means (M2) is arranged to have its stored value set and/or reset by a remote network equipment.

8. Serial interface according to one of claims 1 to 7, characterized in that it further comprises a transmission means (TM) arranged to incorporate a parity data into each associated stream data block before transmitting it.

9. Serial interface according to claim 8, characterized in that said transmission means (TM) is arranged to incorporate a parity data at a driver end of the associated stream data block. 5

10. Real-time bit error rate testing method for a serial interface (IF 1 , IF2) interconnecting first and second data communication equipments of a communication network and adapted to transmit and/or receive streams of serial data blocks, characterized in that it consists in incorporating a parity data into each stream data block before transmitting it serially to said serial interface (IFl, IF2), and, each time said serial interface receives a stream data block, i) in reading at 0 least partly said stream data block to detect its parity data, then ii) in checking the parity of the data contained in this received stream data block, excepted its associated parity data, in order to deliver a computed parity data, then iii) in comparing said detected parity data to the corresponding computed parity data, in order to deliver a comparison data representative of a parity success or failure, and iv) in case of comparison data representative of a parity failure, in incrementing by one 5 a stored value representative of a number of parity failures before carrying out a new parity comparison relative to a next stream data block.

11. Method according to claim 10, characterized in that ones stores in said serial interface (IFl, IF2) a value representative of a total number of data bits contained into the stream data blocks it has received. o

12. Method according to claim 11, characterized in that one reads said values stored into said serial interface, and then one divides these values therebetween to determine a value representative of the bit error rate (BER).

13. Method according to claim 12, characterized in that one determines each value representative of the bit error rate into said serial interface (IFl, IF2). 5

14. Method according to claim 12, characterized in that one uses a remote network equipment to read out said value representative of the number of parity failures and said value representative of the total number of data bits stored in said serial interface (IFl, IF2) to determine each value representative of the bit error rate.

15. Method according to one of claims 10 to 14, characterized in that one carries out said 0 parity comparison by means of a logic EXOR function.

16. Method according to one of claims 10 to 15, characterized in that one uses a remote network equipment to set and/or reset said value representative of the number of parity failures and/or said value representative of the total number of data bits stored in said serial interface (IFl, IF2).

17. Method according to one of claims 10 to 16, characterized in that said serial interface (IFl, IF2) incorporates each parity data at a driver end of the associated stream data block to be transmitted.