CN104104559B - A kind of E1 Error Detectors system - Google Patents
A kind of E1 Error Detectors system Download PDFInfo
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- CN104104559B CN104104559B CN201410372920.6A CN201410372920A CN104104559B CN 104104559 B CN104104559 B CN 104104559B CN 201410372920 A CN201410372920 A CN 201410372920A CN 104104559 B CN104104559 B CN 104104559B
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Abstract
Invention describes a kind of E1 Error Detectors system.By realize E1 Error Detector functions module and method integration into E1 equipment, pass through web interface and show test result, and running parameter etc. of Error Detector is set.Wherein, in uplink, E1 signal generations module mainly completes E1 signal generations and is sent to E1 signaling interfaces.On downlink, local sequence synchronization module detects after receiving E1 signals according to the synchronization of frame head progress E1 signals；Sequence compares and synchronous E1 signals and original E1 signals are carried out error code and alarm detection by Bit Error Code Statistics module, and the signal such as the error code of detection and alarm is shown on webpage by the processing of CPU and web.The Error Detector device realized by the method, it is not necessary to using peripheral hardware circuit, reduce the complexity of design, while engineering and batch production can be made to improve work efficiency, reduce cost.
Description
Technical field
The present invention relates to a kind of E1 Error Detectors system, by realize E1 Error Detector functions module and method integration to E1 equipment
In, test result is shown by web interface, and the running parameter of Error Detector is set etc..It is mainly used in the communications field.
Background technology
With developing rapidly for Internet, in next generation network, network number is carried out by elementary cell of data packet
Dominant position will be occupied according to transmission and the mode exchanged.But the existing PDH nets for serving the public voice communication services of PSTN
The E1 circuits that network provides will also long-term existence.
In the performance test of digital communication system, the error performance of E1 is surveyed usually using E1 error analyzers
Amount.Although it has the advantages that easy to use, abundant in content, the error code testing visual result of test, accurate, E1 error codes point
Analyzer is expensive, is not easy to be adapted to some system interfaces, it usually needs separately adds external auxiliary long distance driver circuit.Contained
When the equipment of E1 business is produced in enormous quantities, need to consume great amount of cost, waste of resource, Er Qie if directly Error Detector is used
Engineering is in use, carrying Error Detector also can be inconvenient for a long time.At present largely using FPGA/ASIC as system in communication system
The kernel control chip of system, the function of the various protocol layers in physical layer is concentrated on inside FPGA/ASIC and is realized, is not only improved
The integrated level of communication system, while decrease the design complexities of hardware and software.
The content of the invention
To solve the above-mentioned problems, E1 error code testing functions are integrated in E1 equipment by the present invention, are shown by web interface
Test result, and the running parameter of Error Detector is set etc., without installing software, conveniently check test result, reduce equipment and throw
Cost is provided, improves work efficiency.
The present invention proposes a kind of E1 Error Detectors system.Existing E1 device hardwares resource is fully used, realizes the announcement of E1
Alert type（Main alarm type has frame loss, AIS, pattern step-out, out of frame, error code and frame count）And error detection, carry
Height batch production and the work efficiency of engineering, make engineering opening and investigate more convenient during problem.
Realize that technical scheme is as follows：
A kind of E1 Error Detectors system, including FPGA, CPU, web and display module；Web and display module include being connected to one
The web modules and display module risen；CPU is connected with FPGA, web module bi-directional data respectively；The FPGA gives birth to including E1 signals
Into module, local sequence synchronization module, sequence compares and Bit Error Code Statistics module；E1 signal generations module and local sequence synchronization mould
Block is connected by E1 signaling interfaces, and sequence compares and Bit Error Code Statistics module is connected with local sequence synchronization module, CPU respectively；
Web modules：Control command is sent to CPU, after CPU receives control command, FPGA is sent to by bus, each mould in FPGA
Root tuber performs corresponding action according to the control command received；
E1 signal generation modules：Generate 256bitE1 signals, preceding 8bit as E1 frame heads, behind 248bit produced by m-sequence
It is raw；
Local sequence synchronization module：Carry out frame head synchronously to detect, odd even frame head 3 frames of each continuous detection；To synchronization and step-out
Frame sum counted after sent by bus to CPU, while the E1 signal outputs after synchronization are compared to sequence and
Bit Error Code Statistics module is detected；
Sequence compares and Bit Error Code Statistics module：By the synchronous E1 signals of local sequence synchronization module input and original E1 signals
It is compared, judges the number and alarm type of error code；The frame number of the alarm error code detected and statistics is passed through into bus
Export to CPU；CPU receives error code and alarm data by bus, then error code and alarm are formed to the form of message frame, passes through
It is shared to store data update, carry out real-time query for web and display module；
Display module：The value inquired is shown on webpage, realizes web display functions.
The E1 signal generations module randomly generates E1 signals by 15 grades of scramblers.
The local sequence synchronization module, since E1 frames are parity frame alternate transports, so carrying out preamble detecting
When, to be carried out continuously 6 frames and detect -6 kinds of synchronous regime monitorings, all detect that the synchronous E1 frames for then thinking to receive are until 6 times
Frame synchronization, be otherwise step-out, and the detailed process that frame head synchronously detects is carried out to every frame and is：
Frame head synchronization detection is divided into 6 kinds of states and is detected；When being detected and whetheing there is error code be all to the frame head of E1 into
Row detection, so as to judge as step-out or synchronization；
In A synchronous regimes, synchronization is detected whether, think asynchronous if detection has error code, enter B synchronous protections
State, if detection continues to be detected in A synchronous regimes without error code；
In B synchronous protection states, think synchronous if detection is without error code, into A synchronous regimes, it is same to continue A
Walk state-detection；Detecting that error code then enters C synchronous protection states；
In C synchronous protection states, think synchronous if detection is without error code, continue the detection of A synchronous regimes；If inspection
Measure error code and then jump to D desynchronizing states；
In D desynchronizing states, it is detected and verifies, is then considered step-out if any error code, is judged as out of frame at this time；Such as
Fruit then jumps to E search test status without error code in out of frame state-detection to frame；
Test status are searched in E, if error code is then sent to D desynchronizing states, are determined as out of frame；
Enter F search test status if detection is without error code；
Test status are searched in F, D desynchronizing states is sent to if examining and having error code, is determined as out of frame；
It is frame synchronization if examining without error code, into A synchronous regimes, is determined as frame synchronization.
The detailed process of E1 signal generations module generation E1 signals is：
According to the requirement of standard E1 signals, there are dividing for odd even, even first slot transmission frame synchronization of frame in multi-frame structure
Code, is " 10011011 "；First slot transmission of odd frame is " 11111111 " that this module is produced according to E1 standard signals to accusing code
First time slot of raw parity frame is produced as frame head, 248bit data portions afterwards by m-sequence；
Data are produced using m-sequence, take out the data of even sections；The clock used is the 2.048M's of phaselocked loop generation
Clock, counting is proceeded by when detecting that systematic reset signal is drawn high, and the frame head of even frame is produced at the beginning of counting, it
It is afterwards the even frame part of generation E1 signals, while produces the mark of even frame；The frame head that even frame produces odd frame afterwards is sent completely, is connect
It is odd frame transmission of the data as E1 signals by the use of m-sequence generation, while produces the mark of odd frame；Then odd even mark is passed through
Data are alternately sent to E1 signaling interfaces by will signal in the form of parity frame.
The specific work process of the local sequence synchronization module includes：
E1 signals and clock that E1 signaling interfaces are sent are received, the clock of interface signal is adopted using high power clock
Sample, FIFO is write by E1 signals, and it is enabled that writing for FIFO is produced when E1 interface clock rising edges；The reading of FIFO, which enables, to be passed through
The empty mark of E1 signals number and reading stored in FIFO produces, and data output is carried out serioparallel exchange afterwards；By serioparallel exchange it
Data afterwards carry out odd even frame check to frame head by state machine and produce parity flag at the same time, and the parity flag detected is sent
Compare to sequence and Bit Error Code Statistics module；Received E1 data are docked at the same time carries out frame synchronization and step-out verification；To what is detected
Synchronous frame number is counted the frame number that will be counted on and is sent to bus to CPU；And record current and history out of frame mark hair
Bus is sent to CPU；Synchronous E1 signals are sent to sequence and are compared and Bit Error Code Statistics module.
The sequence compares and the specific work process of Bit Error Code Statistics module includes：
E1 signals on the local sequence synchronization module of reception is synchronized, divide the address in rom tables according to parity flag
Then class reads data；By the data read in rom tables compared with the E1 signals in synchronization, whether have by multilevel iudge
The alarm of error code, AIS, dropout, pattern step-out, current alarm signal is saved in history alarm, counts on history
Alarm；Then various alarms are output to CPU by bus interface module, CPU passes through shared storage and web and display module
Communication, web and display module will be alerted and shown in the form of a web page, check that alarm and error code are that history is gone back by webpage
It is current.
Compared with prior art, the present invention has the following advantages and beneficial to effect：
1st, in terms of test, it is not necessary to build the test platform of complexity, it is only necessary to when starting test, the point from web interface
Hitting Error Detector switch can be tested；
2nd, in terms of production cost, when being produced in batches, it is not necessary to substantial amounts of tradition Error Detector, in every equipment originally
Body just carries Error Detector, so as to cost-effective, can be saved the production time when carrying out error code testing；
3rd, in terms of engineering, it is not necessary to carry bulky Error Detector, it is only necessary to click on and miss from web interface in engineering opening
Code instrument switch can verify that whether engineering opens success；When searching problem for engineering, it is not required that set for this platform again；
4th, in price, it is not necessary to develop hardware again, it is only necessary to by software upgrading on original hardware platform, and
And resource shared by software logic code is few, and cost is greatlyd save from development cost；
5th, in terms of development technique, the display of result is carried out by web and order issues, it is not necessary to complicated operation, directly
Contact, which is hit, to be checked.
Brief description of the drawings
Fig. 1（a）To use the system architecture diagram of routine E1 code error testers；Fig. 1（b）For the system architecture diagram of the present invention.
Fig. 2 is the system architecture block diagram of the present invention.
Fig. 3 is the framework that function of the present invention is realized.
Fig. 4 is 15 grades of scrambler schematic diagrams.
Fig. 5 is synchronous regime preamble detecting flow chart.
Fig. 6 is E1 signal generation block flow diagrams.
Fig. 7 is local sequence synchronization block flow diagram.
Fig. 8 compares for sequence and Bit Error Code Statistics block flow diagram.
Embodiment
The invention will be further described below in conjunction with the accompanying drawings.
Attached drawing 1 is to connect block diagram with the system of this programme using routine E1 code error testers.With PTN microwaves（Band E1 disks）If
It is standby that the simplicity that this programme brings whole system is illustrated.
The system architecture of PTN microwaves is mainly made of IDU and ODU, and modulation /demodulation disk passes through immediate frequency cable in IDU
Line is connected with ODU；ODU and ODU is to launch signal communication by antenna；Then modulation /demodulation in other end ODU and IDU
Disk is connected.
In being tested using conventional E1 code error testers, in addition to needing basic IDU and ODU equipment, also need
To use E1 code error testers and E1 pinboards.Firstly, it is necessary to which E1 disks are connected on E1 pinboards with E1 patchcords, then will
Outputting and inputting on E1 pinboards is connected on E1 code error testers with BNC connecting lines, and the E1 in the IDU sides of opposite end transfers
Loopback is carried out on plate, so just completes building for E1 error code testing systems.
And when being tested using this programme, it is only necessary to which basic IDU and ODU can complete entirely to test, in E1
E1 error code testings can be carried out by opening the switch of E1 error code devices on disk.And in engineering opening if there is problem need into
Row investigation, it is not necessary in addition carry E1 code error testers and BNC connecting lines, it is only necessary to open the E1 error code commissionings carried in E1 disks
Closing opening easily can be tested and be investigated problem.The advantages of can finding this programme from test and engineering use.
Attached drawing 2 is the system architecture of this programme, mainly by FPGA/ASIC, CPU and web（Webpage）Composition.FPGA/
ASIC mainly realizes the function of E1 error code devices, and the error code detected and alarm signal are sent to CPU by bus.CPU exists
After receiving error code and alarm signal, error code and alarm signal are sent to the process of web modules by shared storage, then
Real-time display is on web page.When setting the parameter of Error Detector on web page, web modules obtain web circle by web form
Face information, then passes through bus by the mark of message queue by message queue transmitting order to lower levels to CPU, CPU by command information
It is sent to FPGA/ASIC.So as to form a complete Error Detector device.
Attached drawing 3 illustrates the framework that E1 Error Detectors function is realized.On uplink, E1 signal generations module is mainly given birth to
E1 signaling interfaces are sent into E1 signals, can be by E1 chips to E1 interfaces and then to outside or in E1 herein
Inside the FPGA/ASIC of single-deck in itself, the use of E1 interface modules is directly sent to inside FPGA/ASIC without E1 chips.
On the uplink, local sequence synchronization module, receives the E1 signals that E1 interfaces are sent, and carries out Frame Synchronization Test, will detect
To synchronous frame number and step-out frames statistic CPU is sent to by SPI interface；Sequence compares and Bit Error Code Statistics module, completes to miss
Code statistics and alarm detection, while the error code of generation and warning information are sent to CPU by SPI interface by bus.
Attached drawing 4 is 15 grades of scrambler schematic diagrams, so-called scrambler, right its essence is before digital signal is transmitted to channel
Digital signal carries out randomization in bit-level, so as to reduce shake and intersymbol interference, facilitates the clock of receiving terminal
Extraction.Most common method is to be superimposed a maximum length linear shift register sequence in band transmission signal so that the system of signal
Meter characteristic is suitable for transmitting in corresponding channel.And m-sequence can simply be obtained by what linear feedback shift register
Arrive.The primitive polynomial of 15 grades of scramblers is X15+ X+1, period of state 215- 1, as seen from the figure, the output of register is bk=ak
⊕bk-1⊕bk-15, wherein, K representative element numbers；bkRepresent output result；akRepresent input signal；⊕：Represent exclusive or.Thus come with
Machine produces E1 signals.
Attached drawing 5 is the synchronous regime preamble detecting for receiving E1 signals.Be divided into synchronous regime preamble detecting 6 kinds of states into
Row detection, is all that the frame head of E1 is detected when being detected and whetheing there is error code, so as to judge as step-out or same
Step.It is synchronous regime in state A, detects whether synchronization, thinks asynchronous if detection has error code and arrive B synchronous protection states,
Think that synchronously continuing A synchronously detects if no error code, all detect that the synchronous E1 frames for thinking to receive are until 6 times
Frame synchronization；State B and C are synchronous protection state, are detecting that error code then arrives synchronous protection state, if by same twice
Step guard mode detection has still detected that error code jumps to D desynchronizing states and detects and verify if any error code under desynchronizing state
Then be considered step-out, be judged as out of frame at this time, if in out of frame state-detection to frame without error code if jump to E search examine shape
State, carries out search twice and examines E, and F states, are believed that as frame synchronization if search twice is examined all without error code, if
Error code is then sent to desynchronizing state, is determined as out of frame.
Attached drawing 6 is the flow of E1 signal generation modules.The m-sequence data produced using 15 grades of scramblers, take out odd even portion
The data divided.The clock for the 2.048M that clock as used herein generates for phaselocked loop.When detecting that systematic reset signal is drawn high
Counting is proceeded by, the frame head of even frame is produced at the beginning of counting, afterwards to generate the even frame part of E1 signals, is produced at the same time
The mark of raw idol frame；The frame head that even frame produces odd frame afterwards is sent completely, is used as E1 to believe followed by by the use of the data that m-sequence generates
Number odd frame send, while produce the mark of odd frame.Then data are replaced in the form of parity frame by parity flag signal
It is sent to the interface module of E1 signals.
Attached drawing 7 is local sequence synchronization block flow diagram, E1 signals and clock that E1 interface modules are sent is received, using height
Times clock samples the clock of E1 interface signals, and E1 signals are write FIFO.Produced when E1 interface clock rising edges
Writing for raw FIFO is enabled；The reading of FIFO enables the E1 signals number by being stored in FIFO and reads empty mark to produce, by data
Serioparallel exchange is carried out after output.The data after serioparallel exchange are carried out odd even frame check to frame head by state machine to produce at the same time
Raw parity flag, is sent to sequence by the parity flag detected and compares and Bit Error Code Statistics module；To dock received E1 at the same time
Data carry out frame synchronization and step-out verification.The frame number that will be counted on is counted to the synchronous frame number detected and is sent to bus extremely
CPU；And record current and history out of frame mark and be sent to bus to CPU.Also need to send synchronous E1 signals at this time
Compare to sequence and Bit Error Code Statistics module.
Attached drawing 8 compares and Bit Error Code Statistics block flow diagram for sequence, receive local sequence synchronization module it is synchronized on
Then E1 signals, data are read according to parity flag by the address sort in rom tables.By the data read in rom tables with it is synchronous
On E1 signals be compared, whether there is error code, AIS, dropout, pattern step-out etc. to alert by multilevel iudge, will be current
Alarm signal be saved in history alarm, then can count on the alarm of history.Then various alarms are passed through into bus interface
Module is output to CPU, and CPU is communicated by shared storage with web modules, and alarm etc. is shown to above webpage by web modules, is passed through
Webpage can check alarm and error code is history or current.
Examples detailed above is the preferable embodiment of the present invention, but embodiments of the present invention and from the limit of examples detailed above
System, it is other it is any do not run counter to the present invention Spirit Essences with made under principle change, modification, replacement, combine, simplification should be
Equivalent substitute mode, is included within protection scope of the present invention.
Claims (4)
- A kind of 1. E1 Error Detectors system, it is characterised in that：Including FPGA, CPU, web and display module；Web and display module bag Include web modules and display module；CPU is connected with FPGA, web module bi-directional data respectively；The FPGA includes E1 signal generations Module, local sequence synchronization module, sequence compares and Bit Error Code Statistics module；E1 signal generations module and local sequence synchronization module Connected by E1 signaling interfaces, sequence compares and Bit Error Code Statistics module is connected with local sequence synchronization module, CPU respectively；Web modules：Control command is sent to CPU, after CPU receives control command, FPGA is sent to by bus, in FPGA Each module performs corresponding action according to the control command received；E1 signal generation modules：Generate 256bitE1 signals, preceding 8bit as E1 frame heads, behind 248bit produced by m-sequence；Local sequence synchronization module：Carry out frame head synchronously to detect, odd even frame head 3 frames of each continuous detection；To the frame of synchronization and step-out Sum is sent to CPU after being counted by bus, while the E1 signal outputs after synchronization are compared and error code to sequence Statistical module is detected；Sequence compares and Bit Error Code Statistics module：The synchronous E1 signals of local sequence synchronization module input are carried out with original E1 signals Compare, judge the number and alarm type of error code；The frame number of the alarm error code detected and statistics is exported by bus To CPU；CPU receives error code and alarm data by bus, then error code and alarm are formed to the form of message frame, by shared Store data update, real-time query is carried out for web and display module；Display module：The value inquired is shown on webpage, realizes web display functions；The E1 signal generations module randomly generates E1 signals by 15 grades of scramblers.
- A kind of 2. E1 Error Detectors system according to claim 1, it is characterised in that：The local sequence synchronization module, Since E1 frames are parity frame alternate transports, so when carrying out preamble detecting, to be carried out continuously 6 frames and detect -6 kinds of synchronous shapes State detects, and all detects that the synchronous E1 frames for then thinking to receive are frame synchronization until 6 times, is otherwise step-out, every frame is carried out The detailed process that frame head synchronously detects is：Frame head synchronization detection is divided into 6 kinds of states and is detected；All it is that the frame head of E1 is examined when being detected and whetheing there is error code Survey, so as to judge as step-out or synchronization；In A synchronous regimes, synchronization is detected whether, think asynchronous if detection has error code, enter B synchronous protection shapes State, if detection continues to be detected in A synchronous regimes without error code；In B synchronous protection states, think synchronous if detection is without error code, into A synchronous regimes, continue A synchronization shapes State detects；Detecting that error code then enters C synchronous protection states；In C synchronous protection states, think synchronous if detection is without error code, continue the detection of A synchronous regimes；If detect There is error code then to jump to D desynchronizing states；In D desynchronizing states, it is detected and verifies, is then considered step-out if any error code, is judged as out of frame at this time；If Out of frame state-detection then jumps to E search test status to frame without error code；Test status are searched in E, if error code then jumps to D desynchronizing states, are determined as out of frame；If detection is without error code Test status are searched for into F；Test status are searched in F, D desynchronizing states is jumped to if examining and having error code, is determined as out of frame；It is frame synchronization if examining without error code, into A synchronous regimes, is determined as frame synchronization.
- A kind of 3. E1 Error Detectors system according to claim 1, it is characterised in that：The E1 signal generations module generates E1 The detailed process of signal is：According to the requirement of standard E1 signals, there is point of odd even in multi-frame structure, even first slot transmission frame swynchronization code of frame, is “10011011”；First slot transmission of odd frame is " 11111111 " that this module produces odd even according to E1 standard signals to accusing code First time slot of frame is produced as frame head, 248bit data portions afterwards by m-sequence；Data are produced using m-sequence, take out the data of even sections；The clock used for phaselocked loop generation 2.048M when Clock, counting is proceeded by when detecting that systematic reset signal is drawn high, and the frame head of even frame is produced at the beginning of counting, afterwards To generate the even frame part of E1 signals, while produce the mark of even frame；The frame head that even frame produces odd frame afterwards is sent completely, then It is the odd frame transmission by the use of the data that m-sequence generates as E1 signals, while produces the mark of odd frame；Then parity flag is passed through Data are alternately sent to E1 signaling interfaces by signal in the form of parity frame.
- A kind of 4. E1 Error Detectors system according to claim 1, it is characterised in that：The tool of the local sequence synchronization module Body running process includes：E1 signals and clock that E1 signaling interfaces are sent are received, the clock of interface signal is sampled using high power clock, will E1 signals write FIFO, and it is enabled that writing for FIFO is produced when E1 interface clock rising edges；The reading of FIFO, which enables, passes through FIFO The E1 signals number of middle storage and the empty mark of reading produce, and data output is carried out serioparallel exchange afterwards；After serioparallel exchange Data carry out odd even frame check to frame head by state machine and produce parity flag at the same time, and the parity flag detected is sent to sequence Row compare and Bit Error Code Statistics module；Received E1 data are docked at the same time carries out frame synchronization and step-out verification；Synchronization to detecting Frame number is counted the frame number that will be counted on and is sent to bus to CPU；And record current and history out of frame mark and be sent to Bus is to CPU；Synchronous E1 signals are sent to sequence and are compared and Bit Error Code Statistics module.
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| CN104579821B (en) * | 2014-12-04 | 2018-07-31 | 中国人民解放军91655部队 | The method and apparatus for detecting the frame structure form of the data frame of E1 links |
| CN105591814B (en) * | 2015-12-08 | 2018-10-23 | 河南誉凌电子科技有限公司 | A kind of method and its monitoring system of on-line monitoring E1 channel qualities |
| CN110808772B (en) * | 2019-11-26 | 2022-03-11 | 上海航天测控通信研究所 | Baseband signal processing method and device for receiver of near-moon space communication |
| CN114710423A (en) * | 2022-04-07 | 2022-07-05 | 四川灵通电讯有限公司 | Error code testing method of data chain system |
| CN116455530B (en) * | 2023-06-20 | 2023-11-03 | 中星联华科技（北京）有限公司 | Error code instrument, code pattern generation method and device, electronic equipment and medium |
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