WO2004079573A1

WO2004079573A1 - Multi-processor system

Info

Publication number: WO2004079573A1
Application number: PCT/JP2003/002496
Authority: WO
Inventors: Kunio Yamaguchi
Original assignee: Fujitsu Limited
Priority date: 2003-03-04
Filing date: 2003-03-04
Publication date: 2004-09-16
Also published as: JPWO2004079573A1

Abstract

A multi-processor system includes a plurality of processor cards having a local memory for storing individual information and a backup processor card having a local memory for storing individual information. When one of the processor cards has failed, according to control of a main controller, an access path switching unit of the processor card and the backup processor card switches the access path to a continuation route, so that a route switching controller uses the continuation route to copy the individual information from the local memory of the processor card which has failed to the local memory of the backup processor card.

Description

Description Manore chip processor The technical field

The present invention relates to a multiprocessor system employing a redundant configuration in which various processes in a system operation are distributed and processed by a plurality of processors and a spare processor card is provided for a processor card failure.

Background art

In recent years, the development of systems for transmitting and receiving large data such as voice and images has been rapidly progressing. One example of such a system is a CDMA communication system. This CDMA communication system sends and receives huge amounts of data such as voice and images. In the CDMA communication system, there is a need for a processor system capable of efficiently and rapidly processing the huge amount of data.

Such a system is generally realized by a system composed of a plurality of processors. The prior art is shown below.

Fig. 9 shows the first prior art. FIG. 9 is a configuration diagram of a conventional shared memory type multiprocessor system disclosed in Patent Document 1, for example.

The processor cards 900 to 901, the spare processor card 902, and the shared memory 903 are connected by a global path 908. The main control unit 907 normally monitors the status of each processor card 900 to 901 and the spare processor card 902 by using the status monitoring bus 909.

In the shared memory 903, a shared information area 905, an individual area (# 0 to #n) 904 used individually by each processor card, and a shared memory storing the processor I and D numbers The memory mapping table 906 is allocated.

Of the processor cards shown in FIG. 9, processor card 900 to processor card 901 are currently used processor cards. A plurality of currently used processor cards 900 to 900 update the information stored in the individual area (# 0 to #n) 904 when executing the processing request. This individual area (# 0 to #n) 904 is an area on the shared memory 903, and is an area for storing individual information for taking over the processing when a failure occurs.

The main control unit 907 monitors the status of the processor power. The main control unit 907 switches between the currently used processor card and the spare processor card when detecting a change in the card state.

The main control unit 907 rewrites the ID number of the failed processor in the shared memory matching table 906 with the ID number of the spare processor.

Thereafter, the main controller 907 instructs the spare processor card 902 to access the shared memory matching table 906. With this instruction, the spare processor card 902 accesses the individual area used by the failed processor card immediately before switching. By the above processing, the processing can be taken over.

The second prior art is shown in FIG. FIG. 10 is a configuration diagram of a conventional individual memory type multiprocessor system disclosed in Patent Document 2, for example.

In the system shown in FIG. 10, the processor card 1001 to processor card 106, the spare processor card 107 and the spare processor card 1008, and the shared memory 1 0 9 and the fault monitoring card 1 10 0 are connected by a global bus 1 0 0 0.

Also, the processor card 1001 to processor card 106 and the spare processor card 107 and spare processor card 108 are connected via the command relay card 1011. Connected via IO bus 102.

The processor card 1001 to processor card 106 receive the processing request command from the command relay card 1011, and perform processing.

The spare processor card 1107 and the spare processor card 1108 also receive this processing request command. Spare processor card 1 0 7 The processor card 101008 stores the received processing request command in the local memory 103 so as to take over the received processing request command when the currently used processor card fails. The spare processor card 1007 and the spare processor card 1008 are set in advance as a spare operation mode.

If the currently used processor card fails, one of the spare processor cards reads the processing request command for the failed processor stored in the local memory 103.

Then, the spare processor card starts processing according to the processing request command. As a result, this system takes over the processing to the failed processor.

Patent Document 1

Unexamined Japanese Patent Publication No. 2000-01-166900

Patent Document 2

Unexamined Japanese Patent Publication No.

However, in the case of the conventional technology as described above, the following problems have occurred.

In the system to which the shared memory having the individual area is connected as shown in FIG. 9 described above, if the throughput of the global bus is low, the processing performance of the entire system is greatly reduced.

On the other hand, as a measure to reduce the number of accesses to the global bus, an individual area may be allocated to the local memory in the processor card.

In this case, when the processor card fails, it is necessary to copy the contents of the local memory of the failed processor card to the local memory of the spare processor card in order to take over the individual information.

As a result, there arises a problem that access to other currently used processor cards is affected and performance is reduced.

As a solution to this problem, a configuration as shown in FIG. 2 disclosed.

With this configuration, it is possible to avoid the concentration of access to the shared memory using the one-pass method. Therefore, performance improvement can be realized with this configuration.

However, in this configuration, while the currently used processor card is operating normally, the spare processor card always operates in the spare operation mode. Therefore, in this configuration, a problem that the power consumption of the system becomes high arises.

Here, a processing flow of the technology disclosed in Patent Document 2 is shown below. This process is a typical process. Processing requests from the command relay card 101 1 are received by the processor card 100 1 to the processor card 1 106. Then, the processor cards 1001 to 1006 read the processor individual information on the shared memory 1009. The processor cards 1001 to 1006 perform a series of processing.

Then, the processor card 1001 to processor card 106 write back the result of the series of processing to the individual information of the individual area of each processor in the shared memory 1009 again.

In the example of the above-described processing flow disclosed in Patent Document 2, the handover information to the spare processor power is the processing request command. Therefore, Patent Document 2 discloses that in the worst case, one processing request command is lost due to the processing performance of the currently used processor card and the processing performance of the spare processor card. I have. Disclosure of the invention

One of the objects of the present invention is to provide a multiprocessor system that improves processing performance.

Another object of the present invention is to provide a multiprocessor system capable of suppressing power consumption. Another object of the present invention is to provide a multiprocessor system capable of preventing a command of a processing request from being lost.

A multiprocessor system according to the present invention includes a shared memory, a processor that accesses shared information stored in the shared memory via a common path, and an individual memory that stores individual information taken over when a failure occurs. A plurality of processor models, at least one of which is assigned to the active system and the spare system, respectively.

When a failure occurs in the active processor module, the failure is stored in the individual memory of the spare processor module in place of the failed processor module, and is stored in the individual memory of the failed processor module. Means for generating a data transmission path different from the common bus for storing individual information;

including.

Also, in the multiprocessor system according to the present invention, the means for generating the data transmission path includes: a signal line for taking over the individual information prepared for each processor module; Switching means for connecting a takeover signal line connected to the processor module in which the occurrence of the error occurs and a takeover signal line connected to the standby processor module.

Also, in the multiprocessor system according to the present invention, the means for generating the data transmission path includes: a bus for taking over individual information different from the common bus connecting the processor modules; and a processor module in which the fault has occurred. Means for transmitting and receiving individual information stored in an individual memory of the failed processor module to and from the spare processor module via the takeover bus.

In the multiprocessor system according to the present invention, the standby processor module is activated when a failure occurs in any of the active processor modules. In addition, the multiprocessor system according to the present invention includes a first processor, a first local memory for storing individual information taken over when a failure occurs in the port processor card, and 1 access path to the local memory and one of access paths to the first local memory from the first takeover signal line for copying the individual information in the first local memory A spare port processor card including first access path switching means for switching a path,

A second processor, a second local memory for storing individual information which is taken over when a failure occurs in a processor card, and an access path from the second processor to the second local memory. Second access path switching means for switching an access path from a second takeover signal line for copying the individual information in a second local memory to one of access paths to the second local memory At least two or more processor cards with

A memory for storing the spare processor card and shared information commonly used by the processor cards;

A global bus connecting the spare processor card, the processor card and the memory,

Switching control means for controlling switching of connection between the first takeover signal line and the second takeover signal line;

When a failure occurs in the processor card, the switching control unit includes a main control unit that transmits a processor ID of the failed processor card and an instruction to start copying the individual information.

Further, in the multiprocessor system according to the present invention, the switching control unit receives a processor ID and a memory copy start instruction from the main control unit that has detected a processor card failure, and receives the received processor ID and memory. A receiving buffer selection instruction for selecting a processor card from which the individual information is to be copied based on the copy start instruction; Instruction for selecting a transmission buffer for selecting the individual information, and selecting a takeover signal line for connecting a processor card as a source of the individual information and a processor card as a destination of the individual information. Control instruction analysis means for outputting a route determination instruction and a memory copy instruction for instructing the start of copying of the individual information;

Route selection memory copy control means for selecting the takeover signal line and performing memory copy control based on a route determination instruction and a memory copy instruction received from the control instruction analysis means;

A receiving buffer unit for selecting a buffer based on a receiving buffer selection instruction received from the control instruction analyzing unit and selecting a processor card from which the individual information is copied;

A transmission buffer unit that selects a buffer based on a transmission buffer selection instruction received from the control instruction analysis unit and selects a spare processor card to which the individual information is copied.

Further, in the multiprocessor system according to the present invention, the first access path switching unit includes:

A first access path selecting means for outputting a first access path selection signal for selecting an access path to a local memory based on a failure factor signal indicating a failure factor of a processor card; and An access path from the first processor to the first local memory based on the first access path selection signal, and an access path from the first takeover signal line to the first local memory. A first selector for selecting one of the access paths,

The second access road cutting hairpin means comprises:

Second access path selecting means for outputting a second access path selection signal for selecting an access path to the second local memory based on a failure factor signal indicating a failure factor of the processor power An access path from the second processor to the second local memory based on the second access path selection signal; and the second local memory from the second takeover signal line. Access road to And a second selector for selecting either one.

In addition, the multiprocessor system according to the present invention includes a first processor, a first local memory for storing individual information taken over when a failure occurs in the port processor card, and (1) switching an access path from the access path to the first local memory to the access path to the first local memory from a takeover path for copying the individual information in the first local memory; A spare processor card comprising: access path switching means; and first memory copying control means for controlling copying of the individual information in the first local memory when taking over the individual information.

A second processor, a second local memory for storing individual information taken over when a failure occurs in the processor card, an access path from the second processor to the second local memory, and the second Second access path switching means for switching an access path from a takeover bus for copying the individual information in the local memory to one of access paths to the second local memory; and At least two or more processor cards comprising second memory copy control means for controlling copying of the individual information of the second local memory at the time of takeover;

A memory for storing shared information commonly used by the spare processor card and the processor card;

A takeover path for connecting the spare processor card and the processor card, for copying individual information in the second local memory to the first local memory,

And a main control means for outputting a copy start instruction of individual information to the first memory copy control means and the second memory copy control means when a failure occurs in the processor card. Further, in the multiprocessor system according to the present invention, the first memory copy control unit includes:

The processor ID signal transmission direction is determined based on the spare card identification signal for identifying whether or not the own card is a spare processor card, and the processor ID signal is determined based on the input failure cause signal. First processor ID control means for transmitting or receiving

Based on the copy start instruction received from the main control means, issue an instruction to read the individual information from the second local memory and write an instruction to write the individual information to the first local memory. First memory copy instructing means for outputting a copy completion notice to the main control means when the writing of the individual information to the first local memory is completed;

First memory read control means for controlling reading of the individual information from the second local memory based on a read instruction of the individual information received from the first memory copy instructing means;

A first memory for controlling the harm of the individual information to the first oral memory based on a write instruction of the individual information received from the first memory copy instructing means; ,

A first transfer buffer in which the individual information read by the first memory read control unit is stored;

A first local memory path I / F unit serving as an interface between the first transfer buffer and the first local memory and the takeover bus.- The second memory copy control unit includes:

The transmission direction of the processor ID signal is determined based on the spare card identification signal for identifying whether the card is a spare processor card or not, and the processor ID signal is determined based on the input failure factor signal. A second processor ID control means for transmitting or receiving;

On the basis of the copy start instruction received from the main control means, the second row Second memory copy instructing means for issuing an instruction to read the individual information from a local memory and an instruction to write the individual information to the first local memory;

Second memory read control means for controlling reading of the individual information from the second local memory based on a read instruction of the individual information received from the second memory copy instructing means;

A second memory harm control unit that controls writing of the individual information to the first local memory based on a write instruction of the individual information received from the second memory copy instruction unit;

A second transfer buffer in which the individual information read by the second memory read control means is stored;

A second local memory path IZF means serving as an interface between the second transfer buffer, the second local memory, and the takeover bus.

A first access path selecting means for outputting a first access path selection signal for selecting an access path to a local memory based on a failure factor signal indicating a failure factor of a processor card; and An access path from the first processor to the first local memory, and an access path from the takeover bus to the first local memory, based on the first access path selection signal. A first selector for selecting one of them,

The second access path switching means includes:

A second access path selecting means for outputting a second access path selection signal for selecting an access path to the second memory based on a failure factor signal indicating a failure factor of the processor card; Any one of an access path from the second processor to the second local memory and an access path from the takeover bus to the second local memory based on the second access path selection signal. And a second selector for selecting one.

Further, in the multiprocessor system according to the present invention, the spare processor power is:

In a state where no failure has occurred in the processor card, it is in a standby state where the power is turned on.

As described above, according to the present invention, the means for generating the data transmission path is a common means for storing individual information in the individual memory of the standby processor module when a failure occurs in the active processor module. Since a data transmission path different from the path is generated, it is not necessary to use, for example, the bandwidth of the global bus for the transfer of individual information, and the processing performance of the multiprocessor system can be improved.

Further, in the present invention, since the information transferred from the active processor module to the standby processor module is the individual information, it is possible to prevent the processing request command from being lost.

Further, in the present invention, since the standby processor module is started when one of the active processor modules fails, the power consumption of the standby processor module can be reduced, and The power consumption of the processor system can also be reduced.

The common bus is, for example, a global bus.

The active processor module is, for example, a currently used processor card.

The spare processor module is, for example, a spare processor card.

The individual memory means, for example, a local memory.

In addition, a failure is a concept including, for example, a failure and other defects.

Further, the processor includes, for example, a CPU.

In addition, the access path and the data transmission path are, for example, a case in which one member acts as another member. Signal line for access. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a block diagram of a first embodiment of a multiprocessor system according to the present invention;

FIG. 2 is a block diagram of a route switching control unit used in the first embodiment of the multiprocessor system according to the present invention;

FIG. 3 is a block diagram of an access path switching unit used in the first embodiment of the multiprocessor system according to the present invention;

FIG. 4 is a flowchart of a processor card switching process in the first embodiment of the multiprocessor system according to the present invention;

FIG. 5 is a block diagram of a second embodiment of the multiprocessor system according to the present invention;

FIG. 6 is a conceptual diagram showing assignment of an address space of a takeover bus as viewed from each processor in the second embodiment of the multiprocessor system according to the present invention;

FIG. 7 is a block diagram of a memory copy control unit used in the second embodiment of the multiprocessor system according to the present invention;

FIG. 8 is a flowchart of a switching process of a processor power in the second embodiment of the multiprocessor system according to the present invention;

FIG. 9 is a configuration diagram of a conventional shared memory type multiprocessor system; FIG. 10 is a configuration diagram of a conventional individual memory type multiprocessor system. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, the best mode for carrying out the present invention will be described. The following embodiment is an exemplification, and the present invention is not limited to the configuration of the embodiment.

(First Embodiment of Multiprocessor System) The operation principle of the first embodiment of the multiprocessor system according to the present invention will be described with reference to FIG. FIG. 1 is a block diagram of a first embodiment of a multiprocessor system according to the present invention.

In FIG. 1, 100 to 101 are processor cards (hereinafter, also simply referred to as cards), 102 is a spare processor card, and 103 is a main control unit. The main control unit 103 monitors the status of each processor card via the status monitoring bus 1.4.

105 is a shared memory. Only the shared information area 114 shared by the processor cards is allocated to the shared memory 105.

Reference numeral 106 denotes a local memory included in each of the processor cards 100 to 101 and the spare processor card 102. To the local memory 106, an individual area for storing takeover information at the time of failure of each processor card is allocated.

In the prior art, all areas, including individual areas, were allocated in shared memory. However, in the present embodiment, the individual area is allocated to the local memory 106 of each processor card.

107 is a takeover route. In this specification, the takeover route means a takeover signal line for transmitting a signal. The takeover route 107 is used to transfer individual information stored in the local memory of each processor card when the individual information stored in the individual area is taken over when the processor card fails. used.

Reference numeral 108 denotes a route switching control unit. The route switching control unit 108 controls reading of the individual information of the transfer source, control of writing of the individual information to the destination, and route switching when transferring the individual information stored in the local memory. Control.

Reference numeral 109 denotes a takeover control signal line for transmitting a takeover control signal. This takeover control signal is used to instruct transfer control from the main control unit 103 to the route switching control unit 108.

110 is processor card 100 to 101, spare processor card 102 This is an access path switching unit provided in. The access path switching unit 110 switches the access path to the local memory from the CPU side to the takeover route when a processor power failure occurs.

1 and 2 are CPUs for processing each function of the processor card.

The operation of the first embodiment will be described with reference to FIG. In preparation for takeover in the event of a failure, the processor module 1001 accesses the individual area of the local memory 106 directly from the CPU 112 to update the data in the local memory 106. Do.

The processor card 10001101 accesses the shared information area 114 of the shared memory 105 according to various processes of the system operation.

The main control unit 103 monitors the states of the processor card 10001 and the spare processor card 102 by using the state monitoring bus 104.

It is assumed that one processor card 100 has failed. In this case, the failed processor card 100 notifies the main controller 103 of the failure. In the failed processor card 100, the access path switching unit 110 switches the access path from the roll memory 106 to the takeover route.

As a result, the processor card 100 prepares for switching processing from the currently used processor power 100 to the spare processor card 102.

Next, the main control unit 103 sends to the route switching control unit 108 a copy start instruction of the individual information of the individual area, which is the handover information.

Upon receiving the copy start instruction, the route switching control unit 108 starts reading individual information from the local memory 106 in the failed processor card 100 that is the transfer source.

Then, after completing the reading of the individual information, the route switching control unit 108 writes the read individual information to the local memory 106 in the spare processor card 102 that is the transfer destination.

The route switching control unit 108 writes individual information to the local memory 106 When the copying is completed, the main control unit 103 is notified of the copy completion.

After that, the main controller 103 instructs the spare processor card 102 to start operating. By this operation start instruction, the spare processor card 102 is started. Then, the spare processor card 102 takes over the processing of the failed processor card 100.

Further, when the processor card (for example, the processor card 101) is not used in a certain service, or when a processor card is inserted, the same processing as the above-described takeover processing is performed.

Next, the present embodiment will be described in more detail with reference to FIGS. FIG. 2 is a block diagram of a route switching control unit used in the first embodiment of the multiprocessor system according to the present invention.

FIG. 3 is a block diagram of an access path switching unit used in the first embodiment of the multiprocessor system according to the present invention.

FIG. 4 is a flowchart of a processor card switching process in the first embodiment of the multiprocessor system according to the present invention.

First, the system configuration of the present embodiment will be described with reference to FIG. At least one spare processor card 102 is included in the plurality of processor cards 100-1 to 101-1.

The number of processor cards may be any number of 2 or more.

Then, each processor card is connected to the shared memory 105 and the global bus 113.

The main control unit 103 is connected to the processor cards 100 to 101 and the spare processor card 102 and the shared memory 105 by a status monitoring bus 104.

The shared memory 105 has a common information area 114 which is an area shared by each processor card.

Each processor card 100 to 101 and the spare processor card 1 It has a local memory 106 for storing the handover information at the time of failure.

In addition, each processor card 100 to 101 and the spare processor card 102 have access routes from the CPU 112 and route switching using the takeover route 107 in the event of a card failure. An access path switching unit 110 that switches between access paths from the control unit 108 is provided.

Each of the processor cards 100 to 101 and the spare processor card 102 are connected by a takeover route 107 via a route switching control unit 108. This takeover route 107 is used to take over the processing in the event of a card failure.

The route switching control unit 108 will be described with reference to FIG.

In FIG. 2, reference numeral 200 denotes a reception buffer for determining a copy-source processor card. In the reception buffer unit 2000, a buffer is selected according to a reception buffer selection instruction 205.

Reference numeral 201 denotes a transmission buffer unit for determining a copy destination processor card. In the transmission buffer unit 201, a buffer is selected according to a transmission buffer selection instruction 206.

Reference numeral 202 denotes a route selection memory copy control unit. The route selection memory copy controller 202 selects the route to take over to the spare processor card in accordance with the route determination instruction 207 and the memory copy instruction 208 when a processor card fails. And controls the copying of the individual information stored in the individual area.

Further, when the copying of the individual information is completed, the route selection memory copy control section 202 outputs a memory copy completion notice 204 to the main control section.

Reference numeral 203 denotes a control instruction analysis unit that receives a failed processor ID and a memory copy start instruction from the main control unit.

The control instruction analysis unit 203 outputs a route selection instruction 2007 and a memory copy instruction 208 to the note selection memory copy control unit 202.

Next, an access path switching unit used in the present embodiment will be described with reference to FIG. · In FIG. 3, reference numeral 300 denotes a failure factor signal including a clock disconnection signal, a watchdog timer time-out signal, and the like.

Reference numeral 301 denotes an access path selection unit for recognizing the cause of a card failure and instructing an access path selection.

Reference numeral 302 denotes a selector for switching an access path to the local memory 303 according to an access path selection instruction from the access path selection unit 301.

Next, the operation during operation and when the processor card fails will be described with reference to FIGS.

When a processing request is made, each processor card 10001101 updates data by directly accessing the individual area of each local memory 106 from the CPU 112 in preparation for taking over the processing.

The main control unit 103 uses the status monitoring bus 104 to monitor the card status of each processor card 10001, spare processor power and the shared memory 105 and the shared memory 105. Execute monitoring polling processing for monitoring.

If a certain processor card fails (for example, the processor card 100 has failed and the card failure cause signal 300 shown in FIG. 3 has occurred), this processor card 100 Part 1 0 3 Perform failure notification _&

In the access path switching section 110 of the processor card 100, the access path selection section 301 shown in FIG. 3 outputs an access path selection signal to the selector 302.

The selector 302 switches the access path from the CPU to the takeover route using the received access path selection signal.

The main control unit 103 recognizes the faulty card as the processor card 100 and sends a faulty processor ID and a memory copy start instruction to the route switching control unit 108. The above processing corresponds to the processing of S400S403 in the flowchart shown in FIG.

That is, in FIG. 4, in S400, a failure occurs in the processor card 100. It has occurred.

Then, in step S4 • 1, the failed processor card 100 notifies the main control unit 103 of the failure interrupt and the processor ID.

Then, in S402, the main control unit 103 receives the interrupt notification and starts the switching process.

Then, in S 403, the main control unit 103 sends the route switching control unit 108 to the local memory 106 of the processor card 100 and the spare processor card 102. An instruction to start copying individual information to the local memory 106 is output. Next, the route switching control unit shown in FIG. 2 receives the processor ID of the failed processor card and the copy start instruction. Then, the route switching control unit selects a route from the failed processor card from which the individual information is copied, based on the processor ID. This selection is performed using the reception buffer unit 200. In addition, the route switching control unit selects a route to the spare processor card to which the individual information is to be copied in the transmission buffer unit 201 based on the spare processor ID set in advance.

The route selection memory copy control unit 202 starts reading individual information from the local memory based on the memory copy instruction 208.

At the time of this reading, the card to be read is the processor card selected as the failed processor card in the reception buffer unit 200. The read start address and capacity are fixed to the system.

After the reading of the individual information from the oral memory is completed, the route selection memory copy control unit 202 starts writing the individual information to the local memory.

At this time, the card to which the route selection memory copy control unit 202 writes the individual information is the spare processor card selected as the copy destination. The starting address and capacity of writing are the same as in reading.

The above processing is the processing shown in S404 of FIG. That is, when receiving the copy instruction, the route switching control unit 108 starts the copy processing. On this occasion, The copy start address and capacity are fixed in the system.

After the transfer of the individual information between the local memories is completed by the above operation, the route switching control unit 108 transmits a transfer completion notification to the main control unit 103 [FIG. 4 0 5)].

Then, the main control unit 103 issues an operation start instruction to the spare processor card 102 [FIG. 4 (S406)].

As a result, the spare processor card 102 can take over the contents of the individual information stored in the individual area used by the failed processor card immediately before switching, and can continuously execute the processing request [FIG. (S407)].

As described above, according to the present embodiment, the takeover operation at the time of a card failure uses a different route from the global path, so that access to the shared memory of another processor card is affected. Without taking over, the takeover operation can be performed.

Moreover, the information taken over by the spare processor card is not the processing request command but the individual information of the individual area updated by the processing request. Therefore, even in the worst case, due to the processing performance of the currently used processor card and the processing performance of the spare processor, the control data of the processing request is not lost, and the service can be continued. It becomes possible.

Further, the spare processor card is normally in a standby state, and does not require an operation such as storage in the local memory, so that power consumption of the system can be suppressed.

(Second embodiment of multiprocessor system)

Next, the operation principle of the second embodiment of the multiprocessor system according to the present invention will be described with reference to FIG. FIG. 5 is a block diagram of a second embodiment of the multiprocessor system according to the present invention.

In FIG. 5, the main control unit 503, the status monitoring path 504, the shared memory 505, the password memory 506, and the access path switching unit 510 are the same as those of the first embodiment. It has the same functions as the main control unit 103, the status monitoring bus 104, the shared memory 105, the local memory 106, and the access path switching unit 110, and has the same functions.

507 is a takeover path. The takeover path 507 is used to take over the individual information stored in the individual area when the processor card fails. That is, the takeover bus 507 is used for transferring individual information stored in each processor card.

Reference numeral 508 denotes a memory copy control unit provided in the processor cards 500 to 501 and the spare processor card 502.

The memory copy control unit 508 reads out the individual information of the transfer source and writes the individual information to the transfer destination when the individual information stored in the local memory is transferred.

Reference numeral 509 denotes a takeover control signal line for transmitting a takeover control signal. This takeover control signal is used to instruct transfer control between the main control unit 503 and the memory copy control unit 508. This takeover control signal is used between the main control unit 503 and the memory copy control unit 508 to notify transfer control.

Reference numeral 512 denotes a CPU provided in each of the processor cards 500 to 501 and the spare processor card 502. The CPU 512 processes the functions of the processor cards 500 to 501 and the spare processor card 502.

This embodiment is different from the above-described first embodiment in that 1) the takeover path is a bus-type connection means, and 2) the memory copy control unit provided in the local memory is provided in each processor. 3) The ability to access the memory of one processor card from another processor card.

Next, the operation of the present embodiment will be described with reference to FIGS. FIG. 6 is a conceptual diagram showing the assignment of the address space of the takeover bus as seen from each processor in the second embodiment of the multiprocessor system according to the present invention.

Each processor card 500 to 501 is designed to be ready for handover in case of failure. The individual information is updated by directly accessing the individual area of the memory 506 from the CPU 512.

Also, each processor card 500501 accesses the shared information area 514 of the shared memory 505 according to various processes of the system operation.

The main control unit 503 monitors the states of the processor card 5005001 and the spare processor card 502 via the state monitoring bus 504.

As shown in FIG. 6, the memory copy control unit 508 accesses the individual area of the local memory of another processor by accessing the address shown in FIG. It is possible.

For example, when the spare port processor card 502 accesses the individual area 600 in the processor card 500 shown in FIG. 6, it accesses with an address in the range of address 101 n shown in FIG. .

Next, the operation when the processor card fails will be described. It is assumed that the failed processor card is the processor card 500. The failed processor card 500 notifies the main controller 503 of the failure. Further, the failed processor card 500 sends the processor ID to the takeover bus 507.

In addition, the failed processor card 500 switches the access path to the local memory 506 to the access path from the takeover bus 507 by the access path switching unit 510.

Thus, the failed processor card 500 prepares for switching from the currently used processor card 500 to the spare processor card 502.

Next, the main control unit 503 transmits a copy start instruction of the individual information as the takeover information stored in the memory copy control unit 508 of the spare processor card 502 in the individual area.

Upon receiving the copy start instruction, the memory copy control unit 508 starts reading the individual information stored in the individual area from the local memory 506 of the failed processor card 500 as the transfer source. . After reading the individual information from the local memory 506 of the failed processor card 506, the memory copy control unit 508 stores the local memory 508 of the spare processor card 502 as the transfer destination. Write the read individual information to

Five.

When the writing of the individual information is completed, the memory copy control unit 508 notifies the main control unit 503 of the copy completion.

Thereafter, the main control unit 503 sends an operation start instruction to the spare processor card 502. The spare processor card 502 receiving this operation start instruction takes over the processing.

Further, when the processor card (for example, the processor card 501) is not used in a certain service, or when the processor card is inserted, the same processing as the above-mentioned takeover is performed.

Next, the present embodiment will be described in more detail with reference to FIGS. 4, 7, and 8. FIG.

FIG. 7 is a block diagram of a memory copy control unit used in the second embodiment of the multiprocessor system according to the present invention.

FIG. 8 is a flowchart of a processor card switching process in the second embodiment of the multiprocessor system according to the present invention.

In the first embodiment described above, the route switching control unit is provided as a takeover unit when switching the processor card.

Further, in the first embodiment described above, the copy control of the local memory is further performed by the route switching control unit provided outside the mouth processor card.

However, unlike the first embodiment, the spare processor card may recognize the failed processor card and perform the takeover control. Thus, in the second embodiment, when a processor card fails, the spare processor card takes over the individual information stored in the individual area from the failed processor card.

First, the system configuration of the present embodiment will be described with reference to FIG. Figure 5 In the meantime, the processor cards 500 to 501 and the spare processor card 502 are connected to the shared memory 505 by the global path 513.

Here, the number of processor cards is an arbitrary number of 2 or more.

The main control unit 503 is connected to the processor cards 500 to 501, the spare processor card 502, and the shared memory 505 by a state monitoring path 504.

The shared memory 505 has a shared information area 513 which is an area shared by each processor card.

Processor card 5 0 0-5 0 1及Pi spare processor card 5 0 2, the _c the local memory 5 0 6 comprise a local memory 5 0 6 for storing individual information is faulty sometimes taken over information are, individually Space is allocated. '

The processor cards 500 to 501 and the spare processor card 502 have access paths from the CPU 512 to the local memory 506 and a takeover bus 5 in case of a card failure. An access path switching unit 510 is provided for switching the access path from 07 to the access path to the oral memory 506.

Further, the processor cards 500 to 501 and the spare processor card 502 include a memory copy control unit 508 that controls copying of data in an individual area for takeover.

The processor cards 500 to 501 and the spare processor card 502 are used to connect the takeover bus 507 for interconnecting the processor cards to the memory copy controller 508. A bus I / F 5 16 is provided.

Further, a main control unit 503 for controlling switching of the processor cards is connected to the processor cards 500 to 501 and the spare processor card 502 by a takeover control signal line 509.

Next, the memory copy control unit 508 provided in the processor card of the present embodiment will be described with reference to FIG.

In FIG. 7, 700 is a processor ID control unit. Processor ID control The reserve force identification signal 706 input to the unit 700 is a signal for identifying whether or not the reserve force is a reserve. The signal line of the spare card identification signal 706 is connected to the internal circuit of the card. Also, a value set in advance in the higher order is input to the processor ID control unit 700 as a spare card identification signal 706.

The processor ID signal 707 is transmitted or received to a processor ID control unit in another processor card. The processor ID signal 707 is transmitted or received as processor ID information.

For example, in the case of a processor card in which the self card is currently used, the direction in which the processor ID signal 707 is transmitted is the output direction. If the own card is the currently used processor card, the processor ID control section 700 outputs the processor ID signal 707 when the failure cause signal 708 is input.

The spare card identification signal 706 and the failure cause signal 708 are transmitted from the main control unit 503 to the access path switching unit 510 using, for example, the takeover control signal line 509 shown in FIG. Is done.

On the other hand, when the own card is a spare processor card, the direction in which the processor ID signal 707 is transmitted is the input direction.

The direction in which the processor ID signal 707 is transmitted is determined by the reserve identification signal 706.

The processor ID signal 707 is used for notifying the processor ID at the time of a card failure.

702 is a memory read control unit. The memory read control unit 702 performs read control for copying the individual information stored in the local memory when the individual information stored in the individual area is taken over.

Reference numeral 704 denotes a memory write control unit. The memory write control unit 704 performs write control for copying the individual information stored in the local memory.

703 is a transfer buffer. This transfer buffer 703 is read by the memory read controller 702 when individual information stored in the local memory is copied. The outputted individual information is temporarily stored until the individual information is written to the local memory by the memory write controller 704.

705 is a local memory IZF section. The local memory I / F unit 705 converts a protocol of memory access executed by the read control unit 720 and the write control unit 704 into a protocol of a memory bus. The local memory bus IF section 705 adjusts path timing. Reference numeral 701 denotes a memory copy instructing unit. The memory copy instructing unit 701 issues an operation instruction for copying individual information to the memory read control unit 702 and the memory write control unit 704 in response to a memory copy start instruction from the main control unit. Do.

Further, the memory copy instructing unit 7101 notifies the main control unit of the completion of the memory copy after the completion of the copying of the individual information.

Next, the operation when the processor card fails will be described with reference to FIGS. 3, 5, 7, and 8. FIG.

For example, if the processor card 500 has failed, the failed processor card 500 takes over the processor ID signal 707 indicating the processor ID of its own card using the processor ID control unit 700. It is sent out on the path 507 [FIG. 8 (S800) to (S810)].

Further, the processor card 500 notifies the main controller 503 of the failure by using the takeover bus 507.

Further, the processor card 500 switches the access path of the local memory to the takeover bus 507 by using the access path switching unit (similar to the above-described first embodiment) shown in FIG. .

In the example shown in the first embodiment, the access path switching unit selects one of an access path from the CPU to the local memory and an access path from the takeover route to the local memory. . However, in this embodiment, a takeover bus is used instead of a takeover route.

Therefore, as shown in FIG. 5, the access path switching unit 5 The access path from the CPU 512 to the local memory 506 and the local memory 5 from the takeover bus 507 via the I / F 516 and the memory copy controller 508 One of the access paths to 06 is selected as the access path.

The processor ID signal 707 sent from the processor card 500 is used as a memory copy control unit 508 of the spare processor card 502 set in advance as a spare processor card. Received only at 7 0 0 '.

The spare processor card 502 recognizes that the failed processor card is the processor card 500 by the received processor ID signal 707.

Also, the main control unit 503 that has received the failure notification notifies the spare processor card 502 of a memory copy start instruction [FIG. 8 (S 802)].

Next, the operation of the memory copy control unit of the spare processor card after receiving the fault notification and the processor ID signal will be described with reference to FIG.

The memory copy instructing unit 70 1 instructs reading of the memory read control unit 70 2 individual information.

In response to the input of the processor ID signal, the memory read control unit 702 starts reading the individual information from the local memory of the failed processor card 500.

The read individual information is temporarily stored in the transfer buffer 703.

After that, the memory harm control unit 704 sets the local memory bus I / F unit 704

Transfer buffer to the low-level memory of the spare processor card 502 via 5

Write the individual information stored in 703 in a fixed capacity unit.

The start address at this time is a value fixed by the processor card as shown in Fig. 6.

For example, the failed processor card is processor card 500, and the spare processor card is spare processor card 502. Therefore, the read address range of the local memory is 101 n, and the write address range is 303 n. [Fig. 8 (S8003) (S804)]

The memory copy controller 510 of the processor card 503 from which the individual information is read performs the individual information read processing based on the memory copy start instruction received from the main controller 503.

For example, the memory read control unit of the processor card 500 reads the individual information from the local memory 506 of the processor card 500.

The read individual information is stored in the transfer buffer of the processor card 500.

The individual information stored in the transfer buffer of the processor card 500 is read by the memory harm control unit of the processor card 500.

Then, the individual information read by the memory write control unit of the processor card 500 is transmitted to the memory read control unit 702 of the spare processor card 502 using the takeover bus 507. You.

The memory read controller 702 of the spare processor card 502 that has received the individual information stores the received individual information in the transfer buffer 703.

The memory write controller 704 of the spare processor card 502 stores the individual information stored in the transfer buffer 703 into the local memory 506 of the spare processor card 502. Write to.

After the copying of the individual information of the entire capacity is completed in this way, the memory copy instructing unit 701 sends a copy completion notification to the main control unit [FIG. 8 (805)]. Then, the memory copy instructing unit 7101 waits for an operation start instruction to its own processor card.

Upon receiving the memory copy completion notification, the main control unit 503 gives an instruction to start the operation of the spare processor card 502 [FIG. 8 (S806)].

Then, the spare processor card 502 receiving this operation start instruction takes over the processing based on the individual information stored in the individual area used by the failed processor card 500 immediately before switching [FIG. S 8 0 7)]

As described above, also in the second embodiment, the above-described first embodiment is performed. The same effect as that of the embodiment can be obtained.

As described above, in the multiprocessor systems of the first embodiment and the second embodiment, the processor cards 100 to 101 and the processor cards 500 to 501 are normal and execute the processing request. During this time, the spare processor card 102 and the spare processor card 502 are powered on only and are in a standby state.

The information taken over by the spare processor card in the event of a processor card failure is individual information stored in the local memory which is updated when the processing request is executed. Therefore, in the first embodiment and the second embodiment, it is possible to prevent the processing request command from being lost.

In addition, according to the multiprocessor systems of the first and second embodiments, addition of a minimum hardware such as a takeover route, a takeover bus, and a means for copying local memory between the takeover buses and the processor cards. In this way, loss of inherited information can be prevented without relying on the processing capability of the processor in the event of a failure of the main processor card, service can be continued, and the processing performance of the multiprocessor system can be greatly improved.

Also, according to the multiprocessor systems of the first and second embodiments, the standby processor card is in the normal standby state, and the information to be taken over is stored in the processor individual area updated by the processing request. It is individual information.

Therefore, according to the multiprocessor systems of the first embodiment and the second embodiment, the power consumption of the multiprocessor system is reduced, and the loss of information to be carried over without depending on the processing capability of the processor in the event of a processor card failure. Prevention and continuity of service can greatly improve the processing performance of a multiprocessor system.

Further, according to the actual measurement value of the execution performance of the processing request in the conventional technology and the predicted value when the present invention is applied, it is possible to improve the performance approximately twice as much as the conventional technology.

For example, the multiprocessor systems of the first embodiment and the second embodiment The processing capacity when applied to the processor part of the exchange is indicated by the number of call processes per hour in the exchange equipment.

The measured value of the number of call processings in the prior art is 25.66.77 × 10 ³ [BHCA], whereas the predicted value of the number of call processings in the multiprocessor system to which the present invention is applied is 5 19 . a ^{7 5 X 1 0 3 [B} HCA].

Therefore, according to the multiprocessor systems of the first embodiment and the second embodiment, it is possible to improve the performance of the number of call processes. [BHCA] is an abbreviation for BusyHoourCallAttEmpt, which means the number of calls processed per hour. Industrial applicability

INDUSTRIAL APPLICABILITY The present invention can be applied to, for example, a switch of a CDMA communication system that efficiently and arbitrarily processes a huge amount of data.

Claims

The scope of the claims

1. Shared memory and

It includes a processor that accesses the shared information stored in the shared memory via a common path and an individual memory that stores individual information that is taken over in the event of a failure, and at least one is used for the active system and the standby system. A plurality of processor modules assigned to each,

When a failure occurs in the active processor module, it is stored in the individual memory of the spare processor module in place of the failed processor module in the individual memory of the failed processor module. Means for generating a data transmission path different from the common path for storing the individual information set

Multiprocessor system including.

2. The means for generating the data transmission path is connected to a signal line for taking over the individual information prepared for each of the processor modules, and the processor module that accommodates each of the signal lines for taking over and that has failed. Switching means for connecting a takeover signal line and a takeover signal line connected to the standby processor module.

The multiprocessor system according to claim 1.

3. The means for generating the data transmission path includes a takeover path for individual information different from the common bus connecting the processor modules, and a path between the failed processor module and the standby processor module. Means for transmitting and receiving individual information stored in an individual memory of the failed processor module via the takeover bus.

The multiprocessor system according to claim 1.

4. The standby processor module is activated when a failure occurs in any of the active processor modules.

The multiprocessor system according to claim 1.

5. A first processor, a first local memory for storing individual information taken over when a failure occurs in the processor card, and an access from the first processor to the first local memory. A first switch for switching an access path from the first takeover signal line for copying the individual information in the first local memory to one of access paths to the first local memory. A spare processor card comprising access path switching means;

A second processor, a second oral memory for storing individual information taken over when a failure occurs in the processor card, and an access path from the second processor to the second oral memory And a second switching of an access path from a second takeover signal line for copying the individual information in the second oral memory to one of access paths to the second local memory. At least two or more processor cards having access path switching means;

A global bus for connecting the spare processor card, the processor card and the memory;

A multiprocessor system comprising: a main control unit that transmits, when a failure occurs in the processor card, a processor ID of the failed processor card and an instruction to start copying the individual information to the switching control unit.

6. The switching control means includes:

A processor ID and a memory copy start instruction are received from the main control unit that has detected a failure in the processor power, and a processor card from which the individual information is copied based on the received processor ID and the memory copy start instruction. A transmission buffer selection instruction for selecting a processor card to which the individual information is to be copied, a processor card to be a copy source of the individual information, and a transmission buffer selection instruction for selecting the processor card to which the individual information is to be copied. Control instruction analyzing means for outputting a route determination instruction for selecting a takeover signal line for connecting to a processor card to be copied, and a memory copy instruction for instructing a start of copying of the individual information;

A route selection memory copy control unit for selecting the takeover signal line and performing memory copy control based on a route determination instruction and a memory copy instruction received from the control instruction analysis unit;

A receiving buffer unit for selecting a buffer based on a receiving buffer selection instruction received from the control instruction analyzing unit and selecting a processor source of a copy source of the individual information;

The multiprocessor according to claim 5, further comprising: a transmission buffer unit that selects a buffer based on a transmission buffer selection instruction received from the control instruction analysis unit and selects a spare processor card to which the individual information is copied. system.

7. The first access path switching means,

First access path selection means for outputting a first access path selection signal for selecting an access path to the first local memory based on a failure factor signal indicating a failure factor of the processor card; and An access path from the first processor to the first local memory based on the first access path selection signal; and an access from the first takeover signal line to the first local memory. A first selector for selecting one of the roads,

The second access path switching means includes: Second access path selecting means for outputting a second access path selection signal for selecting an access path to the second local memory based on a failure factor signal indicating a failure factor of the processor card. Based on the second access path selection signal, an access path from the second processor to the second local memory, and an access path from the second takeover signal line to the second local memory. 7. The manorechi processor system according to claim 5, further comprising a second selector for selecting one of the access paths.

8. A first processor, a first local memory for storing individual information taken over when a failure occurs in the processor card, and an access path from the first processor to the first local memory. And a first access path switching means for switching an access path from a takeover path for copying the individual information in the first local memory to an access path to the first local memory. A second processor; and a spare processor card comprising first memory copy control means for controlling the copying of the individual information in the first local memory when the individual information is taken over. A second local memory for storing individual information that is taken over when a failure occurs in a node, and an access from the second processor to the second local memory. A second access for switching an access path from a takeover bus for copying the individual information in the second oral memory to one of access paths to the second oral memory At least two processor cards, comprising: a path switching unit; and a second memory copy control unit that controls copying of the individual information in the second local memory when the individual information is taken over.

A global path connecting the spare processor card, the processor card and the memory; A takeover bus for connecting the spare processor card and the processor card, for copying individual information in the second local memory to the first local memory, and when a failure occurs in the processor card. And a main control means for outputting an instruction to start copying of individual information to the first memory copy control means and the second memory copy control means.

9. The first memory copy control means includes:

The processor ID signal transmission direction is determined based on the spare card identification signal for identifying whether or not the own card is a spare processor card, and the processor ID signal is determined based on the input fault cause signal. First processor ID control means for transmitting or receiving

On the basis of the copy start instruction received from the main control means, an instruction to read the individual information from the second local memory and an instruction to write the individual information to the first local memory are issued. First memory copy instructing means for outputting a copy completion notice to the main control means when information has been written into the first oral memory; and

First memory write control means for controlling writing of the individual information to the first local memory based on a write instruction of the individual information received from the first memory copy instructing means;

A first local memory bus I / F means serving as an interface between the first transfer buffer, the first local memory, and the takeover path. The second memory copy control means includes:

The processor ID signal transmission direction is determined based on the spare card identification signal for identifying whether or not the own card is a spare processor card, and the processor ID signal is determined based on the input fault cause signal. Second processor ID control means for transmitting or receiving

A second memory that issues an instruction to read the individual information from the second local memory and an instruction to write the individual information to the first local memory based on the copy start instruction received from the main control unit. Copy instruction means,

A second memory read control unit that controls reading of the individual information from the second local memory based on a read instruction of the individual information received from the second memory copy instruction unit;

A second memory write control unit that controls writing of the individual information to the first local memory based on a write instruction of the individual information received from the second memory copy instruction unit;

A second transfer buffer in which the individual information read by the second memory read control unit is stored;

9. The multi-purpose memory according to claim 8, further comprising: a second local memory bus I / F means serving as an interface between the second transfer buffer and the second local memory and the takeover bus. Processor system.

10. The first access path switching means,

First access path selecting means for outputting a first access path selection signal for selecting an access path to the first local memory based on a failure cause signal indicating a failure cause of the processor card; and Any one of an access path from the first processor to the first local memory and an access path from the takeover path to the first local memory based on the first access path selection signal. And a first selector for selecting one or the other, The second access path switching means includes:

Second access path selection means for outputting a second access path selection signal for selecting an access path to the second oral memory based on a failure factor signal indicating a failure factor of the processor card; and One of an access path from the second processor to the second local memory and an access path from the takeover path to the second local memory based on the second access path selection signal The multiprocessor system according to claim 8, further comprising a second selector for selecting one of the two.

1 1. The spare processor card

The multiprocessor system according to any one of claims 5 to 10, wherein the processor card is in a standby state in which power is turned on when no failure occurs in the processor card.