JP2000148523A - Duplex memory device and method for switching memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a duplex shared memory system by simple consti-tution without reducing the performance of the system. SOLUTION: A switching circuit 14 is connected to a 1st memory 15 and a 2nd memory 16 in a shared memory part 13, and at the time of detecting a memory fault, switches the operating memory to the stand-by memory, controls respective accesses from plural proces-sors Pi to Pn and ends the switching of memories during the arbi-tration of a system bus 11 by an arbitration circuit 12, so that a processor can always access the operating memory without being conscious of the duplex memory.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a dual memory device and a memory switching method in a multiprocessor system in which a shared memory is duplicated.

[0002]

2. Description of the Related Art A memory system for a communication control device is required to have a large capacity and high reliability in accordance with an increase in data processing amount. As a means for achieving this, a duplicated memory system is often employed. In a duplicated memory system, generally, the same data is stored in duplicated memories in an active system and a standby system, and the same data is guaranteed. The data is read from the operational data. When a failure occurs in the active memory,
Switch from the active system to the standby system.

As a switching control method when a failure occurs, there are a software method and a hardware method. In the switching control by software processing, the processing is always performed sequentially, so that data writing is not performed simultaneously to the duplicated memory. Therefore, if a failure occurs during writing to one memory, the data is not written to the other memory, and the data is not correctly updated. For this reason, data identity cannot be guaranteed.

Particularly in a multiprocessor system, a processor accessing a memory recognizes a memory error and can deal with it. However, other processors do not recognize the memory error and access the memory. Therefore, old data is read and erroneous processing is executed.

In order to solve such a problem, it is conceivable to mark a memory address that is currently being rewritten and restrict access when the processor attempts to read data at this memory address. Although the identity of the duplicated memory can be guaranteed, the control amount increases or the control processing speed decreases.

On the other hand, switching control by hardware has a higher control processing speed than software control. Also, data can be written to the duplicated memory substantially simultaneously.

[0007]

However, even in hardware control, it is necessary to make the processor stand by, though slightly, for switching between the active memory and the standby memory. Since processing is performed at high speed in a multiprocessor system, this slight waiting time leads to processing delay.

Further, it is necessary to make the processor recognize that the memory is being switched. For this reason, the processor is provided with switching recognition means, and necessary control is performed by software after the switching recognition means recognizes. However, in this method, the circuit becomes complicated and the number of control software increases, so that the cost increases and the reliability of the system decreases.

On the other hand, in order to allow the processor to access the memory without recognizing the switching, a systematic synchronizing circuit mechanism, a control signal circuit and the like for inhibiting the memory access on the processor side are provided. . However, this method also complicates the mechanism of the system and significantly increases the cost.

SUMMARY OF THE INVENTION The present invention has been made in view of the above, and in a multiprocessor system, a duplicated memory device and a memory switching method capable of easily and at low cost assuring identical duplicated memories and performing high-speed processing. I will provide a.

[0011]

According to the present invention, when a failure detection unit detects the occurrence of a failure, the storage destination of data handled by the processor is changed from the active memory to the standby memory without arbitrating the right to use the bus. It is to switch spontaneously.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A dual memory device according to a first aspect of the present invention comprises: a shared memory unit for storing data handled by a plurality of processors connected by a bus in an active memory and a standby memory in a redundant manner; A failure detection unit that detects the occurrence of a failure in the active memory; and, when the failure detection unit detects the failure, the storage destination of the data from the active memory without arbitrating the right to use the bus. And a memory switching unit that spontaneously switches to the standby memory.

According to a second aspect of the present invention, in the dual memory device according to the first aspect, the memory switching unit switches from the active memory to the standby memory before performing a retry process. take.

With these configurations, when the failure detection unit detects the occurrence of a failure, the memory switching unit does not arbitrate the right to use any of the buses of the processor and the bus arbitration circuit until the processor performs the retry process. At first, it switches spontaneously from the active memory to the standby memory. As a result, the software on the processor side only needs to be designed to access the ordinary memory. Also,
There is no need to provide a switching recognition circuit that allows the processor to recognize switching. No software control for responding to the signal from the switching recognition circuit is required. Further, there is no need to provide a circuit for restricting memory access on the processor side on the shared memory unit side or the bus arbitration circuit side. As a result, the reliability of the memory can be improved with a simple configuration in terms of software and hardware.

In the second embodiment, the processor does not need to wait for retry processing until arbitration of the right to use the bus ends, so that the processing speed of the entire multiprocessor system can be increased.

In a memory switching method according to a third aspect of the present invention, data handled by a plurality of processors connected by a bus to a shared memory unit is duplicated and stored in an active memory and a standby memory, and the occurrence of a failure is detected. In this case, the storage destination of the data is spontaneously switched from the active memory to the standby memory without arbitrating the right to use the bus.

A fourth aspect of the present invention, in the memory switching method according to the fourth aspect, employs a configuration in which switching from the active memory to the standby memory is performed until retry processing is performed.

According to these configurations, when the occurrence of a failure is detected, the right to use any of the buses of the processor and the bus arbitration circuit is not arbitrated and the spontaneous transfer from the active memory to the standby memory is performed until the retry processing is performed. Switch to
As a result, the software on the processor side only needs to be designed to access the ordinary memory. Also, there is no need to provide a switching recognition circuit for causing the processor to recognize switching. No software control for responding to the signal from the switching recognition circuit is required. Further, there is no need to provide a circuit for restricting memory access on the processor side on the shared memory unit side or the bus arbitration circuit side. As a result, the reliability of the memory can be improved with a simple configuration in terms of software and hardware.

Further, in the fourth embodiment, the processor does not need to wait for the retry process until the arbitration of the right to use the bus ends, so that the processing speed of the entire multiprocessor system can be increased.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is an overall block diagram of a radio communication system using a base station control device (also referred to as a radio control device) having a load sharing type multiprocessor system according to an embodiment of the present invention.

The base station controller 1 is connected between the plurality of base stations 2 and the exchange 3, and serves to provide transmission paths between the mobile stations 4 and between the mobile stations 4 and telephones on the fixed network 5. .

As shown in FIG. 2, the base station controller 1
An I / O unit 6 for connecting to an external line connected to the base station 2 and the exchange 3 and a central processing unit 7 having a multiprocessor configuration for performing data processing are provided.

The data processing performed by the central processing unit 7 includes, specifically, control of connection between the mobile stations 4 and the communication line between the mobile station 4 and the telephone, operation control of the base station 4 (reset, operation stop, state monitoring). / Management, fault detection / recovery control), mobile station 4
Or control data transmission and protocol control with another base station controller, status / fault monitoring / management / control in the base station controller 1, database management of statistical information, etc., input / distribution / Including display.

FIG. 3 is a block diagram of the central processing unit according to the above embodiment.

The central processing unit 7 for controlling communication has a system bus 11. A plurality of processors P1 to Pn are connected to the system bus 11. In addition, an arbitration circuit 13 that arbitrates the right to use the system bus 11 is connected to the system bus 11. Further, a shared memory unit 12 shared by a plurality of processors P1 to Pn is connected to the system bus 11.

FIG. 3 is a block diagram showing the shared memory unit 12 according to the above embodiment. The shared memory unit 12
It has a switching circuit 14 that draws a clock line 21a, an access line 21b, and a data line 21c from the system bus 11, respectively. The switching circuit 14 supplies a clock line 22 to the first memory 15 and the second memory 16.
a, 23a, access lines 22b, 23b, and data lines 22a, 22b. With the above configuration, the plurality of processors P1 to Pn
Can access the shared memory unit 12 via the system bus 11.

The first memory 15 and the second memory 16 constitute an operating system and a standby system. The distinction between the active system and the standby system is made by a bit indicating the distinction between the active and the standby in the control register indicating the card status. By controlling the writing to the control register by the switching circuit 14, the first memory 15 and the second memory 16 are prevented from having the same status at the same time.

The switching circuit 14 maps the active address space to the active memory and the standby address space to the standby memory according to the card status. Switching circuit 14
Copies the data written from the processor to the active memory to the standby system. Further, at the time of reading, the switching circuit 14 reads data from the standby memory and performs an error check at the same time as sending data from the active memory.

A case where a parity error occurs in the active memory while the processor P1 is writing data to the shared memory unit 12 will be described below. In this case, the first memory 15 is used as an active memory and the second memory 16 is used as a standby memory. FIG. 5 is a timing chart showing a retry sequence in the central control unit according to the embodiment. The processing in the central control unit 7 is performed in synchronization with the bus clock signal (BCLK). The processor P1 sends a bus use request signal (BREQ) on the system bus 11. In response,
The arbitration circuit 12 passes the access right to the processor P1 as a bus use right acquisition signal (BGNT). FIG. 5 shows a state where BGNT is asserted before the timing chart is shown.

The processor P1 sends a data transfer start address (A) and a data signal (D). At the same time, the processor P1 asserts a bus busy signal (BB) to indicate that the system bus 11 is busy. Similarly, an address strobe signal (AS) and a data strobe signal (DS) are asserted.

When the processor P1 is writing data to the shared memory unit 12, the switching circuit 14 performs a parity check. Specifically, after writing the data and the parity received from the system bus 11 to the first memory 16, it reads again from the memory device whether or not the data was written correctly. Next, it is checked whether a bit error has occurred using the parity bit.

If the switching circuit 14 detects a parity error in the first memory 16 of the active system, the switching circuit 14
Asserts a data transfer completion signal (DTACK) and a data transfer error signal (BERR) simultaneously, and sends a retry response to the processor P1.

The processor P1 has DTACK and BE
RRs are detected at the same time, and the shared memory unit 12 recognizes that reading has failed and a retry response has been received. At the time of this recognition, the processor P1 issues a bus busy signal (BB)
To release the bus cycle.

On the other hand, the switching circuit 14 monitors BB and waits for the end of the access of the processor P1. After confirming the end of the bus cycle, the switching circuit 14 switches between the active system and the standby system. Specifically, the switching circuit 14 maps the data line 21a to map the standby memory to the active address space and change the card status.
The data line 22a on the first memory 15 side is switched to the data line 23a on the second memory 16 side. This switching is spontaneously performed by the switching circuit 14. That is, the processing is not performed by waiting for a signal based on one of the signals of the processor P1 and the arbitration circuit 12.

The processor P1 sends a bus use right request signal (BREQ) on the system bus 11 as an access request for retry. The arbitration circuit 12 compares all the processors having access requests at the time of detecting the BREQ from the processor P1, and assigns an access right to one of the priority processors to a bus use right acquisition signal (BG
NT). Processor P, unless otherwise requested
The retry cycle with 1 starts immediately. Therefore, before the start of the retry cycle, the system bus 1
A bus cycle of acquiring a use right, transmitting a bus busy signal, and transmitting a memory data address from one access request is required. During this bus cycle, the switching circuit 14 has completed switching between the active system and the standby system, so that normal access to the active system memory is guaranteed.

As described above, according to the above-described embodiment, access to the shared memory unit 13 by the plurality of processors P1 to Pn always occurs only at the address of the active memory. As a result, the processor can access the memory without being aware of the redundancy, and since unnecessary control does not intervene, the reliability of the memory can be easily reduced without deteriorating the performance as compared with the non-redundant memory system. It is possible to improve the performance. That is, special control is not required for the processor side control circuit / software as compared with the related art. Further, by simply connecting a circuit for switching memory mapping to a bus to the shared memory circuit, it is possible to realize redundancy. In addition, since the occurrence of a memory failure is notified to the processor in the form of a bus retry response signal, a simple circuit can be used. Further, since the failure detection and the switching control are performed in the same circuit, the control circuit can be easily configured.

The present invention is not limited to the above embodiment. For example, the failure detection of the memory may be a check method other than the parity. For example, CRC, EC
C, BCC, etc. can be used.

[0039]

As described above, according to the present invention, the reliability of the system can be improved by realizing the duplexing of the shared memory without changing the control on the processor side in the communication control device.

[Brief description of the drawings]

FIG. 1 is an overall block diagram of a wireless communication system using a base station control device including a load sharing multiprocessor system according to an embodiment of the present invention;

FIG. 2 is a block diagram showing a base station controller shown in FIG. 1;

FIG. 3 is a block diagram showing a central control unit shown in FIG. 2;

FIG. 4 is a block diagram showing a shared memory unit of the central control unit shown in FIG. 2;

FIG. 5 is a timing chart showing a retry sequence in a central control unit according to the embodiment.

[Description of Signs] 11 System bus 12 Arbitration circuit unit 13 Shared memory unit 14 Switching circuit 15 First memory 16 Second memory

Claims (4)

[Claims] 1. A shared memory unit that stores data handled by a plurality of processors connected by a bus in a redundant manner in an active memory and a standby memory, a failure detector that detects occurrence of a failure in the active memory, A memory switching unit that spontaneously switches a storage destination of the data from the working memory to the standby memory without arbitrating the right to use the bus when the failure detecting unit detects the occurrence of a failure. Dual memory device. 2. The dual memory device according to claim 1, wherein the memory switching unit switches from the active memory to the standby memory before performing a retry process. 3. The method according to claim 1, wherein data handled by a plurality of processors connected to the shared memory unit via a bus is duplicated and stored in an active memory and a standby memory, and arbitration of the right to use the bus is performed when a failure is detected. Wherein the storage destination of the data is spontaneously switched from the active memory to the standby memory. 4. The memory switching method according to claim 3, wherein switching from the active memory to the standby memory is performed until the retry processing is performed.