JP2000105753A - Two-way data transfer method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a two-way data transfer method by which a data reception side processor successively fetches transfer data from a transmission side processor without necessity to synchronize fetching with that transfer while allowing the execution of data transfer mutually between processors without lowering the throughput because of a collision or bus occupancy on a processor bus. SOLUTION: In the case of transferring data from respective processors 1 and 2 to the opposite processors 2 and 1, after empty banks on a RAM 3 are captured by the respective processors 1 and 2 and data to be transferred to the opposite processors 2 and 1 are temporarily stored, in the case of reporting a data transfer request to the opposite processors 2 and 1 as an interruption, at the opposite processors 2 and 1, after waiting that interruption, the transfer data can be successively extracted from the relevant banks as quickly as possible.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bidirectional data transfer method when data is transferred bidirectionally between two mutually independent processors, and further comprises a processor inside. The present invention relates to a two-way data transfer method in which data is transferred from an active device to a standby device when an active device is in an operation state after a control device is configured as duplex. is there.

[0002]

2. Description of the Related Art Hitherto, data transfer has been performed bidirectionally between processors. In this case, a data transfer method includes a method of accessing a common memory from each of a plurality of processors, a method of accessing a processor, and the like. The reality is that a method of connecting to a counterpart processor via a serial communication port which itself has a function has been considered.

[0003] Japanese Patent Application Laid-Open No. 09-160883, for example, relates to this type of technology. In this case, data is transmitted and received between processors via a communication board. .

[0004]

However, in the case of the conventional data bidirectional transfer method, it is impossible to simultaneously transfer data between the processors to the other party, or the data receiving processor does not. ,
In order to prevent loss of the transfer data, the transfer data must be fetched in synchronization with the data transfer from the transmitting processor, and further, there is a problem such as a collision on the processor bus or a reduction in processing capability due to bus occupation. Things.

On the other hand, in the case of Japanese Patent Application Laid-Open No. 09-160883, processing is performed so that simultaneous access is disabled when each of a transmission driver and a reception driver accesses resources (data buffers and the like) on a communication board. Exclusive control processing by a queue is required.

SUMMARY OF THE INVENTION An object of the present invention is to allow a data receiving processor to simultaneously transfer data to a partner without causing a reduction in processing performance due to collision on the processor bus or bus occupation. Another object of the present invention is to provide a data bidirectional transfer method in which transfer data from a transmitting processor can be fetched at any time as it is unnecessary to fetch the data in synchronization with the transfer.

[0007]

SUMMARY OF THE INVENTION The object of the present invention is to provide a dual port RA interposed as a common resource between processors.
When data is transferred from each processor to the other processor in a state where M is divided into at least two banks, the dual port RA is used by the processor.
After the empty bank on M is captured and the transfer data to the partner processor is temporarily stored on the bank, a data transfer request is notified to the partner processor as an interrupt related to the bank, In the processor,
This is achieved by waiting for the interrupt, fetching the transfer data from the corresponding bank on the dual port RAM as needed, waiting for the end of the transfer data fetching, and restoring the corresponding bank to an empty state. In the case where the control device is configured to be duplicated, the dual port RAM provided in each of the active system device and the standby system device is divided into at least two banks. When data is transferred to the system device, an empty bank on the active dual port RAM is captured,
After the transfer data to the standby device is temporarily stored on the bank, a data transfer request is notified to the standby device as an interrupt related to the bank, while the standby device is
After waiting for the interrupt, transfer data is fetched from the corresponding bank on the active dual port RAM at any time, and after the transfer data is completely fetched, the active dual port R
This is achieved by restoring the corresponding bank on the AM to an empty state.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. First, a description will be given of a case where two mutually independent processors are put into an operating state and data transfer is performed bidirectionally between the processors. FIG. 1 shows a schematic configuration of a system including these processors. It is a thing. As shown, two mutually independent processors (CPU or M
PU) 1 and 2 are both in an operating state, and a dual-port RAM (hereinafter referred to as a common resource) is provided between the processors 1 and 2 so that data can be transferred bidirectionally between the processors 1 and 2. , Simply referred to as a RAM) 3. As a result, in principle, the RAM 3 can be arbitrarily read / written via the CPU bus at any time from the processors 1 and 2 under the condition that simultaneous storage of data at the same address is prohibited. .

The RAM 3 in this embodiment has a continuous address space. The address space is divided into at least two equal parts (two banks), and transfer data from the processors 1 and 2 is stored in the RAM 3. When temporarily storing data in the RAM 3, for example, transfer data from the processor 1 is preferentially temporarily stored in a lower address space, and
While being read by the processor 2 at any time, the transfer data from the processor 2 is also temporarily stored in the upper address space preferentially and read by the processor 1 as needed. As a result, when data transfer is sporadically performed from each of the processors 1 and 2,
Even a two-bank configuration is required and sufficient. However, when data transfer is performed from each of the processors 1 and 2 at a high frequency, it is apparent that such a data transfer mode cannot be dealt with only by the two-bank configuration. Therefore, in general, the RAM 3 has an address space of 4
What is necessary is just to divide equally as equal or more. For example, the RAM 3 is composed of four banks, and the four banks are given priority in the order of storing the transfer data from the processors 1 and 2 (for example, the bank having the highest priority for the processor 1 is the processor 2 Priority is assigned to minimize the priority), and among the banks that are currently empty, the transfer data from the processor 1 is temporarily stored in the bank having the highest priority for the processor 1, while The transfer data from the processor 2 may be temporarily stored in the bank having the highest priority for the processor 2.

Here, the case where the transfer data from the processor 1 is temporarily stored in the RAM 3 and subsequently read out by the processor 2 as needed will be specifically described as follows. That is, assuming that data is transferred from the processor 1 in a state where the bank # 1 has the highest priority for the processor 1 and the bank # 1 is in an empty state, the bank # 1 is captured. After the transfer data to the processor 2 is temporarily stored in the bank # 1, a transfer request flag is set in a portion corresponding to the bank # 1 in the bank control register 1-1. I have. As a result, the processor 2 is notified of the data transfer request to the interrupt controller 2-3 as an interrupt related to the bank # 1. In the processor 2, it is known that transfer data addressed to the own processor exists on the bank # 1 from the interrupt, and the transfer data is taken out of the bank # 1 as soon as possible after waiting for the interrupt. After the transfer data has been fetched, the transfer request flag in the bank # 1 corresponding section on the bank control register section 1-1 is set by the bank # 1 corresponding section on the bank control register clear section 2-2. As a result of the reset, the bank # 1 is restored to an empty state. In processor 1, bank # 1
It is known that the transfer data from the own processor has been taken into the processor 2 from the recovery to the empty state. Also, if the data transfer to the processor 2 continues, if the bank # 1 is already in the recovery state at that time, the bank # 1 only needs to be captured. If bank # 1 is not yet in a recovery state, it is sufficient to confirm that bank # 2 is in an empty state and then to acquire bank # 2. If bank # 2 is not in a recovery state yet, After confirming that the bank # 3 is empty, the bank # 3 may be captured.

On the other hand, for processor 2, bank # 4
Is the highest priority, and furthermore, assuming that data is transferred from the processor 2 in a state where the bank # 4 is in an empty state, the bank # 4 is captured and
After the transfer data to the processor 1 is temporarily stored in the bank # 4, a transfer request flag is set in a portion corresponding to the bank # 4 in the bank control register unit 2-1. As a result, the data transfer request is notified to the interrupt control unit 1-3 as an interrupt related to the bank # 4 to the processor 1. Processor 1
Then, it is known from the interrupt that transfer data addressed to the own processor exists on bank # 4.
After the interruption, the transfer data is taken out from the bank # 4 as needed, and after the transfer data is taken out, the bank # 1 on the bank control register clear unit 1-2 is read.
The bank # 4 is restored to an empty state by resetting the transfer request flag in the bank # 4 corresponding section on the bank control register section 2-1 by the corresponding section. The situation where the data transfer to the processor 1 is continued is the same as the situation where the data transfer to the processor 2 is continued.

When the RAM 3 has a 4-bank configuration, only the banks # 1 and # 2 are used for data transfer from the processor 1 to the processor 2, and the banks 3 are used for data transfer from the processor 2 to the processor 1. # 4
If only # 3 is used, no problem is considered to occur. However, banks # 3 and # 4 are used for data transfer from processor 1 to processor 2, and banks # 3 and # 4 are used for data transfer from processor 2 to processor 1.
This is a problem when 2 and up to # 1 are used. That is, for example, from the time when the empty bank # 3 is captured by the processor 1 to the time when the data transfer request is notified to the processor 2 as an interrupt related to the bank # 3, the bank 2 is captured by the processor 2. That is, there is a risk of being performed. Such a contention in capturing an empty bank can be avoided by notifying the other party of the status of capturing the empty bank in each of the processors 1 and 2 and referring to the situation when capturing the empty bank. .

As is clear from the above description, the transfer data from each of the processors 1 and 2 can be simultaneously stored in the RAM 3, and the data transfer from one processor causes the other processor to transfer the data. Is not immediately restricted. Incidentally, since each of the banks # 1 to # 4 is common to the processors 1 and 2, when data transfer is performed unilaterally and continuously from one of the processors, the banks # 1 to # 4 are not used. It is possible that all of # 1 through # 4 may be captured for those data transfers.

FIG. 2 also shows that the control device including the processor therein is configured to be redundant, and that the active device is switched from the active device to the standby device when the active device is in operation. Describing when data is transferred,
FIG. 2 shows a schematic system configuration including these processors. As shown in the drawing, the substantial difference from the one shown in FIG. 1 is that each of the processors 1 and 2 is provided with an active RAM 1-4 and a spare RAM 2-4, and furthermore, has an active RAM 1-4. , The spare RAM2-4 is C
It is mentioned that both of the processors 1 and 2 can be accessed via the PU bus, and other than that, the situation is almost the same as that shown in FIG. However, regarding the data transfer direction, unilaterally from the active system to the active RAM
, Data is transferred to the standby system. This is because, when any failure occurs in the active system, the standby system is immediately started up as a new active system while maintaining continuity in control processing. This is because it is necessary to always make the data identical. For example, when the processor 1 is placed in the operating state as the active control device, the internal data in the active control device is unilaterally transferred to the standby control device as the processor 2 via the RAM 1-4. When the processor 2 is newly put into operation as an active controller due to the occurrence of some failure in the processor 1, the internal data in the active controller is stored in the RAM2-4.
Is unilaterally transferred to the standby system control device as the processor 1 via the.

[0015]

As described above, according to the first and second aspects of the present invention, the data transfer between the processors to the other party can be performed simultaneously without causing a collision on the processor bus or a decrease in the processing capacity due to the bus occupation. Is allowed, the transfer data from the transmitting processor can be fetched at any time in the data receiving processor as it is unnecessary to fetch the data in synchronization with the transfer.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a schematic configuration of a system including two independent processors in a case where data transfer is performed bidirectionally between the processors;

FIG. 2 is a diagram illustrating a configuration in which a control device including a processor therein is configured as a duplex device, and when an active system device is in an operation state, the active system device is switched to a standby system device; Diagram showing a system outline configuration including these processors when data is transferred

[Explanation of symbols]

1, 2, processor, 1-1, 2-1, bank control register section, 1-2, 2-2 bank control register clear section, 1-3, 2-3 ... interrupt control section, 3, 1-4 , 2-4 ... Dual port RAM

Claims (2)

[Claims] 1. A data bidirectional transfer method in which data is transferred bidirectionally between two mutually independent processors, wherein a dual port RAM interposed as a common resource between the processors is provided. When data is mutually transferred from the processors to the partner processor in a state where the banks are divided into at least two or more banks, an empty bank on the dual port RAM is captured by the processor, and then the partner processor is placed on the bank. After the transfer data is temporarily stored, the other processor is notified of the data transfer request as an interrupt related to the bank, while the other processor waits for the interrupt and transfers data from the corresponding bank on the dual port RAM. After the data is taken out at any time and the transfer data is taken out, the corresponding bank is vacated. A data bidirectional transfer method that restores the state. 2. A control device having a processor therein is configured to be redundant, and data is transferred from the active device to the standby device when the active device is in operation. In this method, a dual port RAM provided in each of an active device and a standby device is divided into at least two banks. When data transfer is performed, an empty bank in the active dual port RAM is captured, and data to be transferred to the standby device is temporarily stored in the bank. While the request is notified as an interrupt related to the bank, the standby device waits for the interrupt and fetches transfer data from the corresponding bank on the active dual port RAM as needed. And a data bidirectional transfer method in which the corresponding bank on the active dual port RAM is restored to an empty state after the completion of the transfer data extraction.