WO2002047146A2 - DAMASCENE NiSi METAL GATE HIGH-K TRANSISTOR - Google Patents

DAMASCENE NiSi METAL GATE HIGH-K TRANSISTOR Download PDF

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Publication number
WO2002047146A2
WO2002047146A2 PCT/US2001/046551 US0146551W WO0247146A2 WO 2002047146 A2 WO2002047146 A2 WO 2002047146A2 US 0146551 W US0146551 W US 0146551W WO 0247146 A2 WO0247146 A2 WO 0247146A2
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Prior art keywords
metal
low temperature
gate
recess
semiconductor structure
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PCT/US2001/046551
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French (fr)
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WO2002047146A3 (en
Inventor
Qi Xiang
Paul R. Besser
Matthew S. Buynosky
John Clayton Foster
Paul L. King
Eric N. Paton
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Advanced Micro Devices, Inc.
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Priority claimed from US09/731,031 external-priority patent/US6475874B2/en
Priority claimed from US09/734,189 external-priority patent/US6342414B1/en
Application filed by Advanced Micro Devices, Inc. filed Critical Advanced Micro Devices, Inc.
Priority to AU2002228811A priority Critical patent/AU2002228811A1/en
Publication of WO2002047146A2 publication Critical patent/WO2002047146A2/en
Publication of WO2002047146A3 publication Critical patent/WO2002047146A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Definitions

  • the present invention relates to semiconductor manufacturing technology, more particularly to a method for fabricating field effect transistors by a low temperature suicide process.
  • MOS Metal Oxide Semiconductor
  • the principal elements of a typical MOS transistor generally comprise a semiconductor substrate on which a gate electrode is disposed.
  • the gate electrode is typically a heavily doped conductor to which an input signal is typically applied via a gate terminal.
  • Heavily doped active regions e.g., source/drain regions, are formed in the semiconductor substrate and are connected to source/drain terminals.
  • a channel region is formed in the semiconductor substrate beneath the gate electrode and separates the source/drain regions.
  • the gate electrode is generally separated from the semiconductor substrate by a dielectric layer, e.g., an oxide layer, to prevent current from flowing between the gate electrode and the source/drain regions or channel regions.
  • a dielectric layer e.g., an oxide layer
  • Conventional process steps for fabricating a typical MOS transistor are depicted in Figs. 1 to 8.
  • an oxide layer is thermally grown on a semiconductor substrate 10, i.e., typically silicon, and a conductive layer, typically polysilicon, is formed over the oxide layer.
  • the oxide layer and conductive layer are patterned and etched to form gate dielectric 12 and gate electrode 14, respectively.
  • Fig. a conductive layer
  • impurity atoms e.g., boron or phosphorus
  • the gate electrode 14 as a mask
  • the ion implantation step is followed by an annealing step which normally involves a high temperature of 700°C or higher to activate the implanted impurity atoms in the shallow source/drain regions 16 and to cure the damage caused by the physical impact to the crystal structure of the silicon substrate 10 when the impurity atoms are implanted thereto.
  • Sidewall spacers 18 are then formed on the side surfaces of the gate dielectric 12 and gate electrode 14, as depicted in Fig. 3.
  • source/drain regions 20 are formed by ion implanting impurity atoms, e.g., boron or phosphorus, at the impurity implantation concentration and energy higher than those from the first annealing process, by utilizing the gate electrode 14 and the sidewall spacers 18 as a mask, as depicted in Fig. 4.
  • the annealing process is performed at a high temperature of 700°C or higher to activate the implanted impurity atoms in the source/drain regions 20 and to cure the damage caused by the implantation impact.
  • a metal layer 22 is typically provided by first applying a thin layer of, for example, titanium, atop the wafer which contacts the source/drain regions 20. Then, the wafer is subjected to one or more annealing steps at the temperature of 800°C or higher. This causes the titanium layer 22 to selectively react with the silicon of the source/drain regions 20 and the gate electrodes 14, thereby forming a metal suicide (TiSi 2 ) layer 24 selectively on the source/drain regions 20 and the gate electrodes 14.
  • a metal suicide self-aligned suicide
  • an interlayer dielectric film 26 is deposited over the entire surface of the substrate 10, and an interconnect process is performed (not shown) to provide conductive paths by forming via holes through the interlayer dielectric 26 and filling the via holes with a conductive material, e.g., tungsten.
  • the thickness of the gate oxide is also scaled down accordingly.
  • excessively reduced thickness of the gate oxide causes charge carrier leakage by tunneling effect, thereby leading to faster degradation of the MOS transistor.
  • a high k (dielectric constant) gate dielectric e.g., Zr0 2 , Hf0 2 , In0 2 , La0 2 , Ta0 2
  • Zr0 2 , Hf0 2 , In0 2 , La0 2 , Ta0 2 was introduced to replace the silicon oxide for submicron MOS devices.
  • the high k gate dielectric becomes thermally unstable during the high temperature process steps for fabrication of the MOS transistor.
  • the source/drain region activation annealing steps in Figs. 2 and 4 and the silicidation step in Fig. 6 are normally performed at a temperature of at least 700°C or higher, or in some cases at a temperature of 1000 °C or higher.
  • tantalum oxide (Ta 2 Os), another high k gate dielectric, is transformed from amorphous to crystalline, which causes charge carrier leakage.
  • tantalum oxide undesirably interacts with the underlying silicon substrate or overlying polysilicon gate electrode of the MOS transistor.
  • a metal gate electrode has been introduced to avoid the reaction between the high k gate dielectric and the polysilicon gate electrode during the high temperature processing steps.
  • a metal deposition process was proposed to form a metal gate layer by depositing molybdenum, tungsten, tungsten suicide, nickel silicide, or titanium nitride.
  • the present invention provides a method for forming a self-aligned low temperature metal silicide gate on a high k gate dielectric layer within semiconductor structures.
  • the method includes forming a precursor having a substrate with active regions separated by a channel, and a temporary gate over the channel and between dielectric structures.
  • the temporary gate is removed to form a recess having a bottom and sidewalk between the dielectric structures, and a high dielectric constant (high K) gate dielectric layer is deposited in the recess on the bottom and sidewalk.
  • a low temperature silicidation metal is deposited over the semiconductor structure including the recess, and the low temperature silicidation metal is removed from the semiconductor structure except for a portion in the recess.
  • Silicon is deposited over the semiconductor structure, and annealing is performed to cause the silicon and the portion of the low temperature silicidation metal in the recess to interact to form a self-aligned low temperature metal silicide gate.
  • the semiconductor structure is then planarized to remove the amorphous silicon.
  • the low temperature silicide metal deposited over the semiconductor structure is removed except for a portion in the recess, which enables the portion in the recess to selectively interact with the overlying silicon, thereby forming the self-ahgned low temperature silicide gate selectively within the recess. Since the silicidation between the silicon and the low temperature silicidation metal occurs selectively in the recess, and other portions of the silicon remain unchanged, the remaining portions of the low temperature silicidation metal can be easily removed, by planarization, for example. Also, since the metal silicide gate is formed at the low temperature, e.g., approximately 700°C, the high k gate dielectric is prevented from interacting with the underlying semiconductor substrate and the overlying gate.
  • silicon is deposited first in the recess, followed by the low temperature silicidation metal.
  • Silicide is then formed in the gate by annealing and unreacted silicidation metal is removed.
  • Fig. 1 is a schematic depiction of a cross-section of a prior art semiconductor structure, in which a gate electrode is formed on a semiconductor substrate with a gate oxide therebetween.
  • Fig. 2 depicts the portion of Fig. 1, during the first ion implantation process to form shallow source and drain regions on the main surface of the substrate.
  • Fig. 3 depicts the portion of Fig. 2, after the first annealing process and a sidewall spacer formation process.
  • Fig. 4 depicts the portion of Fig. 3, during the second ion implantation process to form source and drain regions on the main surface of the substrate.
  • Fig. 5 depicts the portion of Fig. 4, after the second annealing process and a metal layer deposition process.
  • Fig. 6 depicts the portion of Fig. 5, after a silicidation process to form a metal silicide layer on the source and drain regions and the gate electrode.
  • Fig. 7 depicts the portion of Fig. 6, after an interlayer dielectric layer is formed over the semiconductor structure.
  • Fig. 8 is a schematic depiction of a cross-section of a semiconductor structure precursor in accordance with embodiments of the present invention.
  • Fig. 9 depicts the portion of Fig. 8, after the temporary gate electrode has been removed to form a recess.
  • Fig. 10 depicts the portion of Fig. 9, after a high k dielectric layer has been deposited on the surfaces of the recess and over the interlayer dielectric layer.
  • Fig. 11 depicts the portion of Fig. 10, after a low temperature silicidation metal has been deposited over the high K dielectric layer.
  • Fig. 12 depicts the portion of Fig. 11, after the low temperature silicidation metal has been removed except for the portion in the recess
  • Fig. 13 depicts the portion of Fig. 12, after silicon has been deposited over the entire semiconductor structure.
  • Fig. 14 depicts the portion of Fig. 13, after annealing to form a self-aligned low temperature silicide gate over the channel.
  • Fig. 15 depicts the portion of Fig. 13, after the semiconductor structure is planarized to remove the low temperature silicidation metal.
  • Fig. 16 depicts the portion of Fig. 10, after amorphous silicon has been deposited over the high K dielectric layer in accordance with another embodiment of the invention.
  • Fig. 17 depicts the portion of Fig. 16, after the amorphous silicon has been removed except for the portion in the recess.
  • Fig. 18 depicts the portion of Fig. 17, after a low temperature silicidation metal has been deposited over the entire semiconductor structure.
  • Fig. 19 depicts the portion of Fig. 18, after annealing to form a self-aligned low temperature silicide gate over the channel.
  • Fig. 20 depicts the portion of Fig. 19, after the low temperature silicidation metal remaining after silicidation has been removed.
  • the method and apparatus described below do not form a complete process flow for manufacturing integrated circuits.
  • the present invention can be practiced in conjunction with integrated circuit fabrication techniques currently used in the art, and only so much of the commonly practiced process steps are included as are necessary for an understanding of the present invention.
  • the figures representing cross-section portions of a semiconductor chip or a substrate during fabrication are not drawn to scale, but instead are drawn to illustrate the feature of the present invention.
  • the present invention provides a method for implementing a self-ahgned low temperature metal silicide gate on a high k gate dielectric without the problems accompanied in conventional methods.
  • the metal sihcide gate is formed at the low temperature, e.g., approximately 700°C, the high k gate dielectric is prevented from interacting with the underlying semiconductor substrate and the overlying gate.
  • the silicon is deposited within the recess and the silicidation metal is deposited over the silicon, followed by annealing to form silicide.
  • Fig. 8 is a cross-section of a precursor for the semiconductor structure constructed in accordance with embodiments of the present invention.
  • a silicon substrate 10 has active regions 20 formed therein by conventional ion implantation and subsequent annealing techniques.
  • a silicide layer 24 is formed atop the active regions 20 to reduce the resistance between the active regions 20 and conductive interconnect lines which will be formed subsequently.
  • annealing and silicidation steps which involve high temperatures, e.g., approximately 700°C or higher, are completed before the temporary gate 14 is removed from the region between the sidewall spacers 18, as depicted in Fig. 9.
  • a plasma reactive ion etch (RIE) using chlorine or a wet polysilicon etch using conventional etch chemistry may be utilized to remove the polysilicon gate 14 to form an opening (i.e., recess) 28.
  • a high k dielectric is provided as layer 30 having a thickness between about 50A and about 200A, for example.
  • Conventional methods of deposition such as chemical vapor deposition, may be used to deposit the high k gate dielectric layer 30.
  • Typical materials that may be used in the high k gate dielectric layer 30 include Zr0 2 , Hf0 2 , In0 2 , La0 2 , Ta0 2 , for example.
  • Other multiple metal oxides may be used or perovskites may be employed as tire high k gate dielectric material in layer 26.
  • a reason for using high k materials as a gate dielectric is that conventional silicon dioxide is no longer extendable. Also, a high k gate dielectric provides better electrical coupling with the gate and the channel. -Also, with high k materials, a thicker film can be used while still obtaining the same electrical field.
  • One of the concerns with high k materials is its low temperature stability. In other words, at high temperatures, high k material reacts with the silicon substrate. Processing at lower temperatures, such as with nickel silicide, mitigate this concern.
  • Fig. 11 depicts the semiconductor structure of Fig. 3, after deposition of a low temperature silicidation metal (e.g., nickel) 32.
  • the low temperature silicidation metal 32 is provided within the recess 28 on top of the high k gate dielectric layer 30.
  • the deposition may be performed by low temperature chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD).
  • CVD low temperature chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • the semiconductor structure of Fig. 11 is planarized, by chemical mechanical planarization (CMP), for example, to remove the low temperature silicidation metal 32 and the high k gate dielectric 30 except for the portion within the recess 28.
  • CMP chemical mechanical planarization
  • silicon (e.g., amorphous silicon or polysilicon) 34 is deposited entirely over the semiconductor structure by conventional deposition techniques.
  • the deposition may be performed by low temperature chemical vapor deposition (CVD) at a temperature sufficient to prevent the high k gate dielectric 30 from becoming unstable, for example, at a temperature between about 500°C and about 600°C.
  • CVD chemical vapor deposition
  • annealing is performed to convert the low temperature silicidation metal 32 confined in the recess 28 to self-aligned sihcide 36.
  • the self-aligned sihcide metal gate (e.g., nickel silicide) 36 is selectively formed over the high k gate dielectric 30. Other portions of the silicon 34, which were not in contact with the low temperature silicidation metal 32, remain unchanged.
  • rapid thermal annealing is performed to form the self-ahgned silicide metal gate (e.g., nickel sihcide) 36, at a temperature between about 500°C and about 600°C for a period of between about 30 seconds and about 60 seconds.
  • the remaining unreacted portion of the silicon 34 is removed by conventional planarization techniques, e.g., chemical mechanical polishing (CMP) by utilizing the material difference between the metal silicide gate (e.g., nickel silicide gate) 36 and the silicon layer 34. Since the sihcide metal gate 36 is selectively formed over the high k gate dielectric 30, not entirely deposited over the entire upper surface of the semiconductor structure including the recess, tire planarization step can performed with less complexity, by chemical mechanical polishing, until no silicon is detected, thereby automatically shaping the silicide metal gate 36.
  • CMP chemical mechanical polishing
  • this embodiment of the present invention enables implementation of a self-aligned low temperature metal sihcide gate over a high k dielectric film, by manipulating the material difference between a metal sihcide gate and silicon overlying the metal silicide gate.
  • the lower temperature silicidation occurs at the necessary areas, thereby avoiding silicidation of the entire upper surface of the semiconductor structure. This enables easier formation of the low temperature metal silicide gate, simply by planarizing the unreacted silicon, until no silicon is detected.
  • the metal sihcide gate is formed at the low temperature, e.g., approximately 700°C, the high k gate dielectric is prevented from interacting with the underlying semiconductor substrate and the overlying gate.
  • Fig. 16 depicts the semiconductor structure of Fig. 3, after deposition of an amorphous silicon layer 132.
  • the amorphous silicon layer 132 is provided within the recess 28 on top of the high k gate dielectric layer 30.
  • the deposition may be performed by low temperature chemical vapor deposition (CVD) at a temperature sufficient to prevent the high k gate dielectric 30 from becoming unstable, for example, at a temperature between about 500°C and about 600°C.
  • CVD low temperature chemical vapor deposition
  • the semiconductor structure of Fig. 16 is planarized, by chemical mechanical planarization (CMP), for example, to remove the amorphous silicon 132 and the high k gate dielectric 130 except for the portion within the recess 28.
  • CMP chemical mechanical planarization
  • a self-aligned silicidation is achieved.
  • a low temperature silicidation metal e.g., nickel
  • Fig. 18 a low temperature silicidation metal (e.g., nickel) 134 is deposited entirely over the semiconductor structure by conventional deposition techniques. Subsequently, in Fig.
  • annealing is performed to convert the amorphous silicon 132 confined in the recess 28 to self-ahgned silicide 136. Since the metal layer 134 is in limited contact with the amorphous silicon 132 over the recess 28, the self-ahgned silicide metal gate (e.g., nickel silicide) 136 is selectively formed over the high k gate dielectric 30. Other portions of the low temperature silicidation metal 134, which are not in contact with the amorphous silicon 132, remain unchanged.
  • the metal gate e.g., nickel silicide
  • the self-aligned silicide metal gate e.g., nickel silicide
  • the self-aligned silicide metal gate e.g., nickel silicide
  • the remaining unreacted portion of the low temperature silicidation metal 134 is removed by conventional etch techniques by utilizing the selectivity between the metal sihcide gate (e.g., nickel sihcide) 136 and the metal layer (e.g., nickel) 134.
  • the silicide metal gate 136 is selectively formed over the high k gate dielectric 30, the remaining silicidation metal 134 can be easily removed by using an etchant having high selectivity between the sihcide 136 and the metal 134, for example, sulfuric acid, nitric acid or hydrogen peroxide.
  • the semiconductor structure now has a complete replacement gate electrode comprising the high k gate dielectric 30 and the metal silicide gate 136.
  • this embodiment of the present invention enables implementation of a self-aligned low temperature metal sihcide gate by manipulating the etch selectivity between a metal silicide gate and a metal overlying the metal sihcide gate. Also, since the metal silicide gate is formed at the low temperature, e.g., approximately 700°C, the high k gate dielectric is prevented from interacting with the underlying semiconductor substrate and the overlying gate.

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Abstract

A method for implementing a self-aligned low silicide gate (36) is archived by confining a low temperature silicidation metal (32) within a recess (28) overlying a channel and annealing to cause the low temperature silicidation metal (32) and its overlying silicon (34) to interact to form the self-aligned low temperature metal silicide gate (36). A planarization step is performed to remove the remaining unreacted silicon (34) by chemical mechanical polishing until no silicon (34) is detected. In order embodiments, the silicon (132) is deposited in the recess (28), followed by deposition of the silicidation metal (132) and annealing to form the metal silicide gate (136).

Description

DAMASCENE NiSi METAL GATE HIGH-K TRANSISTOR
TECHNICAL FIELD
The present invention relates to semiconductor manufacturing technology, more particularly to a method for fabricating field effect transistors by a low temperature suicide process.
BACKGROUND ART
Over the last few decades, the electronics industry has undergone a revolution by various efforts to decrease the size of device elements formed in integrated circuits (IC), and such efforts have contributed in increasing the density of circuit elements and device performance. A large variety of semiconductor devices have been manufactured having various applications in numerous disciplines.
Currently, the most common and important semiconductor technology presently used is silicon-based, and the most preferred silicon-based semiconductor device is a MOS (Metal Oxide Semiconductor) transistor. The principal elements of a typical MOS transistor generally comprise a semiconductor substrate on which a gate electrode is disposed. The gate electrode is typically a heavily doped conductor to which an input signal is typically applied via a gate terminal. Heavily doped active regions, e.g., source/drain regions, are formed in the semiconductor substrate and are connected to source/drain terminals. A channel region is formed in the semiconductor substrate beneath the gate electrode and separates the source/drain regions. The gate electrode is generally separated from the semiconductor substrate by a dielectric layer, e.g., an oxide layer, to prevent current from flowing between the gate electrode and the source/drain regions or channel regions. Conventional process steps for fabricating a typical MOS transistor are depicted in Figs. 1 to 8. First, as depicted in Fig. 1, an oxide layer is thermally grown on a semiconductor substrate 10, i.e., typically silicon, and a conductive layer, typically polysilicon, is formed over the oxide layer. The oxide layer and conductive layer are patterned and etched to form gate dielectric 12 and gate electrode 14, respectively. Then, as depicted in Fig. 2, impurity atoms, e.g., boron or phosphorus, are ion implanted into the surface of the silicon substrate 10, by utilizing the gate electrode 14 as a mask, to form shallow source/drain regions 16 on the main surface of the silicon substrate 10.
The ion implantation step is followed by an annealing step which normally involves a high temperature of 700°C or higher to activate the implanted impurity atoms in the shallow source/drain regions 16 and to cure the damage caused by the physical impact to the crystal structure of the silicon substrate 10 when the impurity atoms are implanted thereto. Sidewall spacers 18 are then formed on the side surfaces of the gate dielectric 12 and gate electrode 14, as depicted in Fig. 3.
Subsequently, source/drain regions 20 are formed by ion implanting impurity atoms, e.g., boron or phosphorus, at the impurity implantation concentration and energy higher than those from the first annealing process, by utilizing the gate electrode 14 and the sidewall spacers 18 as a mask, as depicted in Fig. 4. Once again, the annealing process is performed at a high temperature of 700°C or higher to activate the implanted impurity atoms in the source/drain regions 20 and to cure the damage caused by the implantation impact.
As transistor dimensions approached one micron in diameter, conventional parameters resulted in intolerably increased resistance between the active region 20 and conductive interconnect lines formed subsequently to interconnect various device elements in the integrated circuit device. The principle way of reducing such contact resistance is by forming a metal suicide atop the source/drain regions 20 and the gate electrodes 14 prior to application of the conductive film for formation of the various conductive interconnect lines. The most common metal suicide materials are CoSi2 and TiSi2.
As depicted in Fig. 5, a metal layer 22 is typically provided by first applying a thin layer of, for example, titanium, atop the wafer which contacts the source/drain regions 20. Then, the wafer is subjected to one or more annealing steps at the temperature of 800°C or higher. This causes the titanium layer 22 to selectively react with the silicon of the source/drain regions 20 and the gate electrodes 14, thereby forming a metal suicide (TiSi2) layer 24 selectively on the source/drain regions 20 and the gate electrodes 14. Such a process is referred to as a salicide (self-aligned suicide) process because the TiSi2 layer 24 is formed only where the titanium material directly contacts the silicon source/drain regions 20 and the polycrystalline silicon gate electrode 14. Following the formation of the suicide layer 24, as depicted in Fig. 7, an interlayer dielectric film 26 is deposited over the entire surface of the substrate 10, and an interconnect process is performed (not shown) to provide conductive paths by forming via holes through the interlayer dielectric 26 and filling the via holes with a conductive material, e.g., tungsten.
As the dimensions of the MOS transistor are further scaled down to submicron and nanometer dimensions, the thickness of the gate oxide is also scaled down accordingly. However, such excessively reduced thickness of the gate oxide causes charge carrier leakage by tunneling effect, thereby leading to faster degradation of the MOS transistor.
To solve this problem, a high k (dielectric constant) gate dielectric, e.g., Zr02, Hf02, In02, La02, Ta02, was introduced to replace the silicon oxide for submicron MOS devices. However, it has been also observed that the high k gate dielectric becomes thermally unstable during the high temperature process steps for fabrication of the MOS transistor. For example, as mentioned above, the source/drain region activation annealing steps in Figs. 2 and 4 and the silicidation step in Fig. 6 are normally performed at a temperature of at least 700°C or higher, or in some cases at a temperature of 1000 °C or higher. At such a high temperature, tantalum oxide (Ta2Os), another high k gate dielectric, is transformed from amorphous to crystalline, which causes charge carrier leakage. In addition, at such a high temperature, tantalum oxide undesirably interacts with the underlying silicon substrate or overlying polysilicon gate electrode of the MOS transistor.
To solve this problem, a metal gate electrode has been introduced to avoid the reaction between the high k gate dielectric and the polysilicon gate electrode during the high temperature processing steps. For example, as described in the U. S. Patent No. 5,960,270 by Misra, et al. a metal deposition process was proposed to form a metal gate layer by depositing molybdenum, tungsten, tungsten suicide, nickel silicide, or titanium nitride.
However, it has been also observed that the metal atoms from the gate electrode diffuse into the gate dielectric, thereby causing faster degradation of the high k gate dielectric, and both the high k gate dielectric and the metal gate electrode suffer structural stress from such high temperature process steps. Also, since the metal or metal silicide layer is deposited entirely over tire semiconductor structure, it has been observed that it is difficult to controllably remove the unnecessary portions of the deposited metal or metal silicide layer to shape a metal or metal silicide gate due to the material unity.
Thus, there is a continuing need for improved methods that enable implementation of a reliable gate structure in submicron MOS transistors without the undesirable side effects and complicated process steps. DISCLOSURE OF THE INVENTION
These and other needs are met by the present invention that provides a method for forming a self-aligned low temperature metal silicide gate on a high k gate dielectric layer within semiconductor structures. The method includes forming a precursor having a substrate with active regions separated by a channel, and a temporary gate over the channel and between dielectric structures. The temporary gate is removed to form a recess having a bottom and sidewalk between the dielectric structures, and a high dielectric constant (high K) gate dielectric layer is deposited in the recess on the bottom and sidewalk. A low temperature silicidation metal is deposited over the semiconductor structure including the recess, and the low temperature silicidation metal is removed from the semiconductor structure except for a portion in the recess. Silicon is deposited over the semiconductor structure, and annealing is performed to cause the silicon and the portion of the low temperature silicidation metal in the recess to interact to form a self-aligned low temperature metal silicide gate. The semiconductor structure is then planarized to remove the amorphous silicon.
Hence, in accordance with an aspect of the present invention, the low temperature silicide metal deposited over the semiconductor structure is removed except for a portion in the recess, which enables the portion in the recess to selectively interact with the overlying silicon, thereby forming the self-ahgned low temperature silicide gate selectively within the recess. Since the silicidation between the silicon and the low temperature silicidation metal occurs selectively in the recess, and other portions of the silicon remain unchanged, the remaining portions of the low temperature silicidation metal can be easily removed, by planarization, for example. Also, since the metal silicide gate is formed at the low temperature, e.g., approximately 700°C, the high k gate dielectric is prevented from interacting with the underlying semiconductor substrate and the overlying gate.
In other embodiments of the invention, silicon is deposited first in the recess, followed by the low temperature silicidation metal. Silicide is then formed in the gate by annealing and unreacted silicidation metal is removed.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements in which:
Fig. 1 is a schematic depiction of a cross-section of a prior art semiconductor structure, in which a gate electrode is formed on a semiconductor substrate with a gate oxide therebetween. Fig. 2 depicts the portion of Fig. 1, during the first ion implantation process to form shallow source and drain regions on the main surface of the substrate.
Fig. 3 depicts the portion of Fig. 2, after the first annealing process and a sidewall spacer formation process.
Fig. 4 depicts the portion of Fig. 3, during the second ion implantation process to form source and drain regions on the main surface of the substrate. Fig. 5 depicts the portion of Fig. 4, after the second annealing process and a metal layer deposition process.
Fig. 6 depicts the portion of Fig. 5, after a silicidation process to form a metal silicide layer on the source and drain regions and the gate electrode. Fig. 7 depicts the portion of Fig. 6, after an interlayer dielectric layer is formed over the semiconductor structure.
Fig. 8 is a schematic depiction of a cross-section of a semiconductor structure precursor in accordance with embodiments of the present invention.
Fig. 9 depicts the portion of Fig. 8, after the temporary gate electrode has been removed to form a recess.
Fig. 10 depicts the portion of Fig. 9, after a high k dielectric layer has been deposited on the surfaces of the recess and over the interlayer dielectric layer.
Fig. 11 depicts the portion of Fig. 10, after a low temperature silicidation metal has been deposited over the high K dielectric layer. Fig. 12 depicts the portion of Fig. 11, after the low temperature silicidation metal has been removed except for the portion in the recess
Fig. 13 depicts the portion of Fig. 12, after silicon has been deposited over the entire semiconductor structure.
Fig. 14 depicts the portion of Fig. 13, after annealing to form a self-aligned low temperature silicide gate over the channel.
Fig. 15 depicts the portion of Fig. 13, after the semiconductor structure is planarized to remove the low temperature silicidation metal.
Fig. 16 depicts the portion of Fig. 10, after amorphous silicon has been deposited over the high K dielectric layer in accordance with another embodiment of the invention. Fig. 17 depicts the portion of Fig. 16, after the amorphous silicon has been removed except for the portion in the recess.
Fig. 18 depicts the portion of Fig. 17, after a low temperature silicidation metal has been deposited over the entire semiconductor structure.
Fig. 19 depicts the portion of Fig. 18, after annealing to form a self-aligned low temperature silicide gate over the channel.
Fig. 20 depicts the portion of Fig. 19, after the low temperature silicidation metal remaining after silicidation has been removed.
MODES FOR CARRYING OUT THE INVENTION
The method and apparatus described below do not form a complete process flow for manufacturing integrated circuits. The present invention can be practiced in conjunction with integrated circuit fabrication techniques currently used in the art, and only so much of the commonly practiced process steps are included as are necessary for an understanding of the present invention. The figures representing cross-section portions of a semiconductor chip or a substrate during fabrication are not drawn to scale, but instead are drawn to illustrate the feature of the present invention. The present invention provides a method for implementing a self-ahgned low temperature metal silicide gate on a high k gate dielectric without the problems accompanied in conventional methods. This is achieved by using dummy gate techniques to confine a low temperature silicidation metal within a recess formed over a channel and annealing to cause the low temperature silicidation metal and its overlying silicon to react to form the self- aligned low temperature metal silicide gate. Since the removal of the low temperature s-licidation metal except for the portion in the recess is performed prior to the low temperature silicidation, the remaining unreacted portions of the silicon can be easily removed, for example, by planarization, e.g., chemical mechanical polishing. Also, since the metal sihcide gate is formed at the low temperature, e.g., approximately 700°C, the high k gate dielectric is prevented from interacting with the underlying semiconductor substrate and the overlying gate. In other embodiments, the silicon is deposited within the recess and the silicidation metal is deposited over the silicon, followed by annealing to form silicide.
With this in mind, Fig. 8 is a cross-section of a precursor for the semiconductor structure constructed in accordance with embodiments of the present invention. In Fig. 8, a silicon substrate 10 has active regions 20 formed therein by conventional ion implantation and subsequent annealing techniques. A silicide layer 24 is formed atop the active regions 20 to reduce the resistance between the active regions 20 and conductive interconnect lines which will be formed subsequently.
A polysilicon gate 14, which serves as a temporary gate, is provided on top of the channel. Sidewall spacers 18 are provided on the side walk of the gate 14, and interlayer dielectric 26 is provided to cover the active regions 20 and the silicide layer 24. Although it is not shown, a silicon oxide gate dielectric could be formed between the substrate 10 and the gate 14.
As previously mentioned, the annealing and silicidation steps which involve high temperatures, e.g., approximately 700°C or higher, are completed before the temporary gate 14 is removed from the region between the sidewall spacers 18, as depicted in Fig. 9. A plasma reactive ion etch (RIE) using chlorine or a wet polysilicon etch using conventional etch chemistry may be utilized to remove the polysilicon gate 14 to form an opening (i.e., recess) 28.
In Fig. 10, a high k dielectric is provided as layer 30 having a thickness between about 50A and about 200A, for example. Conventional methods of deposition, such as chemical vapor deposition, may be used to deposit the high k gate dielectric layer 30. Typical materials that may be used in the high k gate dielectric layer 30 include Zr02, Hf02, In02, La02, Ta02, for example. Other multiple metal oxides may be used or perovskites may be employed as tire high k gate dielectric material in layer 26.
As previously mentioned, a reason for using high k materials as a gate dielectric is that conventional silicon dioxide is no longer extendable. Also, a high k gate dielectric provides better electrical coupling with the gate and the channel. -Also, with high k materials, a thicker film can be used while still obtaining the same electrical field. One of the concerns with high k materials, however, is its low temperature stability. In other words, at high temperatures, high k material reacts with the silicon substrate. Processing at lower temperatures, such as with nickel silicide, mitigate this concern.
Fig. 11 depicts the semiconductor structure of Fig. 3, after deposition of a low temperature silicidation metal (e.g., nickel) 32. The low temperature silicidation metal 32 is provided within the recess 28 on top of the high k gate dielectric layer 30. The deposition may be performed by low temperature chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD). Following the deposition of the low temperature silicidation metal 32, as depicted in Fig. 12, the semiconductor structure of Fig. 11 is planarized, by chemical mechanical planarization (CMP), for example, to remove the low temperature silicidation metal 32 and the high k gate dielectric 30 except for the portion within the recess 28. As will be described hereafter, by confining the low temperature silicidation metal 32 within the recess 28, a self-aligned silicidation is achieved.
In Fig. 13, silicon (e.g., amorphous silicon or polysilicon) 34 is deposited entirely over the semiconductor structure by conventional deposition techniques. The deposition may be performed by low temperature chemical vapor deposition (CVD) at a temperature sufficient to prevent the high k gate dielectric 30 from becoming unstable, for example, at a temperature between about 500°C and about 600°C. Subsequently, in Fig. 14, annealing is performed to convert the low temperature silicidation metal 32 confined in the recess 28 to self-aligned sihcide 36. Since the silicon 34 is in limited contact with the low temperature silicidation metal 32 over the recess 28, the self-aligned sihcide metal gate (e.g., nickel silicide) 36 is selectively formed over the high k gate dielectric 30. Other portions of the silicon 34, which were not in contact with the low temperature silicidation metal 32, remain unchanged. To maintain the high k gate dielectric 30 stable, rapid thermal annealing is performed to form the self-ahgned silicide metal gate (e.g., nickel sihcide) 36, at a temperature between about 500°C and about 600°C for a period of between about 30 seconds and about 60 seconds.
In Fig. 15, the remaining unreacted portion of the silicon 34 is removed by conventional planarization techniques, e.g., chemical mechanical polishing (CMP) by utilizing the material difference between the metal silicide gate (e.g., nickel silicide gate) 36 and the silicon layer 34. Since the sihcide metal gate 36 is selectively formed over the high k gate dielectric 30, not entirely deposited over the entire upper surface of the semiconductor structure including the recess, tire planarization step can performed with less complexity, by chemical mechanical polishing, until no silicon is detected, thereby automatically shaping the silicide metal gate 36.
Thus, this embodiment of the present invention enables implementation of a self-aligned low temperature metal sihcide gate over a high k dielectric film, by manipulating the material difference between a metal sihcide gate and silicon overlying the metal silicide gate. In accordance with the present invention, the lower temperature silicidation occurs at the necessary areas, thereby avoiding silicidation of the entire upper surface of the semiconductor structure. This enables easier formation of the low temperature metal silicide gate, simply by planarizing the unreacted silicon, until no silicon is detected. Also, since the metal sihcide gate is formed at the low temperature, e.g., approximately 700°C, the high k gate dielectric is prevented from interacting with the underlying semiconductor substrate and the overlying gate.
Fig. 16 depicts the semiconductor structure of Fig. 3, after deposition of an amorphous silicon layer 132.
The amorphous silicon layer 132 is provided within the recess 28 on top of the high k gate dielectric layer 30. The deposition may be performed by low temperature chemical vapor deposition (CVD) at a temperature sufficient to prevent the high k gate dielectric 30 from becoming unstable, for example, at a temperature between about 500°C and about 600°C.
Following the deposition of the amorphous sihcon 132, as depicted in Fig. 17, the semiconductor structure of Fig. 16 is planarized, by chemical mechanical planarization (CMP), for example, to remove the amorphous silicon 132 and the high k gate dielectric 130 except for the portion within the recess 28. As will be described hereafter, by confining the amorphous sihcon 132 within the recess 28, a self-aligned silicidation is achieved. In Fig. 18, a low temperature silicidation metal (e.g., nickel) 134 is deposited entirely over the semiconductor structure by conventional deposition techniques. Subsequently, in Fig. 19, annealing is performed to convert the amorphous silicon 132 confined in the recess 28 to self-ahgned silicide 136. Since the metal layer 134 is in limited contact with the amorphous silicon 132 over the recess 28, the self-ahgned silicide metal gate (e.g., nickel silicide) 136 is selectively formed over the high k gate dielectric 30. Other portions of the low temperature silicidation metal 134, which are not in contact with the amorphous silicon 132, remain unchanged. To maintain the high k gate dielectric 30 stable, rapid thermal anneahng is performed to form the self-aligned silicide metal gate (e.g., nickel silicide) 136, at a temperature between about 500°C and about 600°C for a period of between about 30 seconds and about 60 seconds. In Fig. 20, the remaining unreacted portion of the low temperature silicidation metal 134 is removed by conventional etch techniques by utilizing the selectivity between the metal sihcide gate (e.g., nickel sihcide) 136 and the metal layer (e.g., nickel) 134. Since the silicide metal gate 136 is selectively formed over the high k gate dielectric 30, the remaining silicidation metal 134 can be easily removed by using an etchant having high selectivity between the sihcide 136 and the metal 134, for example, sulfuric acid, nitric acid or hydrogen peroxide. The semiconductor structure now has a complete replacement gate electrode comprising the high k gate dielectric 30 and the metal silicide gate 136.
Thus, this embodiment of the present invention enables implementation of a self-aligned low temperature metal sihcide gate by manipulating the etch selectivity between a metal silicide gate and a metal overlying the metal sihcide gate. Also, since the metal silicide gate is formed at the low temperature, e.g., approximately 700°C, the high k gate dielectric is prevented from interacting with the underlying semiconductor substrate and the overlying gate.
Although the present invention has been described and illustrated in detail, it is to be clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the scope of the present invention being limited only by the terms of the appended claims.

Claims

CLAIMSWhat Is Claimed Is:
1. A method of forming a semiconductor structure comprising the steps of: forming a precursor having a substrate (10) with active regions (20) separated by a channel, and a temporary gate (14) over the channel and between dielectric structures (26); removing the temporary gate (14) to form a recess (28) with a bottom and sidewalk between the dielectric structures (26); depositing a high dielectric constant (high K) gate dielectric layer (30) in the recess (28) on the bottom and sidewalk; depositing a low temperature silicidation metal (32) over the semiconductor structure including the recess
(28); removing the low temperature silicidation metal (32) except for a portion in the recess (28); depositing sihcon (34) over the semiconductor structure; annealing to cause the silicon (34) and the portion of the low temperature sihcidation metal (32) in the recess (28) to interact to form a self-aligned low temperature metal sihcide gate (36); and planarizing the semiconductor structure to remove the sihcon (34).
2. The method of claim 1, wherein a thickness of the high K gate dielectric layer (30) is between approximately 50A and approximately 200A.
3. The method of claim 2, wherein the low temperature silicidation metal (32) is nickel.
4. The method of claim 1, wherein the low temperature sihcidation metal (32) is removed by a chemical mechanical polishing (CMP).
5. The method of claim 1, wherein further processing of the semiconductor structure is maintained below a temperature sufficient to prevent a substantial interaction between the high k gate dielectric layer (30) and the substrate (10).
6. A method of forming a semiconductor structure comprising the steps of: forming a precursor having a substrate (10) with active regions (20) separated by a channel, and a temporary gate (14) over the channel and between dielectric structures (26); removing the temporary gate (14) to form a recess (28) with a bottom and sidewalk between the dielectric structures (26); depositing a high dielectric constant (high K) gate dielectric layer (30) in the recess (28) on tire bottom and sidewalk; depositing amorphous silicon (132) over the semiconductor including the recess (28); removing the amorphous silicon (132) except for a portion in the recess (28); depositing a low temperature sihcidation metal (134) over the semiconductor structure; anneahng to cause the low temperature sihcidation metal (134) and the portion of the amorphous silicon
(132) in the recess (28) to interact to form a self-aligned low temperature metal silicide gate electrode (136); and removing the low temperature sihcidation metal (134) remaining unreacted after the anneahng.
7. The method of claim 6, wherein the lower temperature sihcidation metal (134) is nickel.
8. The method of claim 6, wherein further processing of the semiconductor structure is maintained below a temperature sufficient to prevent a substantial interaction between the high k gate dielectric layer (30) and the substrate (10).
9. The method of claim 6, wherein the remaining low temperature sihcidation metal (134) is removed by an etchant having a high selectivity between the low temperature silicidation metal (134) and the low temperature metal silicide gate (136).
10. The method of claim 9, wherein the etchant is sulfuric acid, nitric acid or hydrogen peroxide.
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