517290 A7 B7 五、發明說明（ 經濟部智慧財產局員工消費合作社印製 [技術領域] 本發明係有關半導體製作技術’詳言之，係藉由低溫 矽化程序而製作場效電晶體之方法。 [技藝背景] 近數十年來，電子工業歷經一段革新，係經由許多努 力，縮小在積體電路（IC)上的元件元素尺 提升電路元素之密度，以及元件效能。已成功地製成造力出也許 多半導體元件，廣泛應用在諸多學術領域。 目前，現今最常用i最重要的半導體技術係為石夕系元 件、，而最廣受應用的石夕系帛導體元件㈣M〇s(金屬氧化 半導體，簡稱為金氧半導體）電晶體。一般而言，典型撾〇§ 電晶體的主要元素，包含在上面具有閘電極的半導體基 板。典型上，該閘電極係為一高濃度摻入雜質的導體，而 典型上輸入訊號係透過閘極端而施加於該導體。例如源 極，汲極等高濃度摻入雜質的作用區，係在半導體基板之 中开>/成且連接至源極及没極端子。在閘電極下方的半導 體基板中，形成一通道區，該通道區並分隔源極和汲極區。 一般而言，閘電極係藉由例如氧化層的介電層，而與半導 體基板隔離，以使電流不會流通於閘電極，和源極，汲極 區或通道區之間。 第1圖至第8圖，係表示以習知的程序步驊製作典型 的MOS電晶體之流程。如第i圖所示，氧化層係在例如 典型的矽質半導體基板1〇上熱成長，典型的多晶矽之導電 層係在氧1化層之上形成。氧化層以及導電層，係各自加以 本紙張尺度_ +¾¾家鮮（CNS)A4規格（210 公£3---- 1 91990 (請先閱讀背面之注意事項再填寫本頁) ----- 訂---------線一 X ) 經濟部智慧財產局員工消費合作社印製517290 A7 B7 V. Description of the Invention (Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs [Technical Field] The present invention is related to semiconductor manufacturing technology. In particular, it is a method for making field-effect transistor by low temperature silicidation process. [ Technical background] In recent decades, the electronics industry has undergone a period of innovation. Through many efforts, it has reduced the size of element elements on integrated circuits (ICs) to increase the density of circuit elements and component performance. Many semiconductor components are widely used in many academic fields. At present, the most commonly used semiconductor technology is the Shixi series, and the most widely used Shixi series 帛 conductor element ㈣MOS (metal oxide semiconductor) (Referred to as the metal oxide semiconductor) transistor. Generally speaking, the main element of a typical transistor is a semiconductor substrate with a gate electrode on it. Typically, the gate electrode is a conductor with a high concentration of impurities. The input signal is typically applied to the conductor through the gate terminal. For example, the effect of doping impurities at high concentrations such as source and drain. It is connected in the semiconductor substrate and is connected to the source and terminal. In the semiconductor substrate under the gate electrode, a channel region is formed, which separates the source and drain regions. Generally, In other words, the gate electrode is isolated from the semiconductor substrate by a dielectric layer such as an oxide layer, so that current does not flow between the gate electrode, the source electrode, the drain region, or the channel region. FIGS. 1 to 8 The figure shows the process of making a typical MOS transistor using conventional procedures. As shown in Figure i, the oxide layer is thermally grown on, for example, a typical silicon semiconductor substrate 10, and a typical polycrystalline silicon conductive layer It is formed on the oxygenated layer. The oxide layer and the conductive layer are each in accordance with the paper size _ + ¾¾ CNS A4 size (210 kg £ 3 ---- 1 91990) (please read the note on the back first) Please fill in this page for matters) ----- Order --------- Line one X) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs
五、發明說明（2 圖案化和蝕刻，而分別形 後，如第2圖所示，… 以及間電極14。隨 閘電極η㈣光罩，轉子m等雜制子’藉由利用 在石夕基板10的 :夕基板10的表面中’ φ成淺源極和汲極區16。 在離子植入步驟之德，技装 _ 接耆係一般為攝氏700度或更 兩▲的退火處理步驟，以活化在 化在淺源極和汲極區16中已榷 入的雜質原子，並修補當辘 社娃士 . 田雜質原子植入至矽基板1〇之結晶 、4中時’因物理碰撞而造成的損害。隨後即形成侧壁間 隔層18於閘極介電層12以及閘電層U之側邊上，如第3 所不。 然後’如第4圖所示，藉由利用閘電極14和側壁間隔 層18作為光罩’而以比第—退火處理程序更高的雜質植入 濃度和能量’離子植入例如硼或磷等雜質原子，而形成源 極和沒極區20。再次重中，在攝氏度或更高溫的環境 下執行退火處理程序，以活化在源極和汲極2〇區之中已植 入的雜質原子，並修補因植入碰撞所造成的損害。 因為電晶體之直徑大約為一微米（V m)，故習知的參數 導致在作用區20和導電性内連線之間無法忍受的電阻增 加，該導電性内連線係後來在積體電路元件之中形成以連 接内部之各元件元素。減低這類接觸性電阻的主要方法， 係在施加用以形成多條導電性内連線的導電性薄膜之前， 在源極和汲極區20以及閘電極14之上面先形成金屬石夕化 物。最常用的金屬矽化物材料為CoSi2* TiSi2。 如第5圖所示，典型上，係首先在接觸源極和汲極區 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 91990 --------^---------^ (請先閱讀背面之注意事項再填寫本頁) 2 517290V. Description of the invention (2 Patterning and etching, and after forming, as shown in Figure 2, ... and the inter electrode 14. With the gate electrode η㈣ photomask, rotor m and other hybrids' by using in Shixi substrate 10: In the surface of the substrate 10, φ is a shallow source and drain region 16. In the process of ion implantation, the technical equipment _ connection system is generally an annealing process of 700 degrees Celsius or two ▲ Activate the impurity atoms that have been discussed in the shallow source and drain regions 16 and repair them. When the impurity atoms of the field are implanted into the silicon substrate 10 crystals and 4, it is caused by physical collision. Then, a sidewall spacer 18 is formed on the sides of the gate dielectric layer 12 and the gate dielectric layer U, as shown in Fig. 3. Then, as shown in Fig. 4, by using the gate electrodes 14 and The side wall spacer layer 18 serves as a mask and ion implantation of impurity atoms such as boron or phosphorus with a higher impurity implantation concentration and energy than the first-annealing process to form source and non-electrode regions 20. Again, it is important , Perform an annealing process at a temperature of Celsius or higher to activate the source and drain 2 The implanted impurity atoms in the region, and repair the damage caused by the impact of the implant. Because the diameter of the transistor is about one micrometer (V m), the conventional parameters lead to the interconnection between the active region 20 and the conductivity. An unbearable increase in resistance between lines, the conductive interconnect was later formed in integrated circuit elements to connect the various element elements inside. The main method of reducing this type of contact resistance is to apply multiple A metal thin film is formed on the source and drain regions 20 and the gate electrode 14 before a conductive thin film of conductive interconnects. The most commonly used metal silicide material is CoSi2 * TiSi2. As shown in Figure 5 As shown, typically, the paper is firstly applied to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) in the contact source and drain regions of this paper. 91990 -------- ^ ------ --- ^ (Please read the notes on the back before filling this page) 2 517290
五、發明說明（3 經濟部智慧財產局員工消費合作社印製 3 20的βθ圓上面，覆上一薄層如鈦的元素，以提供金屬層 22。隨後，將此晶圓將於攝氏8〇〇度或更高溫逕行一次或 多次退火處理步驟。這將使鈦層22與源極和汲極區2〇以 及閘電極14之矽，產生選擇性的反應，從而在源極和汲極 區20以及閘電極14之上，選擇性形成金屬矽化”以^)層 24。因為TiSL層24只會在直接接觸到矽源極和汲極2〇， 以及多結晶閘電極14的表面上形成，所以該程序即稱為自 動矽化（salicide，self-aligned siHcide pr〇cess)自動對準矽 化）程序。如第7圖所示，接著矽化層24的成形之後，遂 於基板10的整個表面上，沈積層間介電薄膜26，並執行（未 顯示）内連程序，以藉由在層間介電層26之間形成導通孔 (via holes)，並填入例如鎢的導電材料，而提供導電路徑。 因為M0S電晶體之尺寸，進一步縮小至次微米（sub micron)以及奈米（nanometer)之譜，於是閘極氧化層之厚度 也隨之縮小。然而，閘極氧化層之厚度的過度縮減，造成 載荷子因為穿遂效應而洩漏，因而導致M〇s電晶體之加 速退化。 為解決此問題，遂採用高K(介電常數）閘極介電層， 取代就次微米級之MOS元件所用的氧化矽，該高κ閘極 介電層係例如Zr02，Hf02，In02，La〇2，Ta〇2。然而，已 發現到高K閘極介電層，在製作M0S電晶體的高溫程序 步驟期間，會因受熱而產生不穩定之現象。舉例而言，如 前所述’在第2圖和第4圖中，源極和没極區之活性化退 火處理步驟’以及第6圖中的碎化步驟，一般皆在攝氏7Q〇 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 91990 41^^--------訂---------線· (請先閱讀背面之注意事項再填寫本頁) 517290V. Description of the invention (3 The Intellectual Property Bureau Employee Consumer Cooperative of the Ministry of Economic Affairs printed a 3 20 βθ circle on top and covered it with a thin layer of elements such as titanium to provide a metal layer 22. Subsequently, this wafer will be placed at 80 ° C. One or more annealing steps are performed at 0 ° C or higher. This will cause the titanium layer 22 to selectively react with the source and drain regions 20 and the silicon of the gate electrode 14 to thereby cause a selective reaction between the source and drain regions. 20 and the gate electrode 14 selectively form a metal silicide layer ^) 24. Because the TiSL layer 24 will only be formed on the surface directly contacting the silicon source and drain 20, and the polycrystalline gate electrode 14, Therefore, this process is called a salicide, self-aligned siHcide process. As shown in FIG. 7, after the formation of the silicide layer 24, the entire surface of the substrate 10 is then formed. An interlayer dielectric film 26 is deposited and an interconnection process (not shown) is performed to provide a conductive path by forming via holes between the interlayer dielectric layers 26 and filling in a conductive material such as tungsten. Because of the size of the M0S transistor, As small as the sub micron and nanometer spectrum, the thickness of the gate oxide layer is also reduced. However, the excessive reduction in the thickness of the gate oxide layer causes the charge carriers to leak due to the tunneling effect. In order to solve this problem, a high-K (dielectric constant) gate dielectric layer is used instead of the silicon oxide used in sub-micron-level MOS devices. Dielectric layers are, for example, Zr02, Hf02, In02, La〇2, Ta〇2. However, high-K gate dielectric layers have been found to be unstable due to heat during high-temperature process steps for making MOS transistors. For example, as mentioned above, the steps of activation annealing treatment of source and non-electrode regions in Figures 2 and 4 and the fragmentation step in Figure 6 are generally performed at 7Q Celsius. 〇 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 91990 41 ^^ -------- Order --------- line · (Please read the (Please fill in this page again)
五、發明說明（4 ) 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 4 度或更高溫的環境下執行，在某些情況中甚至是在攝氏 1000度或更高溫的環境下執行。在此高溫下，氧化鈦 (2〇5)即另同K閘極介電層，便從非晶狀轉變成為結 晶狀，而造成載荷子之茂漏。此外，在此高溫中，氧化鈦 遂不口思地和石夕基板底上方，或MOs電晶體之多晶石夕閘 電極下方，產生交互作用。 為解決此㈣，遂採用金屬閘電#，以在高溫程序步 驟期間’避免介於鬲K閘極介電層和多晶矽閘電極之間的 作用。舉例而言，如由Misra，etal4申請之美國專利序號 5,960,27G其中所述，計畫以金屬沈積程序，藉由沈積錮， 鏑r ’石夕化鎢，石夕化鎳，氮化鈇，形成金屬閘極層。然而， 也已發現到，從閘電極擴散入閘極介電層的金屬原子，會 造成高K閘極介電層的加速退化，且高尺閘極介電層和金 屬閘電層二者，皆會由於這種高溫程序步驟，而受到結構 應力的損害。此外，因為金屬或金屬矽化層，係全面沈積 於半導體結構之上，故已發現到，很難可控制地去除已沈 積的金屬或金屬矽化層之不需要的部分，進而無法由於材 料單一性，而使金屬或金屬矽化閘極成形。 因此’持績存在有改良方法之需求，此改良方法必須 能在次微米級之MOS電晶體中，完成可靠的閘極結構， 而不會有不合意的副作用以及複雜的程序步驟。 [發明之揭示] 本發明可滿足這些需求以及其他之需求。本發明係提 供一方法，可在半導體結構中的高κ閘極介電層之上，开 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 91990 ---------------------訂----------線一 (請先閱讀背面之注意事項再填寫本頁) 517290 經濟部智慧財產局員工消費合作社印製 5 A7 五、發明說明（5 ) 成自動對準低溫金屬矽化閘極，進而滿足此需求。此方法 包含，形成具有基板的母體（preeursor)，此基板上有以通 道分隔的作用區，以及在通道之上和層間介電層結構的臨 時閘極。然後去除該臨時閘極，以在介電層結構之間形成 具有底端以及侧壁的凹陷處，並在底端以及侧壁之上的凹 陷處之中沈積高介電常數（高κ)閘極介電層。在包含凹陷 處的半導體結構之上沈積低溫石夕化金屬，然後從半導體結 構上除了凹陷處之中的部位以外去除該低溫矽化金屬。在 半導體結構上沈積矽，並執行退火處理，進而使矽和在凹 陷處之中的低溫矽化金屬部分產生交互作用，從而形成自 動對準低溫金屬矽化閘極。隨後平坦化半導體結構，以消 除非晶矽。 因此，依照本發明之一形態，將在半導體結構上，除 了凹陷處之中的部位以外所沈積的低溫矽化金屬去除，此 動作可使在凹陷處中的部分與矽下方選擇性產生交互作 用，從而在凹陷處選擇性形成自動對準低溫矽化閘極。因 為於石夕和低/JBL梦化金屬之間的石夕化物，係在凹陷處中選 擇{'生發生，且矽的剩餘部分保持不變，故低溫矽化金屬的 剩餘部分，可藉由如平坦化等方法，而輕易消除。此外， 因為金屬石夕化閘極係在大約攝氏7〇〇度的低溫下形成，故 鬲K閘極介電層不會與半導體基底下方，以及閘極上方產 生交互作用。 在此發明之另一實施例中，首先將矽沈積在凹陷處之 接著才沈積低溫矽化金屬。隨後藉由退火處理以及消 關家標準（CNS)A4規格⑵G x 29 ) 91990 -----—^---------^ (請先閱讀背面之注意事項再填寫本頁) 517290V. Description of the invention (4) Printed by the Consumer Affairs Co., Ltd. of the Intellectual Property Office of the Ministry of Economic Affairs under 4 ° C or higher temperature, and in some cases, even at 1000 ° C or higher. At this high temperature, titanium oxide (205), which is also the same as the K gate dielectric layer, changes from amorphous to crystalline, resulting in leakage of charge carriers. In addition, at this high temperature, titanium oxide does not interact with the top of the Shixi substrate or the polycrystalline silicon gate electrode of the MOs transistor. To solve this problem, a metal gate # is used to avoid the interaction between the 鬲 K gate dielectric layer and the polysilicon gate electrode during the high temperature process steps. For example, as described in U.S. Patent No. 5,960,27G, filed by Misra, etal4, a metal deposition process is planned to deposit hafnium, 镝 r 'stone tungsten carbide, stone silicon carbide, hafnium nitride, A metal gate layer is formed. However, it has also been found that metal atoms diffused from the gate electrode into the gate dielectric layer will cause accelerated degradation of the high-K gate dielectric layer, and both the high-scale gate dielectric layer and the metal gate layer, All are subject to structural stress damage due to this high temperature process step. In addition, because the metal or metal silicide layer is fully deposited on the semiconductor structure, it has been found that it is difficult to controllably remove unwanted portions of the deposited metal or metal silicide layer, and therefore cannot be due to the uniformity of the material. The metal or metal silicided gate is formed. Therefore, there is a need for an improvement method for this performance. This improvement method must be able to complete a reliable gate structure in a sub-micron MOS transistor without undesired side effects and complicated program steps. [Disclosure of the Invention] The present invention can meet these needs and other needs. The invention provides a method, which can be used on a high-k gate dielectric layer in a semiconductor structure, and the paper size is adapted to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 91990 ------- -------------- Order ---------- Line 1 (Please read the precautions on the back before filling out this page) 517290 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs System 5 A7 5. Description of the invention (5) Automatically align the low temperature metal silicified gate to meet this demand. This method includes forming a preeursor with a substrate having active regions separated by channels, and temporary gates on the channels and interlayer dielectric layer structures. The temporary gate is then removed to form a recess with a bottom end and a sidewall between the dielectric layer structures, and a high dielectric constant (high κ) gate is deposited in the bottom end and the recess above the sidewall. Polar dielectric layer. A low-temperature petrified metal is deposited on the semiconductor structure including the depression, and then the low-temperature silicidated metal is removed from the semiconductor structure except for the portion in the depression. Silicon is deposited on the semiconductor structure and an annealing process is performed to interact the silicon with the low-temperature silicided metal portion in the depression, thereby forming an auto-aligned low-temperature metal silicided gate. The semiconductor structure is then planarized to eliminate the amorphous silicon. Therefore, according to one aspect of the present invention, the low-temperature silicided metal deposited on the semiconductor structure except for the portion in the depression is removed. This action can selectively interact with the portion under the silicon in the depression. Thereby, a self-aligned low-temperature silicidation gate is selectively formed in the depression. Because the stone compound between Yu Xixi and Low / JBL Dream Metal is selected in the depression, {'generation occurs, and the remaining part of silicon remains unchanged, so the remaining part of low temperature silicified metal can be obtained by, for example, Methods such as planarization, and easily eliminated. In addition, since the metallized gate is formed at a low temperature of about 700 degrees Celsius, the 鬲 K gate dielectric layer does not interact with the semiconductor substrate and above the gate. In another embodiment of the invention, silicon is first deposited in the depression and then low temperature silicided metal is deposited. Then by annealing treatment and Consumer Standard (CNS) A4 specification ⑵G x 29) 91990 -----— ^ --------- ^ (Please read the precautions on the back before filling this page) 517290
製 6 除未反應的矽化金屬，而在閘極中形成石夕化物。 熟悉此技藝者將可從下列詳細描述中，對本發明之附 加目的更加瞭解，其中僅以用以實施本發明最佳模式之範 例，來顯示並描述本發明之較佳實施型態。如同所即明白 瞭解的，本發明可具有其它不同的實施例，且其各種細節， 只要不違背本發明，皆可依各種明顯不同的觀點，而2生 變型。因此，所附之圖式以及說明在本質上皆視為例示性 質，而非限制。 [圖式之簡單說明] 本發明經由附圖，以及參照至圖中元件之參考數字而 顯示，故將其視為範例而非限制。 第1圖係先存技藝半導體結構之斷面示意圖，閘電極 係在半V體基底上形成’且有一閘極氧化層介於其間。 第2圖表示第1圖之部分，於第一離子植入程序期間， 在基板主表面上形成淺源極和汲極區。 弟3圖表示第2圖之部分，在第一退火處理程序，以 及侧壁間隔層成形程序之後之狀態。 第4圖表示第3圖之部分，於第二離子植入程序期間， 在基板主表面上形成源極和汲極區。 第5圖表示第4圖之部分，在第二退火處理程序，以 及金屬層沈積程序之後之狀態之狀態。 第6圖表示第5圖之部分，在於源極，汲極，和閘電 極之上，形成金屬矽化層的矽化程序之後之狀態。 ^17圖表示第6圖之部分，在半導體結構之上，形成 本紙張尺度適用中國國家標準（CNS)A4規格（21〇x 297公釐） 91990 --------tl---------%· (請先閱讀背面之注意事項再填寫本頁〕 517290 A7 B7 經濟部智慧財產局員工消費合作社印製 7 五、發明說明（7 詹間介電層之後之狀態之狀態。 第8圖表示依照本發明實施例之车墓 弋牛導體結構母體斷面 示意圖。 第9圖表示第8圖之部分，在以消除臨時閑電極而形 成凹陷處之後之狀態。 第10圖表不第9圖之部分，在已於凹陷處表面上以及 層間介電層之上沈積高K介電層之後之狀態。 第11圖表示第10圖之部分，在已於高K介電層之上 沈積低溫矽化金屬之後之狀態。 第12圖表示第11圖之部分，從除了凹陷處以外之部 分去除低溫矽化金屬之後之狀態。 第13圖表示第12圖之部分，在半導體結構上全面沈 積矽之後之狀態。 第14圖表示第13圖之部分，經退火處理而在通道上 形成自動對準低溫矽化閘極之後之狀態。 第15圖表示第13圖之部分，將半導體結構平坦化， 而已去除低溫矽化金屬之後之狀態。 第1 6圖表示第10圖之部分，依照本發明之另一實施 例，已於高K介電層之上沈積非晶矽之後之狀態。 第17圖表示第16圖之部分，已去除除凹陷處中之部 分之非晶矽之後之狀態。 第18圖表示第17圖之部分，已於半導體結構之上全 面沈積低溫矽化金屬之後之狀態。 第19圖表示第18圖之部分，經退火處理而在通道上 本紙張尺度適用中國國家標準（CNS)A4規格（210x297公釐） 91990 ---------------------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 517290 Α7 ------- Β7 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 五、發明說明（8 ) 形成自動對準低溫矽化閘極之後之狀態。 第20圖表示第1 9圖之部分，將矽化後剩餘的低溫矽 化金屬去除之後之狀態。 [元件符號說明] 1 〇 基底 12 多晶矽閘極 16 側壁間隔層 20 金屬層 24 層間介電層 28 高K閘極介電層 32 石夕 36 非晶秒層 134 自動對準矽化金屬閘極 [發明之實施型態] 下述方法及裝置，並不構成完整的積體電路製作流 程。本發明可與現今通用的積體電路製作技術一併實行， 且唯有包含如此繁複的實行程序步驟，才足夠作為理解々 發明之所需。圖中並未將製作期間之半導體晶片或基板$ 斷面部分依實際尺寸比例繪出，而是以顯示本發明之特黑 的方式繪出。 0 本發明係提供一方法，可於高κ閘極介電層上實施自 動對準低溫金屬矽化閘極，而不會有習知方法所衍生之問 題此乃藉由使用虛設閘極（dummy gate)之技術，將低溫 _石夕化金屬限制在通道上的凹陷處中，並退火處理，以使俏 本紙張尺度適用中國國家標準（CNS)A4規格⑵〇 χ 297公髮） 14 18 22 26 30 34 132 136 介電層 淺坑源極/没極 作用區 矽化層 開口部份 低溫矽化金屬 自動對準矽化金屬 金屬層 閘極 --------------------訂---------線 41^ (請先閱讀背面之注意事項再填寫本頁) 91990 8 517290 經濟部智慧財產局員工消費合作社印製 9 A7 B7 五、發明說明（9 ) 溫石夕化金屬與覆蓋其上的石夕產生反應，而形成自動對準低 溫金屬矽化閘極，從而達成此一目的。因為除了凹陷部分 以外之其他部位之低溫梦化金屬皆在低溫石夕化之前去除， 故其餘尚未反應的石夕，即可藉由例如化學機械研磨等平坦 化方法而輕易去除。此外，因為金屬矽化閘極係以大約攝 氏700度的低溫所形成，故高K閘極介電層便不會與在其 下方之半導體基板以及在其上方之閘極產生交互作用。在 其它實施例中，先將矽沈積於凹陷處之中，而後將矽化金 屬沈積覆蓋於矽之上，接著再藉由退火處理而形成矽化 物。 依據上述之條件第8圖表示依照本發明之實施例所建 構的半導體結構之母體之斷面圖。在第8圖中，矽基板10 具有一作用區20,該作用區係以習知的離子植入和隨後的 退火處理技術而在矽基板之中形成。在作用區2〇之上面， 开> 成有石夕化層24，以減少介於作用區20以及將於隨後形 成的導電内連線之間的電阻。 在通道上面具有作為臨時閘極所用的多晶矽閘極 14。於閘極14之側壁，提供有側壁間隔層18，並提供層 間介電層26，覆蓋於作用區20以及矽化層24之上。雖然 並未顯示’在基板10以及閘極14之間，可形成一氧化石夕 閘極介電層。 如刖所述’在例如攝氏7〇〇度或更高溫底下的退火處 理以及石夕化步驟，皆可考慮在臨時閘極14從側壁間隔層 18之間的區域去除之前實施。如第9圖所示。使用的電 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 x 297公釐） 91990 --------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 517290 經濟部智慧財產局員工消費合作社印製 A7 B7 ---—-- 五、發明說明（10 ) 漿反應性離子蝕刻（RIE)，或是採用習知的蝕刻化學物質之 濕性多晶石夕触刻，皆可利用來去除多晶石夕閘極14，以形成 開口部分（例如，凹陷處）28。 在第10圖中，係提供一高K介電層30,舉例而言， 其厚度大約介於50 A至2Q0 A之間。例如化學汽相沈積等 習知的沈積方法，可作為沈積高K閘極介電層3〇之用。 舉例而言，可在高K閘極介電層30中所使用的典型材料 包括有Zr02，Hf02，In02，La02，Ta02。其他複合金屬氧 化物或鈣鈦礦，皆可在層間介電層26之中，作為高κ閉 極介電材料使用。 如前所述，會使用高Κ閘極材料作為閘極介電層的原 因’係因為習知的二氧化碎不再具延伸性。再者，高κ閉 極介電層，提供給閘極和通道較佳的電耦合（electrieal coupling)。此外，藉由高κ材料，使得在得到相同電場之 情开> 下，即可使用較厚的厚膜。然而，我們所關注高κ材 料的其中一點，即是其低溫穩定性。換句話說，於高溫環 ^下¥ ’馬Κ材料係和矽基板產生反應。使用高κ材料例 如矽化鎳，在低溫處理，符合上述需求。 第11圖表示，在低溫矽化金屬（例如，鎳）之沈積過後， 第3圖的半導體結構。低溫矽化金屬32係位於凹陷處28 之中，而該凹陷處係位於高Κ閘極介電層3〇上面。可藉 由低溫化學汽相沈積（CVD)，或是電漿增強化學汽相沈積 (PECVD)等方法，執行沈積。 在低溫石夕化金屬32的沈積之後，如第12圖所述，將 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公爱) "~ ---- ---------#--------訂---------線· (請先閱讀背面之注咅？事項再填寫本頁) 10 91990 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 11 517290 A7 ------- B7 五、發明說明（11 ) 第11圖之半導體結構藉由化學機械平坦化（CMp)等方法， 而平坦化，舉例言之，除了凹陷處28之中的部分以外，去 除所有的低溫矽化金屬32以及高κ閘極介電層3〇。如後 所述，藉由將低溫矽化金屬32侷限於凹陷處28之中，而 達成自動對準矽化之目的。 在第13圖中，將矽（例如，非晶矽或多晶矽）34藉由習 知的沈積技術，而全面沈積於半導體結構之上。可藉由低 溫化學汽相沈積（CVD)，在足以使高κ閘極介電層3〇不會 變為不穩定的溫度之下，而執行此沈積，舉例而言，在大 約介於攝氏500度至攝氏6〇〇度的溫度下即可。 隨後，在第丨4圖中，執行一退火動作，而將限制在凹 陷處28之内的低溫石夕化金屬32，轉變為自動對準石夕化物 36。因為矽34係有限地接觸位於凹陷處28之上的 化金屬32，故自動對準矽化金屬閘極（例如，矽化鎳）， 係在高Κ閘極介電層30之上選擇性形成。而其餘矽34， 即未接觸低溫矽化金屬32的部分，則保持不變。為維持 Κ閘極介電層30的穩定，故在大約介於攝氏5〇〇度至攝氏 6〇〇度的溫度下，執行為期大約介於3〇秒至大約6〇秒的 快速加熱退火處理，以形成自動對準石夕化金屬閉極（例如， 矽化鎳）36。 在第15圖中m之其餘未反應的部分，係藉由習 知的平坦化技術而去除’例如藉由利用介於金屬石夕化閉極 (例如’發化鎳閘極）36’和石夕層34之間的材料差里性，而 ^行的化學機械研磨（CMP)。因# 本紙張尺度適財國國家標準（CNS)A4規格（210 X 297公^----- 你 91990 訂---------線 (請先閱讀背面之注意事項再填寫本頁) 517290 A7System 6 removes unreacted silicides and forms petrochemicals in the gate. Those skilled in the art will better understand the additional objects of the present invention from the following detailed description, in which only the best mode for implementing the present invention is used to show and describe the preferred embodiment of the present invention. As is immediately understood, the present invention may have other different embodiments, and various details thereof may be modified in a variety of different ways without departing from the present invention. Accordingly, the accompanying drawings and descriptions are to be regarded as illustrative in nature, and not as restrictive. [Brief description of the drawings] The present invention is shown through the drawings and reference numerals referring to the elements in the drawings, so it is regarded as an example rather than a limitation. Fig. 1 is a schematic cross-sectional view of a semiconductor structure of a prior art. The gate electrode is formed on a half-V substrate with a gate oxide layer interposed therebetween. FIG. 2 shows a part of FIG. 1. During the first ion implantation procedure, a shallow source and a drain region are formed on the main surface of the substrate. Figure 3 shows the part of Figure 2 after the first annealing process and the sidewall spacer forming process. FIG. 4 shows a part of FIG. 3. During the second ion implantation process, source and drain regions are formed on the main surface of the substrate. Fig. 5 shows the state of the part of Fig. 4 after the second annealing process and the metal layer deposition process. Fig. 6 shows a part of Fig. 5 after the silicidation process of forming a metal silicide layer on the source, drain, and gate electrodes. Figure ^ 17 shows the part of Figure 6. Based on the semiconductor structure, the paper size is applied to the Chinese National Standard (CNS) A4 specification (21 × 297 mm) 91990 -------- tl --- ------% · (Please read the precautions on the back before filling this page) 517290 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 7 V. Description of the invention (7 Status of the state after the dielectric layer) Fig. 8 is a schematic cross-sectional view of a mother body of a car tomb yak conductor structure according to an embodiment of the present invention. Fig. 9 shows a part of Fig. 8 after the depression is formed by eliminating temporary idle electrodes. Fig. 10 The part shown in FIG. 9 is a state after a high-K dielectric layer has been deposited on the surface of the depression and on the interlayer dielectric layer. FIG. 11 shows a part of FIG. 10 after the high-K dielectric layer has been deposited. The state after the low-temperature silicide metal is deposited on it. Fig. 12 shows the part of Fig. 11 after removing the low-temperature silicide metal from the part other than the depression. Fig. 13 shows the part of Fig. 12 where the semiconductor structure is fully deposited. State after silicon Figure 14 shows Figure 13 Part of it is annealed to form a state after automatic alignment of the low-temperature silicided gate on the channel. Figure 15 shows the part of Figure 13 after the semiconductor structure is flattened and the low-temperature silicided metal has been removed. The figure shows a part of FIG. 10, according to another embodiment of the present invention, after the amorphous silicon has been deposited on the high-K dielectric layer. FIG. 17 shows the part of FIG. 16, except that the depressions have been removed Figure 18 shows the state after amorphous silicon. Figure 18 shows the part of Figure 17 after the low-temperature silicidation metal has been fully deposited on the semiconductor structure. Figure 19 shows the part of Figure 18 after annealing treatment. The paper size on the aisle applies to the Chinese National Standard (CNS) A4 (210x297 mm) 91990 --------------------- Order -------- -Line (Please read the precautions on the back before filling this page) 517290 Α7 ------- Β7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (8) Forming the self-aligned low-temperature siliconized gate After that, Fig. 20 shows a part of Fig. 19, and the silicon The state after the remaining low-temperature silicide metal is removed. [Element symbol description] 1 〇 Base 12 Polycrystalline silicon gate 16 Side wall spacer 20 Metal layer 24 Interlayer dielectric layer 28 High-K gate dielectric layer 32 Shi Xi 36 Amorphous seconds Layer 134 automatically aligns with a silicided metal gate [implementation mode of the invention] The following methods and devices do not constitute a complete integrated circuit manufacturing process. The present invention can be implemented together with current integrated circuit manufacturing technologies, and It is only necessary to include such complicated procedural steps to understand the invention. In the figure, the cross section of the semiconductor wafer or substrate $ during production is not drawn according to the actual size ratio, but is drawn in a way that shows the special black of the present invention. 0 The present invention provides a method for automatically aligning low-temperature metal silicided gates on high-k gate dielectrics without the problems derived from conventional methods. This is achieved by using dummy gates. ) Technology, the low temperature _ Shi Xihua metal is confined in the depression on the channel, and annealed, so that the size of the paper is suitable for the Chinese National Standard (CNS) A4 specification (⑵χχ 297) 14 18 22 26 30 34 132 136 Dielectric layer shallow pit source / dead active area silicide layer opening part low temperature silicide metal automatically aligned with silicide metal layer gate ----------------- --- Order --------- Line 41 ^ (Please read the notes on the back before filling in this page) 91990 8 517290 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 9 A7 B7 V. Description of the invention ( 9) The warm Shixi metal reacts with the Shixi covering it to form a self-aligned low-temperature metal silicide gate to achieve this goal. Because the low-temperature dream metal in all parts other than the recessed portion is removed before the low-temperature lithography, the remaining unreacted lithography can be easily removed by a planarization method such as chemical mechanical polishing. In addition, because the metal silicided gate is formed at a low temperature of about 700 degrees Celsius, the high-K gate dielectric layer does not interact with the semiconductor substrate below it and the gate above it. In other embodiments, silicon is deposited in the depression first, and then a silicide metal is deposited on the silicon, and then a silicide is formed by annealing. FIG. 8 shows a cross-sectional view of a mother body of a semiconductor structure constructed in accordance with an embodiment of the present invention in accordance with the above conditions. In FIG. 8, the silicon substrate 10 has an active region 20, which is formed in the silicon substrate by a conventional ion implantation and subsequent annealing processing technique. Above the active area 20, a petrified layer 24 is formed to reduce the resistance between the active area 20 and a conductive interconnect to be formed later. Above the channel is a polycrystalline silicon gate 14 for use as a temporary gate. A sidewall spacer layer 18 is provided on the sidewall of the gate electrode 14, and an interlayer dielectric layer 26 is provided to cover the active region 20 and the silicide layer 24. Although not shown 'between the substrate 10 and the gate electrode 14, a oxide oxide gate dielectric layer may be formed. As described above, the annealing treatment and the petrification step at, for example, 700 ° C or higher may be performed before the temporary gate 14 is removed from the region between the sidewall spacers 18. As shown in Figure 9. The size of the electric paper used is applicable to China National Standard (CNS) A4 (21 × 297 mm) 91990 -------- Order --------- line (please read the note on the back first) Please fill in this page again) 517290 Printed A7 B7 by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ------ 5. Description of the invention (10) Plasma reactive ion etching (RIE), or using conventional etching chemicals The wet polycrystalline stone can be etched to remove the polycrystalline silicon gate 14 to form an opening (eg, a depression) 28. In FIG. 10, a high-K dielectric layer 30 is provided. For example, the thickness is about 50 A to 2Q0 A. For example, a conventional deposition method such as chemical vapor deposition can be used as a deposited high-k gate dielectric layer 30. For example, typical materials that can be used in the high-K gate dielectric layer 30 include Zr02, Hf02, In02, La02, Ta02. Other composite metal oxides or perovskites can be used in the interlayer dielectric layer 26 as a high κ closed dielectric material. As mentioned earlier, the reason why a high-K gate material is used as the gate dielectric layer 'is because the conventional dioxide fragmentation is no longer extensible. Furthermore, a high-k closed-gate dielectric layer provides better electrical coupling between the gate and the channel. In addition, with a high κ material, a thicker film can be used when the same electric field is obtained. However, one of the concerns of high kappa materials is their low temperature stability. In other words, under the high-temperature environment, the reaction between the material and the silicon substrate occurs. The use of high-k materials such as nickel silicide, which is processed at low temperatures, meets the above requirements. FIG. 11 shows the semiconductor structure of FIG. 3 after deposition of a low-temperature silicided metal (eg, nickel). The low temperature silicide metal 32 is located in the depression 28, and the depression is located above the high-K gate dielectric layer 30. Deposition can be performed by methods such as low temperature chemical vapor deposition (CVD), or plasma enhanced chemical vapor deposition (PECVD). After the deposition of the low-temperature petrified metal 32, as shown in Figure 12, the paper size will be applied to the Chinese National Standard (CNS) A4 specification (21〇X 297 public love) " ~ ---- ---- ----- # -------- Order --------- line · (Please read the note on the back? Matters before filling out this page) 10 91990 Consumption by Employees of Intellectual Property Bureau, Ministry of Economic Affairs Printed by the cooperative 11 517290 A7 ------- B7 V. Description of the invention (11) The semiconductor structure in Figure 11 is flattened by methods such as chemical mechanical planarization (CMp), for example, except for the depressions Except for part 28, all the low-temperature silicide metal 32 and the high-k gate dielectric layer 30 are removed. As will be described later, the purpose of automatically aligning the silicidation is achieved by confining the low-temperature silicided metal 32 to the recess 28. In Figure 13, silicon (e.g., amorphous silicon or polycrystalline silicon) 34 is fully deposited on the semiconductor structure by conventional deposition techniques. This deposition can be performed by low temperature chemical vapor deposition (CVD) at a temperature sufficient to prevent the high κ gate dielectric layer 30 from becoming unstable, for example, at about 500 ° C It can be at a temperature of 600 degrees Celsius. Subsequently, in FIG. 4, an annealing operation is performed, and the low-temperature petrified metal 32 confined within the depression 28 is converted into an auto-aligned petrified material 36. Because the silicon 34 is in limited contact with the metallized metal 32 above the recess 28, the silicon self-aligned metal gate (for example, nickel silicide) is automatically aligned and is selectively formed over the high-K gate dielectric layer 30. The remaining silicon 34, that is, the portion not in contact with the low temperature silicide metal 32, remains unchanged. In order to maintain the stability of the K gate dielectric layer 30, a rapid heating annealing process is performed at a temperature of about 500 to 600 degrees Celsius for a period of about 30 to 60 seconds. To form a self-aligned lithographic metal closed electrode (eg, nickel silicide) 36. The remaining unreacted part of m in Fig. 15 is removed by the conventional planarization technique, for example, by using a closed metal electrode (such as a 'fahua nickel gate) 36' and a stone The material between the layers 34 is poor, and the chemical mechanical polishing (CMP) is performed. Because # This paper size is suitable for National Standards (CNS) A4 specifications (210 X 297) ^ ----- you 91990 order --------- line (Please read the precautions on the back before filling in this (Page) 517290 A7
經濟部智慧財產局員工消費合作社印製 K閘極介電層30之上選擇性形成，而 陷處的所有半導體結構表面之面沈積在包括凹 化風掾钟nt洽 此平坦化步驟可藉由 化予機械研磨，研磨至直到沒有矽 金屬„ # Μ & &上γ 檢：利出’便可使矽化 、屬閘極36自動成形’從而減少執行時的複雜度。 從而，本發明之實施例，便可藉由運用介於金屬碎化 :極’和在金屬碎化閉極之上的梦之材料差㈣而完成 在尚K介電薄臈之上的自動對準低溫金屬石夕化閘極。依昭 本發明’較低溫时化係在所必須的表面上發生，從而避 免整個半導體結構的上層表面之梦化。這使得低溫金屬梦 化閘極便可簡單地經由將未反應的矽平坦化，直到沒有矽 去消除，從而更容易使之成形。此外’因為金屬矽化閘極 係在例如大約攝氏700度的低溫時形成，故高K閘極介電 層便不會與在其下之半導體基板，以及在其上方之閘極產 生交互作用。 第16圖表示在非晶矽層132沈積過後之第3圖的半導 體結構。非晶矽層132係提供在凹陷處28之中，該凹陷處 28之中係位於高K閘極介電層30頂端之上。可藉由低溫 化學汽相沈積（CVD)，在足以使高K閘極介電層30不會變 為不穩定的溫度之下，執行此沈積，舉例而言，在大約介 於攝氏500度至攝氏600度的溫度下即可。 在非晶矽132的沈積之後，如第17圖所示，第16圖 之半導體結構即藉由化學機械平坦化（CMP)等方法，而平 坦化，舉例說明，除了凹陷處2 8之中的部分以外，消除所 有的非晶矽1 32以及高K閘極介電層30。如後所述，藉由 !------0--------^---------$ (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 12 91990 517290The Intellectual Property Bureau of the Ministry of Economic Affairs ’employee consumer cooperative selectively prints on the K gate dielectric layer 30, and the surface of all the semiconductor structures in the depressions is deposited on the surface including the concave wind chimes. This flattening step can be achieved by Chemical mechanical grinding, grinding until there is no silicon metal # # Μ & & Upper γ Inspection: Sharp out 'can make silicified, belong to the gate 36 is automatically formed' to reduce the complexity of execution. Therefore, the present invention Example, the automatic alignment of low-temperature metal stones can be completed by using the material difference between metal fragmentation: poles and dreams above metal fragmentation and closed electrodes. According to the present invention, the 'lower temperature time chemical system occurs on the necessary surface, so as to avoid the dreaming of the upper surface of the entire semiconductor structure. This allows the low temperature metal dreaming gate to be simply The silicon is flattened until there is no silicon to eliminate it, which makes it easier to shape. In addition, 'Si because the metal silicided gate is formed at a low temperature of about 700 degrees Celsius, for example, the high-K gate dielectric layer does not Semiconducting The substrate and the gate above it interact with each other. Figure 16 shows the semiconductor structure of Figure 3 after the amorphous silicon layer 132 has been deposited. The amorphous silicon layer 132 is provided in the recess 28, which is a recess The location 28 is located on top of the high-K gate dielectric layer 30. By low temperature chemical vapor deposition (CVD), the high-K gate dielectric layer 30 can be kept at a temperature that is not unstable. Next, perform this deposition, for example, at a temperature of about 500 degrees Celsius to 600 degrees Celsius. After the deposition of amorphous silicon 132, as shown in FIG. 17, the semiconductor structure of FIG. 16 is By chemical mechanical planarization (CMP) and other methods, the planarization, for example, eliminates all of the amorphous silicon 1 32 and the high-K gate dielectric layer 30 except for the part in the depression 28. As described later As mentioned, with! ------ 0 -------- ^ --------- $ (Please read the precautions on the back before filling this page) This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) 12 91990 517290
五、發明說明（I3 氺非日日矽132置於凹陷處28之中，而達成自動對準石夕化之 目的。 在第18圖中，低溫矽化金屬（例如，鎳）134係藉由習 知的沈積技術，而全面沈積在半導體結構之上。於是，在 第19圖中，執行一退火動作，而將限制在凹陷處28之内 的非晶矽132,轉變為自動對準矽化物136。因為金屬層 134係有限地接觸位於凹陷處28之上的非晶矽η〗，故自 動對準矽化金屬閘極（例如，矽化鎳）136，係在高κ閘極介 電層30之上選擇性形成。而其餘低溫矽化金屬，即未 接觸非晶石夕132的部分，則保持不變。為維持高κ閘極介 電層30的穩定，故在大約介於攝氏5〇〇度至攝氏6⑼度的 溫度下，執行為期大約介於30秒至大約6〇秒的快速加熱 迟火處理以形成自動對準碎化金屬閘極（例如，石夕化鎳） 136 ° 在第20圖中，低溫矽化金屬134之其餘未反應的部 分，係藉由習知的蝕刻技術而去除，例如藉由利用介於金 屬矽化閘極（例如，矽化鎳）136，和金屬層（例如，鎳）134 之間的選擇性。因為矽化金屬閘極136係在高κ閘極介電 層30之上選擇性形成，故剩餘的矽化金屬134可藉由使用 餘刻齊丨而拳二易去除，該餘刻劑舉例而言，如硫酸，硝酸， 過氧化氣在珍化金屬閘極136與金屬層134之間，係具有 问度選擇性，此時的半導體結構便具有完整的取代閘電 極，其包含可就高Κ閘極介電層3〇，以及金屬矽化閘極 136。 本紙張尺度適用中國iii準（CNS)A4規格⑵G χ 297公以----- 13 91990 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 .·--------訂---------線-·--------------------- 517290 五、發明說明（Η ) 從而’本發明之實施例，便可藉由運用介於金屬矽化 閑極，和在金屬矽化閘極之上的金屬之蝕刻選擇性，而完 成自動對準低溫金屬矽化閘極。此外，因為金屬矽化閘極 係在例如大約攝氏700度的低溫時形成，故高K閘極介電 層便不會與半導體基底下方，以及閘極上方產生交互作 用。 ;已洋、、、田把述及顯示本發明，但仍可清楚瞭解到， 僅將其視為說明以及範例，而非限制，唯有在申請專利範 圍中所條列之項目，才視為本發明範之限制。 (請先閱讀背面之注音？事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 適 度-尺 |張 氏 釐 公 97 2 X 10 2 /V 格 規 4 A S) N (C 準 標 家 I國 I國 14 91990V. Description of the invention (I3: Non-Japanese-Japanese silicon 132 is placed in the depression 28, and the purpose of automatically aligning the lithography is achieved. In Figure 18, the low-temperature silicidated metal (for example, nickel) 134 is based on the Xi The known deposition technique is used to deposit the semiconductor structure in a comprehensive manner. Therefore, in FIG. 19, an annealing operation is performed, and the amorphous silicon 132 confined within the recess 28 is converted into a self-aligned silicide 136. Since the metal layer 134 is in limited contact with the amorphous silicon η located above the depression 28, it automatically aligns with a silicided metal gate (eg, nickel silicide) 136, which is above the high-k gate dielectric layer 30 Selectively formed. The remaining low-temperature silicided metal, that is, the portion that does not contact the amorphous stone 132, remains unchanged. In order to maintain the stability of the high-k gate dielectric layer 30, it is between about 500 degrees Celsius and about At a temperature of 6 ° C, a rapid heating late-fire process is performed for a period of about 30 seconds to about 60 seconds to form an auto-aligned shattered metal gate (eg, nickel nickel) 136 ° In Figure 20 The remaining unreacted part of the low temperature silicided metal 134 is It is removed by a conventional etching technique, for example, by using a selectivity between a metal silicide gate (for example, nickel silicide) 136 and a metal layer (for example, nickel) 134. Because the silicide metal gate 136 is at a high level The κ gate dielectric layer 30 is selectively formed, so the remaining silicided metal 134 can be easily removed by using the etch, such as sulfuric acid, nitric acid, and peroxide gas. Between the refined metal gate 136 and the metal layer 134, there is a degree of selectivity. At this time, the semiconductor structure has a complete replacement of the gate electrode, which includes a high-k gate dielectric layer 30, and metal silicide. Gate 136. This paper size is applicable to China III (CNS) A4 specifications ⑵ G χ 297 public ----- 13 91990 (Please read the precautions on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs --------- Order --------- Line ---------------------- 517290 V. Description of the invention (Η) Thus, according to the embodiment of the present invention, by using an etching selectivity between a metal silicided idler and a metal above a metal silicided gate, It automatically aligns the low temperature metal silicide gate. In addition, because the metal silicide gate is formed at a low temperature of about 700 degrees Celsius, for example, the high-K gate dielectric layer does not occur below the semiconductor substrate and above the gate. The interaction has been described and shown by the present invention, but it is still clearly understood that it is only regarded as an illustration and an example, rather than a limitation, and only the items listed in the scope of patent application, It is considered to be a limitation of the scope of the present invention. (Please read the note on the back? Matters before filling out this page.) The Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs printed a moderate-feet | Zhang's centimeter 97 2 X 10 2 / V grid 4 AS ) N (C Associate Standard I Country I Country 14 91990