WO2001015361A1

WO2001015361A1 - Routing interfaces into a backplane

Info

Publication number: WO2001015361A1
Application number: PCT/FI2000/000697
Authority: WO
Inventors: Jorg Laumann
Original assignee: Nokia Networks Oy
Priority date: 1999-08-19
Filing date: 2000-08-17
Publication date: 2001-03-01
Also published as: AUPQ234099A0

Abstract

A method and data interface unit for routing two or more data input streams into one or more data output streams is disclosed. A Data Interface Unit (20) has two input modules (30,32), providing four interface input channels (40-46). A logical AND gate (70) receives four input TDM buses; and outputs on two output TDM buses to a bus interface ASIC (80). Two or four TDM buses can be switched to a respective TDM output bus. For two such buses, this is done in a manner such that a first data block from a frame of an input stream is mapped to the beginning part of an output stream, and a second data block from a frame of another input stream is mapped to the end part of an output stream.

Description

ROUTING INTERFACES INTO A BACKPLANE

Field of the Invention

The invention relates to the field of data communications, and particularly to interface equipment that routes data into a backplane or bus structure.

Background of the Invention

In communications equipment there is a need to provide an interface between peripheral devices such as personal computers, telephones (POTS) and local exchanges. One specific example is as a business multiplexing unit by which many forms of data terminal equipment can be connected to a fixed access network.

A typical configuration for such equipment will consist of a rack mounted enclosure having a master controller unit and a number of slots into which can be inserted data interface units to support the peripheral equipment. A backplane bus structure interconnects the interface boards with the master unit. Rack mount units tend to be of a standardised configuration, such that a particular number of interface slots are provided. Designers of this equipment are aware of the desire to increase the density of boards within the slots to contain physical space requirements without incurring significant cost penalties. There is also a need identified to provide for greater flexibility in the configuration of such rack mount interface systems with reference to the peripheral equipment that an individual interface board can support.

Disclosure of the Invention It is an object of the invention to provide one or more of the desirable results not provided by the prior art arrangements.

Therefore, the invention discloses a method for routing two or more data input streams of a data interface unit, arranged in frames, into one or more data output streams, arranged in frames of the same length, the method comprising the steps of: mapping a first data block from a frame in a first input stream to the beginning part of a frame in an output stream; and mapping a second data block from a frame in a second input stream to the end part of the same frame in said output stream.

The invention further discloses a method for routing four or more data input streams of a data interface unit, arranged in frames, into two or more data output streams, the method comprising the steps of:

(a) mapping a first data block from a frame in a first input stream to the beginning part of a frame in a first output stream;

(b) mapping a second data block from a frame in a second input stream to the end part of the frame in said first output stream;

(c) mapping a third data block from a frame in a third input stream to the beginning part of a frame in a second output stream; and

(d) mapping a fourth data block from a frame in a fourth input stream to the end part of the frame in said second output stream.

The invention yet further discloses a data interface unit for routing two or more data input streams into one or more data output streams, comprising: two interface modules each receiving one or more data input streams ad converting each stream into frames; and two logical AND elements each receiving two or more input streams from one or both interface modules and mapping a first data block from a frame in a first input stream to the beginning part of a frame in an output stream, and to map a second data block from a frame in a second input stream to the end part of the same frame in said output stream.

The invention yet further discloses a network access node comprising: a master control unit; a backplane bus to which the master control unit is connected; and one or more data interface units as defined above for Data Terminal Equipment (DTE), the output streams of which connect to the backplane bus, and wherein the master control unit controls switching of data traffic between the data interface units.

5

A particular advantage of embodiments of the invention is that a data interface unit, occupying a single rack slot, can support four Data Terminal Equipment devices. Other advantages are discussed in the following description.

l o Brief Description of the Drawings

Embodiments of the invention will now be described with reference to the accompanying drawings, in which:

Fig. 1 is a schematic block diagram of a network access node; Fig. 2a is a schematic block diagram of a data interface unit; is Fig. 2b is a schematic block diagram of showing greater detail of Fig. 2a;

Fig. 3a and 3b shows an arrangement of data in timeslots embodying the invention; Figs. 4a and 4b show another embodiment of data arranged in timeslots; and Fig. 5 is a flow diagram describing software configuration of the TDM buses.

20 Description of Preferred Embodiments

Fig. 1 shows a network access node 10 in the form of a rack mount housing 12 that contains a number of slots into which equipment boards can be inserted. The boards connect with a backplane 14 carrying a multi-line bus 16. The left-most board is a master control unit 18 co-ordinating data traffic on the bus 16 to the external link 24. In an 25 embodiment, the link can be a 2 Mbit/s or STM-1 type. The remaining boards are referred to as data interface units 20, which provide an interface between Data Terminal Equipment (DTE) and the backplane bus 16, and so to be switched to the link 24.

Each of the data interface units 20 can support various forms of DTE. In one

30 embodiment, the data interface units 20 can provide an interface between the DTE and the

Public Switch Telephone Network (PSTN) under the V.24, V.35, V.36, EIA 530-A or 64 kbit/s G.703 modes. Alternatively, the data interface unit 20 can provide access to a Public Switch Data Network (PSDN) if operating in the X.21 mode.

Where an individual data interface 20 supports more than one DTE, as would be desirable for reasons of minimising space, then the interface units must provide for switching between the multiple DTE inputs to the backplane 16.

Referring now to Fig. 2a, a schematic block diagram of a Data Interface Unit (DIU) is shown. The DIU 20 has two input modules 30, 32, for each of which are provided two interface input channels 40-46 (IF# 1, IF#2, IF#3, IF#4). The input interfaces 40-46 are User Rate (UR) types, typically of a rate up to 2 Mbit/s. The modules 30, 32 can support a variety of interface types such as the ITU V-series, X-series and G.703 types. Each of the input modules 30, 32 is under the control of a proprietary ASIC 50, 52, termed "Agony". The four possible outputs from the input modules 30, 32 have connection with a 4 x 2M bit/s TDM bus 60. The DIU also includes a controlling microprocessor 36 and associated memory 38.

The ASIC 50, 52 is identified by the Nokia Corporation part number K04379072, and interfaces the respective inputs into either one of the respective output buses in thirty-two timeslot form. For example, IF#1 can be mapped to either of TDM 1 or TDM 2. Similarly for IF#2.

The TDM 1 -4 buses are provided as inputs to a logic gate 70, having two output

TDM buses: TDM A and TDM B. The TDM A and TDM B buses are provided to a bus interface ASIC 80 providing for selective cross-connection to the network access node backplane bus 16. The backplane bus has a payload component and a control (HDLC) component.

As shown in Fig. 2b, the gate 70 comprises two AND elements 90, 92 which provide a mapping function for the buses TDM 1 -4 into the bus timeslots of the output buses TDM A and TDM B. Particularly, either or both of TDM 1 and TDM 3 can be mapped into TDM A, while either or both of TDM 2 and TDM 4 can be mapped into TDM B. Fig. 3a shows a single bus timeslot for respective input data, carried by buses TDM 1-4. Fig. 3b shows the mapping, such that IF#1 (TDM 1) is mapped into the timeslots of bus TDM A starting from (i.e. anchored to) timeslot "0", and IF#3 (TDM 2) is mapped into the same bus starting from timeslot "31". In a similar manner, IF#2 is mapped into the timeslots of bus TDM B starting from timeslot "0" and IF#4 (TDM 4) is mapped into the same bus starting from (i.e. anchored to) timeslot "31".

The possibility of collison of the two data streams combined into a single output bus (e.g. TDM 1 and TDM 3 into TDM A) is avoided by embedded software in the memory 38, executed by the microprocessor 36. This software monitors the used/available bandwidth for each channel, obtained from the configuration settings (e.g. speed/bit rate) set by the ASICs 50, 52.

Fig. 4a shows the same single timeslot and related data for IF#1 - IF#4 as in Fig.

3a. In this instance, the AND gate 70 performs a different mapping whereby all of IF#1 - IF#4 are mapped into a single timeslot of either bus TDM A or TDM B. As can be noted, IF#1 is mapped into timeslot "0", and IF#3 is mapped into timeslot "16" extending for its length to the preceeding timeslots. IF#2 is mapped into timeslot "17" and IF#4 is mapped into timeslot "31". Considered against Figs. 3a and 3b, it is apparent that the mapping is arranged so that the thirty-two timeslots of a single output TDM bus are halved.

Fig. 5 shows a flow diagram describing the software configuration of the TDM buses. Firstly (step 100), the default mapping configurations between the interface input channels and the TDM buses, including the starting timeslot are defined. Next, a request is received from the network management system (e.g. the master control unit 18) to reconfigure the interface input channels between the TDM buses. The microprocessor 36 executes the stored code in the memory 38 to calculate the required timeslot configuration (step 102). Next, a check is performed as to whether the adjacent timeslots are available on the given TDM bus (step 104). If so, then the ASIC 50,52 is configured to use the number of available timeslots requested (step 106) and, if not, the network management system is required to command a different configuration. The programing to give effect to this embodiment would be readily apparent to one skilled in the art.

Other advantages arise from embodiments of the invention, including the ability to accommodate modification in the bit rate of any of the interface inputs (i.e. IF#1 -

IF#4) without impacting on any other bit rate that is sharing the TDM bus (i.e. TDM A and TDM B), as long as the available capacity (i.e. 2 M bit/s) is not exceeded. There is additional flexibility in that the interface unit can support 1, 2, 3 or 4 interfaces, dependent upon purpose. If only two input interfaces are utilised on a single input module (e.g. IF# 1 and IF#2) then each can utilise the full ability of the respective TDM channels (i.e. TDM A and TDM B) to their full capacity. Alternatively, one ASIC (50,52) can be configured to broadcast a single interface (e.g. IF#1) to both TDM channels (e.g.

TDM1 and TDM2) to provide redundancy, and thus path protection, in that IF#1 will appear on both TDMA and TDMB buses. In terms of redundancy, the following logic can be executed:

If (signal on TDM1 ok)

{ connect TDM 1 to IF#l } else

{ connect TDM2 to IF#2

}

It will be appreciated by those skilled in the art that the invention can be embodied in many other forms.

Claims

CLAIMS:

1. A method for routing two or more data input streams of a data interface unit, arranged in frames, into one or more data output streams, arranged in frames of the same length, the method comprising the steps of:

(a) mapping a first data block from a frame in a first input stream to the beginning part of a frame in an output stream; and

(b) mapping a second data block from a frame in a second input stream to the end part of the same frame in said output stream.

2. A method as claimed in claim 1, whereby, in step (a), the first data block occupies said beginning part of the frame anchored to and extending from a first timeslot in said frame, and, in step (b), the second data block occupies the end part of the frame anchored to and extending from the last timeslot.

3. A method as claimed in claim 2, comprising the further steps of subdividing said frame in said output stream into integer blocks which define reference points for the allocation of further input stream data blocks.

4. A method as claimed in any of the preceding claims, whereby said mapping steps are performed by the logical AND function of the first and second input streams.

5. A method as claimed in any one of the preceding claims comprising the further step of selectively switching one of two or more data input streams into said first and/or second data streams.

6. A method as claimed in claim 5, comprising the further step of converting said two or more data input channels into frames before said switching step.

7. A method for routing four or more data input streams of a data interface unit, arranged in frames, into two or more data output streams, the method comprising the steps of:

8. A method as claimed in claim 7, whereby the mapping steps into the respective first and second output streams into the respective first and second output stream, are performed by the logical AND function of the respective input streams.

9. A data interface unit for routing two or more data input streams into one or more data output streams, comprising: two interface modules each receiving one or more data input streams and converting each stream into frames; two logical AND elements each receiving two or more input streams from one or both interface modules and mapping a first data block from a frame in a first input stream to the beginning part of a frame in an output stream, and to map a second data block from a frame in a second input stream to the end part of the same frame in said output stream.

10. A data interface unit as claimed in claim 9, further comprising a processor having control over each interface module to selectively switch the data input streams between the AND elements.

11. A data interface unit as claimed in claim 10, further comprising a cross- connect element receiving said output streams and cross-connecting the output streams to an external bus.

12. A network access node comprising: a master control unit; a backplane bus to which the master control unit is connected; and one or more data interface units as claimed in any one of claims 9 to 11 for Data Terminal Equipment (DTE), the output streams of which connect to the backplane bus, and wherein the master control unit controls switching of data traffic between the data interface units.

13. A network access node as claimed in claim 12, further comprising one or more external link connected to the backplane and the master control unit further controls switching of data traffic between the interface units and the external links.