GB2182228A - Signal handling device - Google Patents

Abstract

A signal handling device for use in a digital pulse code modulation data transmission system contains input sections 2, 3 for receiving PGM data streams A, B of the same format, and an output section 4 for sending a PCM data stream C. The device is capable of temporarily storing each of the streams in a RAM 7 and of transferring selected timeslots from either stream into selected timeslots in the output stream. This mapping or translation of the input timeslots is done under the control of an array of binary data stored in a translation memory 10. <IMAGE>

Description

SPECIFICATION Signal handling device The present invention concerns signal handling devices for use in the transmission of data by Pulse Code Modulation (PCM).

Two standard PCM systems are currently in use. One is known astheT1 system and originated in the U.S.A.

It utilises 24 channels and operates at an overall digit-rate of 1544 kbits/s. The other follows the standards laid down by the Conference of European Posts and Telecommunication Administrations (CEPT). Thefollowing specification is directed to equipment operating to the 30-channel PCM standard set by CEPT. However it will be appreciated that the concepts lying behind the present invention are applicable to any type of multi-channel PCM data stream.

A problem arises when information on one or more channels isto be transferred from one PCM data stream to another. This can be achieved by demultiplexing the first stream, extracting the relevant information, transferring the extracted data to another multiplexer and remultiplexing the extracted data to form a second multi-channel PCM data stream.

Such an arrangement is expensive and inflexible.

An objectofthe present invention isto provideequipmentforexchanging information between mult-channel PCM data streams which is relatively flexible and inexpensive.

Accordingly from one aspect the present invention consists in a signal handling device, the device having two input sections for receiving first and second data streams ofthe same format, a main memory into which the frames ofthe data stream are written in sequence, an output section for transmitting an output PCM data stream having the sameformat as the input data streams, and a translate memory storing an array of binary data which maps timeslots from the first and second input data streams onto selected timeslots of the outgoing stream.

Preferably the format of the input and output streams is that laid down by the Conference of European Posts and Telecommunications Administration (CEPT).

In accordance with a feature of the invention the translate memory may be programmable so thatthe translation oftimeslots between the input streams and the output stream can be altered.

In accordance with anotherfeature of the invention each timeslot is written into the main memory during the first halfofthetimeslot, and requested timeslotsare read from the main memory in responsetotimeslot numbers read from the translate memory, each requested timeslot being read during the second half ofthe timeslot.

In accordance with a still furtherfeature ofthe invention,the device may include a control unit, the control unit including a counter which generates a sequence of addresses corresponding to thetimeslots ofthe output stream. This counter will also generate timing signals controlling the timing ofthe reading ofthe input streams into the main memory.

In orderthatthe present invention may be more readily understood an embodimentthereof will now be described by way of example and with reference to the accompanying drawings, in which: Figure 1 shows a standard frame format for a 30-channel PCM system.

Figure2 is a simple schematic diagram of a device according to the invention fortransferring time slots between two PCM data streams, Figure3is a block diagram ofa shift register, Figure4isa blockdiagram of a byteretimer, Figure5isa blockdiagram of a control unit,and Figure 6is a block diagram showing four devices of the kind shown in Figure 2 in a complete information transfer system.

Referring now to Figure 1 of the drawing this shows the frame format of a 30-channel PCM system operating in accordance with the CEPTstandard. A30-channel PCM multiplex system gives digital transmission for30telephony circuits between two locations. To generate the PCM data stream each audio channel (0-4 kHz) is sampled at a rate of8 kHz; that is, every 125 Fs. In each period of 125 Fs is contained an amplitudesamplefrom each ofthe30-channels and this period is known as a 'frame'. Each frame is divided into 32 'time slots' (TSs), and these are designated TS0-TS31; ; the two extra TSs are used to convey frame-alignment and signalling information.Each TS contains 8 binary digits; these binary digits constitute the line signal and occur at a gross digit rate of 2048 kbit/s.

The gross digit rate equalstheframe repetition rate (8000 Hz) multiplied bythe numberofTSs in aframe (32) multiplied by the number of binary digits perTS (8),therefore grossdigitrate = 8000x32x8, = 2048 kbit/s.

The signalling information for all 30 channels is conveyed in TS16which is sub-multiplexed overa period of 16frames (the frames are numbered 0-15) to form a 'multiframe'. During frame 0, a multiframe-alignment signal is transmitted in Tri 6 to identify the start of the multiframe structure. In each of the succeeding frames, the 8 binary digits available are shared by2 channels for signalling purposes. After one multiframe (2 ms), each channel will have been allocated a 4-bit word for signalling. This corresponds to a signalling information rate of 2 kbit/s per channel.

TSO contains a frame-alignment signal which enables the distant terminal to recover the identity of TSs.

The frame-alignment signal (0011011) is transmitted in binary digits 2-8 in alternate frames. In the intermediate frames a signal known as the 'not word' is transmitted; only binary digit 2 of this word is fixed as being a 'one'.

Referring now to Figure 2 of the drawings this shows a device 1 fortransferring information between two data streams, shown respectively at A and B. The device will hereinafter be referred to as a "timeslot translator" and has input sections 2 and 3 for streams A and B respectively. In accordance with Figure 1 each stream consists of 2 Mbits/s data plus clock plus reset all in 30 channel PCM format.For the timeslottranslator 1 to operate it is not necessaryforthetwo input streams to be in byte, frame or multiframe alignment, butthey must be synchronised with the same clock. The timeslottranslator has an output section 4which is ofthe same 30 channel PCM format. The timeslottranslator 1 is capable of placing an individual timeslotfrom either or both of the input streams into any selected timeslot ofthe output stream C. To avoid more than one word perframe appearing in the outgoing stream, all translation of TimeslotO give "All Ones"-A1S code- inthe outgoing timeslot.This is donesimilarlyforTimeslot 16, Multiframe 0.

There will be some delay in data passing through thetimeslottranslator. This will be a maximum of one frame (125 pwsec) for any 8-bit voice or data timeslot. The degree of delay will depend on: 1) the translation applied for, for example TS1 +31 orTS17+TS19orTS31 41.

2) The actual alignment of the two incoming streams. Timeslot 16 bits are subject to a multiframe delay, but this is minimal comparedto 2 millisecsignalling delays.

Each ofthe input sections 2 and 3 ofthe timeslottranslator includes a shift registerS which acts as a bit staticiserto convert the serial 30-channel data into 8-bit pa parallel data and an associated 9-bit address. Figure3 of the accompanying drawings shows atypical shift register arrangement. In this Figure serial data is input at 200to one input of a chain offlip-flops 201, whilst a clock signal is supplied at 202. Thus each incomping timeslot has an 8-bit data byte plus its address. Each input section also includes a bit retimer 6 which retimes the data and address from each timeslotto synchronise it with the bytetiming of the outgoing stream C.

Figure 4 shows a byte retimer. The 8 parallel data streams are indicated at D to D7. Each stream is supplied to one input of a flip-flop 210-217 the clock inputs of which are supplied with a clock signal at219 in synchronism with the outgoing stream.

Each timeslot data byte and address is written into a RAM main memory 7 during the first half ofthe timeslot by a data and address multiplexer block 8. The outgoing stream C is created by using a counter in a control unit 9 to interrogate a translate memory 10 holding a binary array of data which can be considered as a "map" setting outwhich timeslotfrom which of in put strea ms A and B isto be placed into a particulartimeslot in stream C.

Figure 5 ofthe drawings shows the control unit9 in greater detail. Thus control unit9 comprises a divider chain 300 clocked bya 2048 Khzsignal supplied at 301. Each step of the chain 300 divides the signal supplied to it by 2so that the chain provides, as shown in the drawing, a series of outputs at 1024,512,256, 128,64,32, 16,8,4,2, 1,0.5Khz respectively. These signals are supplied to gating and control logic circuits 302.

The translate memory 10 is interrogated via a translate block 11. The translate memory 10 and the main memory 7 can be any suitable fast access RAM memory which is 8 bits wide and has at least 32 bytes capacity.

When the nexttimeslot number is retrieved from the translate memory 10 a comparison is done in translate block 11 to establish from which frame the timeslot is to be read. This results in an address outto the main memory 7 so that the requested timeslot can be read out. It will be remembered thatthetimeslot data and address was written in the main memory during thefirst half ofthetimeslot. The requested timeslot is read out during the second half.

The data from the main memory 7 is latched in a memory output latch 12 and read out serially at2 megabits/sectoform stream C.

When a timeslot has been requested arithmetic has to be done to ensure the timeslot requested istaken from the correctframe number. There are two types of arithmetic being done on frame numbers, namely ordinary voice timeslots, and Timeslot 1 6timeslots.

Firstly considering the case where the requested timeslot is from the A stream and is an ordinary voice timeslot. In this case the number ofthe requested timeslot is read from the translate memory 10 from the control unit9 and translate block 11. If the incoming Atimeslotwhich hasjust been written in the main memory 7 is greater than the timeslot C is requesting, after translation, then the current A frame number can be used to retrieve the timeslot, as it is fresh information, having just been updated.

If theAtimeslot number equals the requested translated timeslot numberthesame applies, asA iswritten before C is read out in any one timeslot.

lftheAtimeslot numberwhich has just been written is less than the translated timeslot being requested, the information in the currentframe is old, coming from the last multiframe. The last update of this particular timeslotwas in the previous frame of A. Hence in translator block 11 one issubtractedfromthecurrentA frame number and the timeslot accessed is in the previous frame. The subtraction is done by adding all ones totheAframe number.

In the case of Timeslot 16, Timeslot 16 of C is detected and is used to switch the address to the translate memory 10 from the timeslot numberto the frame number, plus the clock rate which represents the front and backofthetimeslot. Thusforexample, say timeslot 4 of C requests timeslot 26 of B. In avoicetimeslot address 4 gets address 26 i.e. 1 from the translate memory 28.

In timeslot 16 offrame4the signalling belonging to timeslot 26 in B is requested. In this casethenumber presented to thetranslate memory 28 is 00100, i.e. frame 4front, address out is 11010 i.e. MSB = 1 frame number is 10 signifying rearof TS16 of frame 10 which is where TS26's signalling is carried. Hence signalling translations produce an absolute frame number and this is used.

Figure 2 also shows the main busses along which information is transferred in the device. Thus all busses marked AD carry the 9-bit addresses associated with each timeslot and all busses marked DB carrythe8-bit data. The control unit 9 sends timing signals to all of the other blocks in the diagram and to reduce complication in the drawing the outputtiming signals from control unit9 have been represented simply bya single bus TM. Again forthe sake of simplicity none ofthe input timing signals to the various blocks have been shown.

Whilstthetimeslottranslator has been shown as a series of circuit blocks, it will be appreciated that a practical embodiment is likely to be a Very Large Scale Integrated Circuit (VSLI).

Referring nowto Figure 6 of the drawings it can be seen that the system comprises fourtimeslottranslators 101,102,103 and 104 arranged to provide a "diamond" switching configuration between 30-channel PCM data streams 15,16,17 and 18. Lines 15 and 16 are forsignalstravelling in the X direction and 17 and 18for signals in the Y direction. The lines extend between four common cards having respective receive sections 19, 20andtransmitsections 21 and 22 for lines 15 and 16, and receive sections 23, 24andtransmit sections 25, 26 for lines 17 and 18. The common cards themselves provide the interface between the system being described and two bi-directional channels forming part of a much larger PCM data transmission network.

The operation of one of thetimeslottranslators within the system will now be described with the understanding that the othertimeslottranslators will operate in an identical manner with respect to their associated input and output data streams.

Accordinglytimeslottranslator 101 will be considered. This timeslottranslatortakes its two inputstreams A and B from lines 16 and 18 respectively and sends its output stream C into the transmit section 25. Atthe transmit section 25 the output stream C can either be merged with a data stream ahead travelling in direction Yfrom receive section 23, or stream C itself be the output from section 25.

The translate memory of the timeslot translator 11, along with those of the othertimeslottranslators, are controlled from a translation control card 29 acting through an address bus 30, a data bus 31 and a control bus 32. The fourtimeslottranslators are all provided with battery back-up as indicated at33 in casethereshould be interruption ofthe main power supply.

The timeslottranslatorwhich has been described with reference to the drawings can be used in a number of additional ways. Thus it can be used as a crossoverfortwo PCM data streams. It can also be used as part of an adaptive differential PCM bypass and alignment system.

Other potential uses of thetimeslottranslator are as a 60-channel - 30-channel concentrator, as a timeslot loopbacktest system and as a drop-and-insert system. In the latter case, for example, the input data stream to receive section 20 is replaced by 30 channels as indicated by the block 40.

The main advantage oftimeslot translators ofthe kind described with reference to the accompanying drawings is the flexibility they afford to the operator. The fact that the required translations are stored in a memory means that the total set oftranslations in that memory can be easily altered, for example, from a keyboard.

Claims (8)

1. A signal handling device for use in a digital Pulse Code Modulation (PCM) data transmission system, the device comprising a first input section for receiving a first PCM data stream the format of which consists of sequential framewords each including a plurality oftimeslots overwhich multiplexed data channels are distributed, a second input section for receiving a second PCM data stream of the same format as said first data stream, an output section fortransmitting an output PCM data stream having the same format as the two input data streams, and atranslate memory storing an array of binary data which is operative to map timeslotsfrom said first and second input data streams onto selectedtimeslots of said outgoing stream.

2. Asignal handling device as claimed in Claim 1,wherein the translate memory is a programmable memory so that the translation timeslots between said input streams and said output stream can be altered.

3. Asignal handling device as claimed in Claim 2, wherein each ofthefirstand second input sections includes: a shift registerwhich acts as a bit staticiserto convert the respective serial input stream into parallel data and an associated address, and a bit retimerfor retiming the data and address of each received timeslot into synchronism with the byte timing of the outgoing data stream.

4. Asignal handling device as claimed in anyoneofthe preceding claims and further including: a main memory, a data and address multiplexer blockforwriting into said main memory during the first half of a timeslot each timeslot data byte, and a control unit for interrogating said translate memory and reading from said main memory the appropriate timeslot byte as selected by the translate memoryfortransmission to said output section.

5. Asignal handling device as claimed in Claim 4and further including atranslate blockcircuitfor interrogating the translate memory and for determining from which frame a requested timeslot is to be read.

6. A signal handling arrangement for use in a PCM data transmission system, the arrangement comprising four signal handling devices each as claimed in any one of Claims 1 to 5 and operatively associated in a diamond formation with a pair of two-way PCM data channels, the arrangement being such thatanytimeslot in any one ofthe four PCM data channels can be transferred to any one of the other PCM data channels.

7. A signal handling device substantially as hereinbefore described with reference to Figures 1 to 5 ofthe accompanying drawings.

8. Asignal handling device substantially as hereinbefore described with referenceto Figure 6 ofthe accompanying drawings.