WO1997027593A1

WO1997027593A1 - Stacked memory module substrate and system for accessing the substrate

Info

Publication number: WO1997027593A1
Application number: PCT/JP1997/000101
Authority: WO
Inventors: Ritsuro Orihashi; Kosuke Kendo
Original assignee: Hitachi, Ltd.
Priority date: 1996-01-24
Filing date: 1997-01-20
Publication date: 1997-07-31
Also published as: JPH09265774A

Abstract

A system for accessing a stacked memory module can write/erase data at a high speed in/on memory modules mounted on a substrate. In the stacked memory modules write access or erase access to each memory chip is made by interleave control between the memory modules or between the memory chips in the memory modules.

Description

Specification

Stacked memory module substrate and access method to the substrate

The present invention relates to an access method for a plurality of stacked memory modules, and a stacked memory module substrate on which a plurality of stacked memory modules are mounted. Background art

The stacked memory module in which a plurality of the stacked memory modules are mounted has an extremely large storage capacity, as known in Japanese Patent Application Laid-Open No. Hei 11-309362. However, for example, if writing is performed normally with a 16 b bus width on a stacked memory module substrate with a memory capacity of 800 MB class, It took a very long time, about 30 minutes or more.

In the above prior art, no consideration has been given to writing at high speed to a stacked memory module in which a plurality of stacked memory modules are mounted.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the prior art, and to provide a stacked memory module capable of high-speed writing or erasing on a stacked memory module board on which a plurality of stacked memory modules are mounted. An object of the present invention is to provide a re-module access method.

Another object of the present invention is to reduce the concentration of heat generated by a module on a stacked memory module substrate on which a plurality of stacked memory modules are mounted. It is an object of the present invention to provide an access method for a stacked memory module in which writing or erasing can be performed at a high speed with ease.

Another object of the present invention is to provide a stacked memory module board on which a plurality of stacked memory modules are mounted, so that the concentration of heat generated in the module can be reduced and writing or erasing can be performed at high speed. An object of the present invention is to provide a memory module substrate. Disclosure of the invention

In order to achieve the above object, the present invention provides an interleave control between the stacked memory modules or between memory chips in the stacked memory module in a stacked memory module board on which a plurality of stacked memory modules are mounted. This is an access method for a stacked memory module, characterized in that write access or erase access is performed on a memory chip.

Also, the present invention provides a method for writing to each memory chip by interleaving control between the above-mentioned stacked memory modules or between memory chips in the stacked memory module in a stacked memory module board on which a plurality of stacked memory modules are mounted. This is an access method to a stacked memory module substrate, which suppresses an increase in heat generation in a module by performing access or erase access.

The present invention is also characterized in that in the above-mentioned access method to the stacked memory module substrate, the stacked memory module is a stacked flash memory module.

The present invention also provides a stacked memory module substrate on which a plurality of stacked memory modules are mounted, wherein Is an interleaved control circuit for performing interleave control between memory chips in the stacked memory module to perform write access or erase access to each memory chip. .

As described above, according to the present invention, a stacked memory module substrate having a three-dimensional mounting structure realizing a large-capacity memory can be accessed at high speed without damaging the module due to concentrated heat generation. For example, a 32 Mb memory chip, 8 layers, and 26 modules can provide a memory capacity of 800 Mb. When accessing the series to this stacked memory module, it takes about 44 minutes to write with a 16 b bus width, but it can be written in less than 100 seconds by interleave control. Become. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a configuration diagram showing an embodiment of a stacked memory module according to the present invention, in which (a) is a plan view and (b) is a front view. FIG. 2 is a perspective view showing a stacked memory module board configuration in which a plurality of stacked memory modules according to the present invention are arranged and mounted on one mother board. FIG. 3 is a diagram showing one embodiment of a flash memory chip according to the present invention. FIG. 4 is a diagram showing a write operation mode for a flash memory chip according to the present invention. FIG. 5 is a diagram showing an erase operation mode for the flash memory chip according to the present invention. FIG. 6 is a diagram showing a write operation mode based on the interleave control for the flash three memory chip according to the present invention. FIG. 7 is a diagram showing a circuit configuration of a stacked memory module substrate according to the present invention. FIG. 8 shows an address bus signal input to the read Z-write control circuit shown in FIG. It is a figure which shows the number structure (data structure) of a signal (ADP). FIG. 9 is an expanded view of a configuration of six stacked memory module substrates when W = 3, S = 2, and H = 4. FIGS. 10A and 10B are diagrams showing a part ahead of control in the laminated memory module board configuration according to the present invention, wherein FIG. 10A shows a case of non-interleave, and FIG. (C) is a diagram showing the case of interleave control between modules. FIGS. 11A and 11B are diagrams showing an intermediate part of the control in the stacked memory module board configuration according to the present invention, which is subsequent to FIG. 10; FIG. 11A shows a case of non-interleaving, and FIG. FIG. 7C shows a case of control, and FIG. 7C shows a case of interleave control between modules. FIG. 12 is a diagram showing a portion following the control of FIG. 11 in the stacked memory module substrate configuration according to the present invention, where (a) shows a case of non-interleaving, and (b) shows inter-module interleaving control. (C) is a diagram showing a case of interleave control between modules. FIG. 13 is a diagram showing a write operation mode based on interleave control for a flash memory chip according to the present invention. FIG. 14 is a diagram showing a circuit configuration of a stacked memory module substrate according to the present invention. BEST MODE FOR CARRYING OUT THE INVENTION

An embodiment according to the present invention will be described with reference to the drawings.

First, FIG. 1 is a diagram showing a stacked memory module mounted on a substrate in a plurality, (a) is a plan view, and (b) is a front view. FIG. 2 is a perspective view showing a case where the stacked memory modules are mounted on a mother board in a row: W direction and a column: S direction. That is, the stacked memory module 1 is, for example, a film-shaped base connected to the outer lead 2. It is formed by stacking boards 3 on which memory chips 4 are mounted (for example, the number of layers H = 8). That is, in the module as a whole, the chip select CS is provided independently for the number of layers (in this case, for example, 8), and the other pins have a common pin arrangement of eight layers. The stacked memory module 1 is mounted on a motherboard 21 with the stacked memory modules 1 arranged in rows: W direction and columns: S direction. Then, the read / write control circuit 22 provided on the motherboard 21 is connected to each memory chip 4 of each stacked memory module 1 via the outer leads 2.

FIG. 3 shows a single flash memory chip 4a. As shown in Fig. 3, the flash memory chip 4a has an AD (address designation) terminal, DT (data input / output) terminal, OE (output enable) terminal, WE (write enable) terminal, and CS (chip Select) and VPP (voltage application) terminals are provided. Then, in the flash memory chip 4a, a high voltage is applied from the VPP terminal during the write operation.

FIG. 4 shows a write operation mode for the flash memory chip 4a. AD, DT, CS, WE, and OE indicate signals input / output to / from each terminal in each cycle (TE, TS). The write operation mode for the flash memory chip 4a includes the command cycle TC (100 to 200 ns as a typical numerical example), the write execution cycle TE (1 to 6 zs as a typical numerical example), and the confirm cycle TS. (100 ns as a typical numerical example). Fig. 5 shows the erase operation mode for the flash memory chip. AD, DT, CS, WE, and OE indicate signals input to and output from each terminal of each cycle (TC, TE, TS). The erase operation mode for the flash memory chip 4a is also It consists of an erase execution cycle and a confirm cycle. In the above description, the confirm cycle is a cycle in which the status signal from the memory chip is read to check whether data has been written or erased, and the type of the memory chip to be used or the method of use. This is a cycle that is omitted for some.

Next, a write operation mode based on interleave control for a plurality of flash memory chips 4a according to the present invention will be described with reference to FIG. However, the case where the number of interleaves = 2 is shown. First, a command cycle is issued to the memory chip 1. Memory chip 1 determines the contents of the command cycle and enters the write execution cycle. Issue a command cycle to memory chip 2 while memory chip 1 is performing a write execution cycle. Memory chip 2 determines the contents of the command cycle and issues a confirm cycle to memory chip 1 during the write execution cycle. When the confirm cycle of memory chip 1 is completed, a confirm cycle is issued to memory chip 2. That is, by performing interleave control (simultaneous parallel access) in which the write operation mode for the memory chip 1 is shifted from the write operation mode for the memory chip 2 by, for example, a write execution cycle, the write time can be shortened. In particular, since heat is generated in the write execution cycle TE in the memory chip, the memory chip 1 and the memory chip 2 are temporarily adjacent to each other, for example, by performing an in-leave control shifted for the write execution cycle. However, it is possible to prevent the heat generation in the module from being increased and to enhance the heat radiation effect to prevent the memory chip from malfunctioning. Furthermore, if cooling fins are attached to each stacked memory module 1 to enhance the cooling effect, It is possible to increase the number of memory chips for performing the write execution cycle. In particular, in order to suppress the concentration of heat generation in the module, it is desirable to perform interleave control between the memory chips between the modules. This is because heat generation is reduced at the end of the write execution cycle TE in the _c memory chip. O ₀

FIG. 7 shows an example of a signal connection relationship between the read / write control circuit 22 and each memory chip 4 of each stacked memory module 1. However, the case where W = 3, S = 2, H = 4 is shown. In the read / write control circuit 22, the ADP terminal is connected to the address signal bus (A

DP) is input, a 16-bit data bus signal (DTP) is input / output to the DTP terminal, a read / write signal is input to the RZW terminal, and a clock signal is input to the CK terminal. The address bus signal (ADP) shown in Fig. 8 consists of the side ID number, module number, chip number, and byte between the most significant bit (MSB) and the least significant bit (LSB). It consists of a number, and is indicated by the number of chip bytes: P = 2 to the power of Q. The side ID is a signal for identifying a plurality of memory modules by grouping them into, for example, those on the front side and those on the back side of the motherboard.

The AD (address) signal from the read / write control circuit 22 is an output signal, which is transmitted to the AD terminal of the memory chip of each module, and the DT (16-bit data) 'signal is the DT of the memory chip of each module. The OE (output enable: 0 output enable) signal is transmitted to and received from the OE terminal of the memory chip of each module, and the WE (write enable: W rite Έ nable) signal is output to each module. The CS (chip select) signal (CS1 to CS24) is sent to the CS1 to CS4 (when H = 4) terminals of each module's memory chip. Is done.

FIG. 9 is an expanded view of the configuration of six stacked memory module substrates when W-3, S = 2, and H = 4.

This is the case of 8. FIGS. 10, 11, and 12 show the control of the configuration of the six stacked memory module substrates shown in FIG. 9 on a time basis, and (a) shows the non-interleaved (B) shows the case of inter-module interleave control, and (c) shows the case of inter-module interleave control. In FIGS. 10, 11, and 12, T = 1 to P, but in FIG. 9, it is indicated as P-8.

If non-interleaved as shown in Fig. 10 (a), Fig. 11 (a) and Fig. 12 (a), for example, 840MB memory capacity by 32Mb memory chip, 8 layers, 26 modules It takes about 44 minutes to access a large number of stacked memory module substrate configurations and write with a 16 b bus width. However, as shown in FIGS. 10 (b), 11 (b) and 12 (b), and FIGS. 10 (c) and 11 (c) and 12 (c), With interleave control, for example, 32Mb memory chip,

When accessing a stacked memory module board configuration with 840 MB memory capacity using 8 layers and 26 modules and writing with a 16 b bus width, the memory chip is concentrated by heat generation in about 60 seconds, less than about 100 seconds. It can be performed without damage.

As shown in FIGS. 10 (b), 11 (b) and 12 (b), an interleave system between layers in each stacked memory module 1 is used. As shown in FIGS. 10 (c), 11 (c) and 12 (c), the interleave control between the stacked memory modules 1 generates more heat in the stacked memory modules than the control. It is desirable because you do not concentrate. For convenience of explanation, in the case of interleaving in the stacked memory module, the access order of the chips in the module is H = 1 → 2 → 3 → 4 in Fig. 10 (b) and Fig. 11 (b). However, the access order can be arbitrarily changed, such as H = 1 → 4 → 2-3, depending on the type of module used and the characteristics of the memory chip. Also, in the case of interleaving between stacked memory modules, (W, S) = (1,) in FIGS. 10 (c), 11 (c) and 12 (c).

1)-→ (2, 1) → (1, 2) → (2, 2) force, ', for example (W, S) = (2, 1) — (2, 2) → (1, 1)-→ (1,

As in 2), the access order can be changed arbitrarily.

In particular, if cooling fins are attached to each stacked memory module 1 to improve heat dissipation efficiency, as shown in FIG. 10 (b) and FIG. 11 (b), Even in the interleave control between layers, writing or erasing in a very short time of 100 seconds or less can be performed on a stacked memory module substrate configuration having a large memory capacity of, for example, 800 MB without damaging the memory chip. Erase) can be executed.

Next, another embodiment of the write operation mode based on the interleave control for the plurality of flash memory chips 4a according to the present invention will be described with reference to FIG. The command cycle consists of two patterns, but since pattern 1 represents the type of command such as read / write, the data to be input to the memory chip to be interleaved is input.

—The data are all the same. Therefore, pattern 1 is interleaved By simultaneously inputting the data to the memory chip and inputting the pattern 2 and subsequent ones successively in the order of accessing the memory chips as in FIG. 6, the number of interleaves can be further increased and the access time can be shortened.

FIG. 14 shows an example of a circuit configuration for realizing the write operation based on the interleave control shown in FIG. However, the number of interleaves minus 4 and the number of memory chips minus 16 are shown. The address decoder 31 selects the memory block to be interleaved, and the address decoder 32 selects the memory chip to access, but performs the decoding function only when the EN signal is valid (logical value H in this circuit example). . The command flag CF is a signal that outputs a logical value H when the pattern 1 of the command cycle described in FIG. 13 is generated. First, the address decoder 31 enables only EN of the address decode 32 connected to the memory block to be interleaved. The selected address decoder 32 selects the memory chip 4 to be accessed according to the input address value. Therefore, commands are written to all memory chips of the interleaving block. After pattern 2 of the command cycle, the write operation shown in FIG. 13 is realized by setting the logical value of the command flag CF to L and accessing the memory chip 4 individually. Note that the present embodiment can deal with any number of interleaves and memory chips. Also, since there is no restriction on the access order of the memory chips, interleaving between the memory modules can be realized, so that it is possible to cope with a heat generation concentration measure when the memories are stacked.

The write operation mode of the memory has been described above. In the operation mode, high-speed erasing is possible by changing the command value and data value in the write operation mode.

In the above embodiment, the laminated memory module substrate configuration including the flash memory has been described. However, the present invention can be applied to SRAM and DRAM.

As for the read operation, the data may be read in the order of writing. Industrial applicability

As described above, according to the present invention, for a stacked memory module substrate configuration having a large memory capacity of, for example, 800 MB, the memory chip or the module is not damaged for 100 seconds or less without damaging the module. Writes or erases in a very short time. Further, according to the present invention, it is possible to execute writing or erasing (erasing) in a very short time of 100 seconds or less without damaging a memory chip or a module. An excellent effect can be exhibited with respect to the stacked memory module substrate configuration composed of.

Claims

The scope of the claims

1. Each memory chip is controlled by interleaving control between the above-mentioned stacked memory modules or between the memory chips in the stacked memory modules on the stacked memory module substrate on which a plurality of stacked memory modules are mounted. An access type to the stacked memory module substrate, which performs write access or erase access to the board.

2. Each memory chip is controlled by the interleaving control between the above-mentioned stacked memory modules on the stacked memory module substrate on which a plurality of stacked memory modules are mounted or between the memory chips in the stacked memory module. An access method to a stacked memory module substrate, wherein write access or erase access is performed to suppress concentration of accesses to a specific module.

3. The method for accessing a stacked memory module substrate according to claim 1, wherein the stacked memory module is a stacked flash memory module.

4. In a stacked memory module substrate on which a plurality of stacked memory modules are mounted, an interleave control is performed between the stacked memory modules or between the memory chips in the stacked memory module to control each memory chip. A stacked memory module substrate comprising an interleave control circuit for performing write access or erase access.

5. An interleave control method characterized by speeding up write access or erase access to each memory chip by continuously writing command cycles to the memory chips.

6. Write command or erase command is simultaneously written to all memory chips in the memory block that performs the interleave, and write address and write data at the time of writing or erase data at the time of erase are successively written to the memory chip. An interleave control method characterized by speeding up write access and erase access to a memory chip.

7. Equipped with an address decoder for selecting a memory block to be interleaved, an address decoder for selecting a memory chip, and a command flag signal. The command flag signal is used to access a single memory chip or memory in an interleaved memory block. 7. An interleave control circuit according to claim 6, wherein the interleave control is performed by switching to all chips.