JPH05120890A - Information medium - Google Patents

Abstract

PURPOSE:To realize an information medium where data is written at a speed higher than conventional regardless of the use of a flash memory which takes a long time to write. CONSTITUTION:Plural flash memory ICs 1 to 4 are provided, and a decoder 5 receives lover bits A0 and A1 of an address signal through terminals 100 and 101 and decodes them and selects a flash memory IC to change addressing. Thus, parallel processing is possible even when the information medium is accessed in the order of address, and data is written at a high speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information medium, and more particularly to an information medium having a flash memory (that is, a programmable ROM capable of electrically erasing all at once).

[0002]

2. Description of the Related Art Conventionally, as information media, from the viewpoint of shape, there are IC cards in the form of rectangular plates, IC coins in the form of circular plates, etc., and from the viewpoint of memory and processing capacity. , ROM cards, memory cards, IC cards, etc., and there are contact type and non-contact type from the viewpoint of the connection state at the time of insertion into the input / output device. Here, since the present invention relates to an information medium including a flash memory, in order to simplify the description, avoid a non-contact type or an IC card that also has a complicated function such as communication or data processing, Taking a contact type memory card as a specific example, a conventional technique will be described with reference to FIG. FIG. 3 shows a plurality (4 in this example).
It is a block diagram which shows the structure of the memory card 8 provided with each flash memory IC1-4. Memory card 8
In addition, the decoder 5 and terminals 100 to 118 for address signals A0 to A18 and terminals 20 for data signals D0 to D7.
0-207, control signal terminals 300-333 (300-
333 does not have to be a serial number).

Each of the flash memories IC1 to IC4 has a capacity of 8 × 128 K bits (that is, 8 bits / 1).
128 K words of memory capacity), terminal 1
The signal A consisting of the address signals A0 to A16 via 00 to 116 is received as the address input. The data signals D0 to D7 via the terminals 200 to 207
A signal D consisting of
Output as the data output. Furthermore, terminals 300-
A control signal C is also received from an external input / output device (not shown) via 333. The decoder 5 has terminals 117 and 118.
A signal AH 'consisting of address signals A17-A18 and a control signal C are received, and the signal AH' is decoded to generate any one of the selection signals CS1-CS4 to the flash memories IC1-4. , The selection signal is output at a timing corresponding to the control signal C.

In the memory card 8 having such a structure, when it is inserted into the input / output device and receives the control signal C and the address signals A0 to A18, the address indicated by the address signals A0 to A18 is 00000 (H). In the case of 1FFFF (H), the flash memory IC1 is selected by the selection signal CS1 from the decoder 5, and the flash memory IC1 is selected.
One word in the address 1 indicated by the signal A is selected, and the data indicated by the data signal D is written into the selected word at a timing corresponding to the control signal C, or the selected word is selected. Access such as reading the word data as the data signal D is performed. Here, “(H)” in the notation of the address value indicates hexadecimal notation.

When the address indicated by the address signals A0 to A18 is 20000 (H) to 3FFFF (H), similarly, one word in the flash memory IC2 is selected by the selection signal CS2 and the signal AH '. Access to this word is made. When the address indicated by the address signals A0 to A18 is 40000 (H) to 5FFFF (H), one word in the flash memory IC3 is selected, and when the address is 60000 (H) to 7FFFF (H), Similarly, one word in the flash memory IC4 is selected and the word is accessed.

Therefore, the addresses are arranged in such a manner that the start address of the flash memory IC1 is 0, as in the addresses written in the blocks of the flash memory of FIG.
0000 (H) address, next address is 00001 (H)
The address and the final address of the flash memory IC1 become the address 1FFFF (H). This is followed by the flash memory IC2, the start address of the flash memory IC2 is 20,000 (H), and the next address is 200.
The address 01 (H) and the final address of the flash memory IC2 become the address 3FFFF (H). Similarly, the start address of the flash memory IC3 is 4000
The address 0 (H) and the final address are addresses 5FFFF (H), and the start address of the flash memory IC4 is 600.
The 00 (H) address and the final address are 7FFFF (H) addresses.

[0007]

The flash memory is
Since this is a large-capacity ROM that can be electrically erased and rewritten, if it is applied to an information medium, access from an input / output device or the like is relatively easy, and a memory storage Since it is possible to realize an information medium that has various advantages such as no need for batteries and large storage capacity,
It is being adopted as a storage element of an information medium. Although the flash memory has such an advantage, the writing procedure to the flash memory is usually to perform the following steps 1 to 5 for each word.

Step 1, First, a write setup command is placed on the data signals D0 to D7 and is controlled by the control signal C to be sent to the memory card 8 (send write setup command), and then the address to be written is addressed to the address signals A0 to. Put the write data on A18 and write the data signal D0 ~
It is placed on D7 and is controlled by the control signal C and sent to the memory card 8 (write program command sending). Each flash memory of this example has a built-in circuit that decodes the data signals D0 to D7 as commands according to the timing. (Time required: 0.1 to 0.3 μs) Step 2, Wait time of 10 to 20 μs. Step 3, the write program verify command is placed on the data signals D0 to D7, controlled by the control signal C, and transmitted to the memory card 8 (write program verify command transmission). Since each flash memory in this example has an address latch built therein, it is not necessary to retransmit the write target address at this timing. (Time required: 0.1 to 0.3 μs) Step 4, Wait time of 5 to 10 μs. Step 5, comparing the data on the data signals D0 to D7 output from the memory card 8 with the write data,
Check if the data was written correctly.

Of these procedures, steps 1, 3,
The required time of 5 is 0.1 to 0.3 μs, while the step 2 is 10 to 20 μs and the step 4 is 5 to 1 μs.
Since it takes 0 μs, the writing time of the flash memory is about 15 to 30 μs, but most of it is the waiting time in step 2 and step 3. Also,
Since the flash memory is a batch erase type, all or block units (for example, 1K word units) are erased collectively at the time of erasing performed before rewriting. Therefore, rewriting is often performed collectively correspondingly. Therefore, when a flash memory is used, it is particularly often that successive writing is performed in the ascending order and the descending order of the addresses of the memory.

However, if the addresses are accessed in order,
Since the addresses are assigned as described above in the conventional configuration, the same flash memory IC is used in most cases.
However, since a long waiting time of about 15 to 30 μs per word is required, if all 512 K words (bytes in this example) in the example of FIG. 3 are written, it takes 7 to 16 seconds. You will need it. This is about 100 times as compared with the case where the SRAM of the same capacity is adopted, and it exceeds the 2-3 seconds that human beings can wait without being frustrated.
Not preferable. An object of the present invention is to solve the above-mentioned problems of the prior art, and to realize an information medium capable of writing data at a higher speed than before while adopting a flash memory which requires a long time for writing. To do.

[0011]

An information medium according to the present invention which achieves the above object comprises a plurality of flash memory ICs, and a flash memory IC of the flash memory IC is generated by decoding a lower bit of an address signal. Either one
Selecting one of them, and selecting one word in the selected flash memory IC by the upper bits remaining after removing the lower bit from the address signal to access the selected word. Is.

More specifically, the flash memory IC to be accessed in word units receives a power of 2 and an address signal and a control signal, and has a bit number corresponding to the lower power number of the address signal. And a decoder that outputs a selection signal to any one of the flash memory ICs at a timing according to the control signal, the flash memory IC removing the lower bit from the address signal. The remaining upper bits are received at the address input to select one word in the flash memory IC that has received the selection signal, receive the control signal, and select the word at a timing according to the control signal. It is the one that provides access to the specified word.

[0013]

In the information medium of the present invention having such a configuration, the lower bits of the address signal are decoded,
The corresponding flash memory IC is selected, and the flash memory I is selected by the remaining upper bits of the address signal.
Since the address in C is selected, the address allocation is different from the conventional one. That is, when the value of the lower bit of the address signal changes and the address indicated by the address signal continuously changes in order, consecutive words in the same flash memory IC are not continuously selected as in the conventional case. , Different flash memory ICs are sequentially selected.
Then, until the flash memory IC completes one cycle, the local address in each flash memory IC becomes the same.

Therefore, even if data is sequentially written to consecutive addresses on the information medium, different flash memory ICs are sequentially accessed inside the information medium. Therefore, the previous access is completed until the flash memory IC completes one cycle. You don't have to wait. As a result, the time required for writing is
Compared to the mere total sum of conventional required time, (1 / number of flash memory ICs) or (actual access time / wait time)
It is shortened to the extent. This is not equivalent to SRAM etc., but within the time that humans can wait without being impatient,
It is settled enough.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A memory card as an embodiment of an information medium having the structure of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows four flash memory ICs 1 to
4 is a block diagram showing a configuration of a memory card 9 including the memory card 4, and corresponds to FIG. 3 of a conventional example. The memory card 9 has the decoder 5 and terminals 100 to 118 for address signals A0 to A18, terminals 200 to 207 for data signals D0 to D7, and terminals 300 to 333 for control signals, but they are redundant and complicated. To avoid explanation, the same configuration,
Similar configurations are denoted by the same reference numerals, and description thereof will be omitted.

The configuration different from the conventional one is the flash memory I.
C1 to 4 receive the signal AH consisting of the address signals A2 to A18 via the terminals 102 to 118 as its address input, and that the decoder 5 determines that the terminals 100, 1
Signal AL consisting of address signals A0 and A1 via 01
And control signal C.

In the memory card 9 having such a structure, when it is inserted into the input / output device and receives the control signal C and the address signals A0 to A18, the address indicated by the address signals A0 to A18 changes to 0000 (H ), 00004 (H), 0
0008 (H), ~ 7FFFC (H) (however, 4 jumps)
In this case, the flash memory IC1 is selected by the selection signal CS1 from the decoder 5 and one word at the address indicated by the signal AH is selected in the flash memory IC1 at the timing corresponding to the control signal C. , The data indicated by the data signal D is written to the selected word, and the data of the selected word is read as the data signal D.

The addresses indicated by the address signals A0 to A18 are 00001 (H), 00005 (H), 00009.
In the case of (H), ~ 7FFFD (H) (however, 4 jumps), similarly, one word in the flash memory IC2 is selected by the selection signal CS2 and the signal AH, and this word is accessed. Be seen. Address signals A0 to A18
The address indicated by is 00002 (H), 00006
(H), 0000A (H), to 7FFFE (H) (however, 4 jumps), one word in the flash memory IC3 is selected, and the address is 00003 (H),
00007 (H), 0000B (H), ~ 7FFFF
In the case of (H) (however, four jumps), one word in the flash memory IC4 is selected, and this word is similarly accessed.

Therefore, the arrangement of the addresses in the entire memory card 9 is such that the start address of the flash memory IC1 is the address 00000 (H) and the start of the flash memory IC2 is the same as the address written in the block of the flash memory in FIG. Address is 00001 (H)
Address, start address of flash memory IC3 is 000
02 (H), the start address of the flash memory IC4 is 00003 (H), and the second address of the flash memory IC1 is 00004 (H). Similarly, addresses are sequentially allocated to the flash memory IC, and finally, the final address of the flash memory IC1 is 7FFFC (H), the final address of the flash memory IC2 is 7FFFD (H), and the final address of the flash memory IC3. Is 7FFFE (H)
Address, last address of flash memory IC4 is 7FF
The address is FF (H).

How to write to the memory card 9 based on the arrangement of addresses will be described with reference to the timing chart of FIG. 2. Step 1 in the 1-word write procedure ~ The detailed description of step 5 is the same as that of the conventional example, and therefore its description will be omitted. Then, in order to make the explanation clear, a case where the memory card 9 is accessed in the order of the addresses of the entire memory card 9, and further, an access is made from an address which is a multiple of 4 will be described as a specific example. ..

First, the write setup command and write program command of step 1 are sent to the flash memory IC1 (W1), and the waiting time of step 2 is taken (WW1). Next, in the conventional case, the process proceeds to step 3 after completion of step 2, but in the present invention,
Since the next address becomes the address of the flash memory IC2, it is possible to access the next address, that is, the flash memory IC2, in parallel with the waiting time (WW1). Therefore, here, following the process (W1) of step 1 to the flash memory IC1,
Flash memory IC for access to the next address
The process of step 1 to 2 (W2) is performed. For the same reason, the access to the next next address, that is, the process of step 1 to the flash memory IC3 (W
3) is performed, and the process (W4) of step 1 to the flash memory IC4 is also performed.

Now, the flash memories IC1 to IC4 are
Since the waiting time of step 2 is all to be exhausted, the process waits at least until the flash memory IC1 becomes accessible (WW9). Flash memory IC1
When the waiting time of step 2 is reached, the flash memory IC1 can be accessed. Therefore, the processing of step 3 to the flash memory IC1, that is, the write program verify command is sent (V1), and the waiting time of step 4 is reached. Take (WV1). Subsequently, since the flash memory IC2 can be accessed, the processing of step 3 is performed on the flash memory IC2 (V
2) Take the waiting time of step 4 (WV2). Similarly, the processes of steps 3 and 4 (V3, WV3) for the flash memory IC3 and the processes of steps 3 and 4 (V4, WV4) for the flash memory IC4 can be performed.

When the waiting time (WV9) is exhausted, the flash memory IC1 can be accessed again. Therefore, the process of step 5 for the flash memory IC1 (C1) and the step 5 for the flash memory IC2 are sequentially performed. The process (C2), the process of step 5 for the flash memory IC3 (C3), and the process of step 5 for the flash memory IC4 (C4) can be performed. In this way
Since a number of words equivalent to the number of flash memory ICs can be processed substantially in parallel, even if writing is sequentially performed to all addresses of the memory card 9, in this example,
Since four words can be processed in a time substantially equal to the time required to process one word in the past, the processing can be performed about four times faster than in the past.

[0024]

Therefore, all flash memories I
If the waiting time for one flash memory IC is longer than the time for one round of access to C, if the number of flash memory ICs is increased and the parallelism is increased accordingly, the information medium having the configuration of the present invention The total writing time to the device is reduced to a fraction of that of the conventional configuration. Further, when the number is increased more than that, the waiting time as an information medium is eliminated, so that the writing time is shortened to about (actual access time / waiting time). As can be understood from the above description, in the information medium having the configuration of the present invention, since the flash memory IC is selected by decoding the lower bits of the address signal, the access to the information medium from the outside can be prevented. Even if the addresses are arranged in order, since they can be processed in parallel, high-speed writing is possible.

[Brief description of drawings]

FIG. 1 is a block diagram of a memory card as an example of an information medium having the configuration of the present invention.

FIG. 2 is a timing chart for explaining the operation of the information medium having the configuration of the present invention.

FIG. 3 is a block diagram of a memory card having a conventional configuration.

[Explanation of symbols]

1, 2, 3, 4 ... Flash memory IC 5 ... Decoder 8 ... Memory card 9 ... Memory card 100-118, 200-207, 300-333 ... Terminal

Claims (2)

[Claims] 1. A plurality of flash memory ICs are provided, one of the flash memory ICs is selected by a signal obtained by decoding the lower bits of an address signal, and the remaining bits obtained by removing the lower bits from the address signal are selected. An information medium, characterized in that one word in the selected flash memory IC is selected by the upper bits to access the selected word. 2. A flash memory IC accessed in word units, which receives a power of 2 and an address signal and a control signal, and decodes a number of bits corresponding to the lower power number of the address signal,
A decoder for outputting a selection signal to any one of the flash memory ICs at a timing according to the control signal, wherein the flash memory IC has the remaining upper bits obtained by removing the lower bits from the address signal. At the address input, selects one word in the flash memory IC receiving the selection signal, receives the control signal, and shifts to the selected word at a timing according to the control signal. An information medium characterized by making access.