JP2000322894A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a nonvolatile semiconductor memory device which can judge a validity of read data and can read out data simultaneously when writing and erasing data. SOLUTION: This device has memory cell arrays 11 and 21 comprised of a plurality of memory areas for storing data to the plurality of memory areas, an identifying means 51 for identifying a first memory area where data is erased, a comparing means 52 for comparing the first memory area and a second memory area where the data stored in the memory cell arrays 11 and 21 is stored when a read command for the data stored in the memory cell arrays is supplied, and a second output means 63 for outputting the comparison result by the comparing means 52. One memory area where data is erased is identified among the plurality of memory areas constituting the memory cell arrays, so that the other memory areas where data can be read at present can be identified. The semiconductor memory device can read data at the other memory areas when data is erased at one memory area.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a nonvolatile semiconductor memory device capable of simultaneously reading and writing data and erasing data.

[0002]

2. Description of the Related Art In recent years, a large number of flash EEPROMs (hereinafter referred to as flash memories) have been developed as main products of nonvolatile semiconductor memory devices capable of electrically writing and erasing data. Generally, the data rewriting time of a flash memory is equal to that of a DRAM (dynamic
Random Access Memory), SRA
M (Synchronous Dynamic Ran)
dom Access Memory). Furthermore, the flash memory could not read other data while rewriting the data.

In order to solve this inconvenience, it is necessary to divide a memory cell array for storing data of a flash memory into a plurality of banks, and to read data of another bank while rewriting data of one bank. A dual operation type flash memory that can operate is developed. FIG. 1 shows a configuration diagram of an example of a dual operation type flash memory. The dual operation type flash memory 10 of FIG. 1 includes a memory cell array 11, an X decoder 12, a Y decoder 13,
A bank 1 including a memory cell array 21, an X decoder 22, a Y decoder 23, and a read circuit 24; a write circuit 31;
Erase circuit 32, control circuit 33, address buffer 3
4, an address generator 35, an output circuit 36,
Address input terminal 41, data input / output terminal 42, R
The configuration includes a D / BY # terminal 43.

The flash memory 10 has X decoders 12 and 22 for selecting memory cells for each of two divided memory cell arrays 11 and 21, and Y decoders 13 and 23.
And a read circuit 1 for reading data from a memory cell
4 and 24 are provided. On the other hand, the flash memory 10
Has only one system because of a large occupation area on the chip, and has two banks 1 and 2 sharing a writing circuit 31 for writing data and an erasing circuit 32 for erasing data.

Therefore, the flash memory 10 cannot rewrite a plurality of banks at the same time. However, it is possible to read data of another bank while rewriting data of one bank. Reading data from another bank while rewriting data in one bank in this manner is called a dual operation operation.

Hereinafter, this dual operation operation will be briefly described. For example, when an instruction for writing data to the bank 1 or erasing data is input, the address buffer 34 stores an address for writing data to the bank 1 or erasing data. Data is written to or erased from the address by utilizing it. In the case of writing, data to be written is input from the data input / output terminal 42 and supplied to the writing circuit 31.

When a read address is input to the address input terminal 41 during the writing or erasing, the control circuit 33 controls the address buffer 34 to supply the address to the bank 1 without supplying the address to the bank 1. Feed to 2. Bank 2 is an X decoder 2 independent of bank 1
Since it has the Y decoder 23 and the read circuit 24, it is possible to read data of the memory cells included in the memory cell array 21.

It is necessary to designate an address included in a bank in which writing or erasing is not performed as an address input from the outside during writing or erasing. The read data is output from the data input / output terminal 42. The flash memory 10 has an RD / BY # terminal 43 for outputting a signal indicating that a write or erase operation is being performed to the outside. For example, RD /
When the output of the BY # terminal 43 is High, it indicates that writing or erasing has not been performed in the flash memory 10 and the flash memory 10 is in a readable state. Also, RD
When the output of the / BY # terminal 43 is Low, writing or erasing is performed in the flash memory 10, and
Indicates that the state cannot be read.

The flash memory shown in FIG. 1 has an RD when any one of the banks is performing writing or erasing.
Although the output of the / BY # terminal 43 is Low, the read operation of the bank in which writing or erasing is not performed is not prohibited.

[0010]

By the way, data in the flash memory is erased in a predetermined block unit, and the block is called a sector. For example, FIG.
In the dual operation type flash memory shown in (1), when there are a plurality of sectors to be erased,
The sector may span multiple banks.

At this time, data erasure is performed sequentially for each sector, and it is determined in the flash memory 10 at which timing the bank to be erased is switched, that is, which bank is in a readable state. Cannot judge outside in real time. This is because the RD / BY # terminal 43 outputs Low when at least one bank is performing writing or erasing, and it was not possible to determine a readable bank at that time.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and provides a nonvolatile semiconductor memory device capable of judging the validity of read data and capable of simultaneously reading and writing data and erasing data. The purpose is to provide.

[0013]

Therefore, in order to solve the above-mentioned problems, the present invention according to claim 1 comprises a memory cell array comprising a plurality of storage areas and storing data in the plurality of storage areas; Identification means for identifying one of the storage areas from which data is being erased,
A first output unit for outputting a signal to an output terminal corresponding to one storage area identified as performing the data erasure.

As described above, by identifying one storage area from which data is erased among a plurality of storage areas constituting the memory cell array, another storage area from which data can be read at present is identified. Can be identified. This is based on the fact that, in the nonvolatile semiconductor memory device of the present invention, while data is erased in one storage area, data can be read in another storage area.

Therefore, one storage area where data is currently erased can be confirmed outside the semiconductor memory device by the first output means, and data erasure and reading can be performed simultaneously. According to a second aspect of the present invention, there is provided a memory cell array including two storage areas and storing data in the two storage areas;
Identification means for identifying one of the storage areas from which data is to be erased, and a signal indicating one of the storage areas identified to be to be erased to an existing output terminal And control means for performing the control.

As described above, by identifying one of the two storage areas constituting the memory cell array from which data is to be erased, the other storage area from which data can be read at present. Can be identified. Further, the identification result by the identification means can be output to the existing output terminal by the control means. Therefore, one storage area in which data is currently erased is provided without providing a dedicated output terminal. It can be confirmed externally, and data can be erased and read at the same time.

According to a third aspect of the present invention, there is provided a memory cell array comprising a plurality of storage areas for storing data in the plurality of storage areas, and erasing data among the plurality of storage areas. When an identification means for identifying the first storage area and an instruction to read data stored in the memory cell array are supplied, the second storage area storing the data is compared with the first storage area. Comparing means for outputting a result of comparison by the comparing means;
Output means.

As described above, of the plurality of storage areas constituting the memory cell array, the first storage area from which data is to be erased is identified, and the instruction to read the data stored in the memory cell array at that time is issued. When supplied,
By comparing the second storage area in which the data is stored with the first storage area, the storage area from which data is currently being erased is the same as the storage area from which data is read based on the supplied instruction. It can be determined whether or not there is.

This is based on the fact that in the nonvolatile semiconductor memory device of the present invention, data erasing and data reading cannot be performed simultaneously in one storage area, and the storage area for erasing data is not used. And the same storage area from which data is read, it can be determined that the read data is invalid. The comparison result output from the second output means indicates whether the storage area from which data is currently erased and the storage area from which data is read based on the supplied instruction are the same, in other words, This is an output signal indicating whether the read data is valid or not, and there is no increase in output terminals due to an increase in the storage area.

Further, the present invention according to claim 4 is characterized by comprising control means for controlling the comparison result by the comparison means to be output to an existing output terminal. As described above, since the control unit can output the identification result by the identification unit to the existing output terminal, the storage area where the data is currently being erased is provided without providing a dedicated output terminal. It can be determined based on the instruction whether or not the storage area from which data is read is the same.

According to a fifth aspect of the present invention, when the comparison result by the comparing means indicates that the second storage area and the first storage area are the same, the data read from the memory cell array is invalidated. It is characterized by the following. As described above, it is possible to determine whether the data read from the memory cell array is valid based on the comparison result by the comparing means.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 shows a configuration diagram of the first embodiment of the semiconductor memory device of the present invention. The semiconductor memory device 10 of FIG. 2 is the same as the configuration diagram of FIG. 1 except for a part, and the same portions are denoted by the same reference numerals and description thereof will be omitted. In this embodiment, a flash memory will be described as an example, but the present invention is not limited to this.

The flash memory 10 shown in FIG. 2 includes a bank 1 including a memory cell array 11, an X decoder 12, a Y decoder 13, and a read circuit 14, and a memory cell array 21, an X decoder 22, a Y decoder 23, and a read circuit 24. Bank 2, a write circuit 31, an erase circuit 32, a control circuit 33, and an address buffer 34.
, An address generator 35, an output circuit 36, an address input terminal 41, a data input / output terminal 42,
The configuration includes a / BY # terminal 43, a bank decoder 51, an RE1 terminal 61, and an RE2 terminal 62.

The flash memory 10 has X decoders 12 and 22 for selecting memory cells for each of the two divided memory cell arrays 11 and 21, and Y decoders 13 and 23.
And a read circuit 1 for reading data from a memory cell
4 and 24 are provided. On the other hand, the flash memory 10
Is a write circuit 31 for writing data and an erase circuit 32
Has only one system because of a large occupation area on the chip, and is shared by the two banks 1 and 2. Therefore, the flash memory 10 cannot simultaneously rewrite a plurality of banks.

As described above, since data in a plurality of banks cannot be written or erased at the same time, when erasing a plurality of sectors spanning a plurality of banks, processing is sequentially performed in sector units. The control circuit 33 controls which process of reading, writing, and erasing data in each bank is performed. Further, the control circuit 33 controls to which bank the input signal such as the address is supplied, or from which bank the data signal is output.

Hereinafter, the operation of the flash memory 10 of FIG. 2 will be described. For example, when an instruction for erasing data in bank 1 is input, address buffer 34 stores the address of the data to be erased from bank 1. The address generator 35 selects a sector designated to be erased, selects a bank address indicating a bank including the sector, and outputs the selected sector and the bank address to the bank 1. The erasing circuit 32 erases the data of the selected sector.

The bank address output from the address generator 35 indicates the bank including the sector that is actually being erased at that time. Therefore,
The flash memory 10 of FIG. 2 has a bank decoder 51 for decoding the bank address. The bank decoder 51 decodes the bank address supplied from the address generator 35 and outputs a signal indicating a bank including a sector which is actually being erased to the RE1 terminal 61 or the RE2 terminal 62 at that time. For example, if the bank including the sector that is actually being erased is bank 2 at that time, the output signal of the RE1 terminal 61 is set to High,
By setting the output signal of the RE2 terminal 62 to Low,
It can be confirmed outside the flash memory 10 that the bank 1 is in a readable state and the bank 2 is in a non-readable state.

FIG. 3 is a timing chart of the first embodiment of the semiconductor memory device according to the present invention. Referring to FIGS. 3B and 3C, the output signal of the RE1 terminal 61 is High, R
It can be confirmed that the output signal of the E2 terminal 62 is Low. At this time, it can be confirmed outside the flash memory 10 that the bank 1 is in a readable state and the bank 2 is in a non-readable state.

Therefore, when a read address is input from the address input terminal 41 at the timing shown in FIG. 3A, data based on the read address is read at the timing shown in FIG. At this time, when the read data is read from the bank 1, it can be determined that the data is valid data. On the other hand, when the read data is read from the bank 2, it can be determined that the data is invalid data.

Therefore, the flash memory 10 shown in FIG.
In this case, since a dedicated output terminal is provided, it is possible to determine whether each bank has a readable state or a non-readable state even if it has a plurality of banks. Next, a second embodiment of the present invention will be described.
FIG. 4 shows a configuration diagram of a second embodiment of the semiconductor memory device of the present invention. The semiconductor memory device 10 of FIG. 4 is the same as the configuration diagram of FIG. 2 except for a part, and the same portions are denoted by the same reference numerals and description thereof will be omitted. In this embodiment, a flash memory will be described as an example, but the present invention is not limited to this.

The number of banks included in the flash memory is 2
, The existing RD /
The BY # terminal 43 can be used. 4 outputs an output signal of the bank decoder 51 to the existing RD / BY # terminal 43 via the selector 65. Switching between the normal function of the RD / BY # terminal 43 and the function of the present invention is performed by the control circuit 33 switching the output of the selector 65 by, for example, a switching command. The selector 65 is supplied with the output signal from the bank decorator 51 and the output signal from the control circuit 33, and selects one of the signals under the control of the control circuit 33 to select R.
Output to the D / BY # terminal 43.

For example, when the output signal of the RD / BY # terminal 43 is switched to indicate which bank is in a readable state, the bank 1 is output when the output signal of the RD / BY # terminal 43 is High. Is in a readable state, and when the output signal of the RD / BY # terminal 43 is Low, it can be confirmed outside the flash memory 10 that the bank 2 is in a readable state.

FIG. 5 is a timing chart of a second embodiment of the semiconductor memory device according to the present invention. Referring to FIG. 5B,
It can be confirmed that the output signal of the RD / BY # terminal 43 is High. The output signal of the RD / BY # terminal 43 is Hi
If it is defined that the bank 1 is in a readable state in the case of gh, it can be externally confirmed that the flash memory 10 is in a state in which the bank 1 can be read and the bank 2 is in a state in which it cannot be read.

Therefore, when a read address is input from the address input terminal 41 at the timing shown in FIG. 5A, data based on the read address is read at the timing shown in FIG. At this time, when the read data is read from the bank 1, it can be determined that the data is valid data. On the other hand, when the read data is read from the bank 2, it can be determined that the data is invalid data.

Therefore, the flash memory 10 shown in FIG.
In this case, it is possible to determine which bank is in a readable state or in a non-readable state without providing a dedicated output terminal. Next, a third embodiment of the present invention will be described. FIG. 6 shows a configuration diagram of a third embodiment of the semiconductor memory device of the present invention. The semiconductor memory device 10 of FIG. 6 is the same as the configuration diagram of FIG. 2 except for a part, and the same portions are denoted by the same reference numerals and description thereof will be omitted.
In this embodiment, a flash memory will be described as an example, but the present invention is not limited to this.

The flash memory 10 shown in FIG. 6 includes a bank 1 including a memory cell array 11, an X decoder 12, a Y decoder 13, and a read circuit 14, and a memory cell array 21, an X decoder 22, a Y decoder 23, and a read circuit 24. Bank 2, a write circuit 31, an erase circuit 32, a control circuit 33, and an address buffer 34.
, An address generator 35, an output circuit 36, an address input terminal 41, a data input / output terminal 42,
/ BY # terminal 43, bank decoder 51, and comparator 5
2 and a dedicated output terminal 63.

The bank decoder 51 decodes a bank address supplied from the address generator 35,
At that time, a signal indicating the bank including the sector that is actually being erased is output to the comparator 52. When a read address is input from the address input terminal 41, a signal indicating a bank based on the read address is output from the comparator 52.
Output to The comparator 52 compares the signals supplied from the bank decoder 51 and the address input terminal 41, and outputs a signal based on the comparison result to the dedicated output terminal 63.

For example, when the comparison result in the comparator 52 indicates that the banks match, that is, when the bank including the sector being erased matches the bank based on the read address, the dedicated output from the comparator 52 is output. Lo to terminal 63
w is defined to be output. At this time, the bank based on the read address is in an unreadable state, and it can be determined outside the flash memory 10 that the read data is invalid data.

On the other hand, if the result of comparison by comparator 52 indicates that the banks do not match, that is, if the bank containing the sector being erased does not match the bank based on the read address, Dedicated output terminal 63
Is defined to output a High signal. At this time, the bank based on the read address is in a readable state, and it can be determined outside the flash memory 10 that the read data is valid data.

FIGS. 7 and 8 are timing charts of a third embodiment of the semiconductor memory device according to the present invention. Referring to FIG. 7B, the output signal of the dedicated output terminal 63 is Low.
When it is defined that a low signal is output from the comparator 52 to the dedicated output terminal 63 when the comparison result in the comparator 52 indicates that the banks match, based on the read address shown in FIG. It can be determined that the read data shown in FIG. 7C is invalid.

On the other hand, referring to FIG. 8B, the output signal of the dedicated output terminal 63 is High, and FIG. 8C is read based on the read address shown in FIG.
Can be determined to be valid. Therefore, in the case of the flash memory 10 of FIG. 6, the bank based on the read address input from the address input terminal 41 and the bank based on the bank address output from the address generator 35, including the sector actually erased at that time. Is determined on the basis of the result of comparing the read data with the valid data. Therefore, there is no limitation due to an increase in the number of banks.

Next, a fourth embodiment of the present invention will be described. FIG. 9 shows a configuration diagram of a fourth embodiment of the semiconductor memory device of the present invention. The semiconductor memory device 10 of FIG. 9 is the same as the configuration diagram of FIG. 6 except for a part, and the same portions are denoted by the same reference numerals and description thereof will be omitted. In this embodiment, a flash memory will be described as an example, but the present invention is not limited to this.

In the flash memory 10 of FIG. 6, the provision of the dedicated output terminal 63 leads to an increase in the chip area.
It is also possible to use the D / BY # terminal 43. FIG.
Flash memory 10 outputs the output signal of the comparator 52 to the existing RD / BY # terminal 43 via the selector 65. Switching between the normal function of the RD / BY # terminal 43 and the function of the present invention is performed by the control circuit 33 switching the output of the selector 65 by, for example, a switching command. The selector 65 is supplied with the output signal from the comparator 52 and the output signal from the control circuit 33, selects one of the signals under the control of the control circuit 33, and outputs the selected signal to the RD / BY # terminal 43.

For example, when the output signal of the RD / BY # terminal 43 is switched to indicate whether the read data is valid or invalid, the read data is output when the output signal of the RD / BY # terminal 43 is High. Is valid and RD
When the output signal of the / BY # terminal 43 is Low, it can be confirmed outside the flash memory 10 that the read data is invalid.

FIG. 10 shows a fifth embodiment of the semiconductor memory device according to the present invention.
FIG. 4 shows a timing chart of the embodiment. Referring to FIG. 10B, it can be confirmed that the output signal of the RD / BY # terminal 43 is High. If it is defined that the read data is valid when the output signal of the RD / BY # terminal 43 is High, the read data shown in FIG. 10C read based on the read address shown in FIG. It can be determined that it is valid. On the other hand, when the output signal of the RD / BY # terminal 43 is Low, it can be determined that the read data shown in FIG. 10C read based on the read address shown in FIG. 10A is invalid.

Therefore, the flash memory 10 shown in FIG.
In this case, it is possible to determine whether the read data is valid or invalid based on the read address without providing the dedicated output terminal 63. Note that the storage areas described in the claims correspond to the banks 1 and 2,
The identification means corresponds to the bank decoder 51, the first output means corresponds to the RE1 terminal 61 and the RE2 terminal 62, the comparison means corresponds to the comparator 52, and the second output means corresponds to the dedicated output terminal 6.
Corresponds to 3.

[0047]

As described above, according to the first aspect of the present invention, of a plurality of storage areas constituting a memory cell array, one storage area from which data is erased is identified. And other storage areas from which data can currently be read. This is based on the fact that, in the nonvolatile semiconductor memory device of the present invention, while data is erased in one storage area, data can be read in another storage area.

Accordingly, one storage area where data is currently erased can be confirmed outside the semiconductor memory device by the first output means, and data erasing and reading can be performed simultaneously. According to the second aspect of the present invention, the current data can be read by identifying one of the two storage areas constituting the memory cell array from which data is to be erased. Other storage areas can be identified. Further, the identification result by the identification means can be output to the existing output terminal by the control means. Therefore, one storage area in which data is currently erased is provided without providing a dedicated output terminal. It can be confirmed externally, and data can be erased and read at the same time.

According to a third aspect of the present invention, a first storage area from which data is to be erased is identified from among a plurality of storage areas constituting a memory cell array, and at that time, the first storage area is stored in the memory cell array. When an instruction to read the data is supplied, the storage area in which the data is currently erased and the supplied instruction are compared by comparing the second storage area storing the data with the first storage area. It can be determined whether or not the storage area from which data is read is the same based on

This is based on the fact that in the nonvolatile semiconductor memory device of the present invention, data erasing and data reading cannot be performed simultaneously in one storage area, and the storage area for erasing data is not used. And the same storage area from which data is read, it can be determined that the read data is invalid. The comparison result output from the second output means indicates whether the storage area from which data is currently erased and the storage area from which data is read based on the supplied instruction are the same, in other words, This is an output signal indicating whether the read data is valid or not, and there is no increase in output terminals due to an increase in the storage area.

Further, according to the present invention, since the identification result by the identification means can be output to the existing output terminal by the control means, the current data is erased without providing a dedicated output terminal. It is possible to determine whether or not the storage area for performing the operation is the same as the storage area from which data is read based on the supplied instruction. Further, according to the present invention, it is possible to determine whether the data read from the memory cell array is valid based on the comparison result by the comparing means.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an example of a dual operation type flash memory.

FIG. 2 is a configuration diagram of a first embodiment of a semiconductor memory device of the present invention.

FIG. 3 is a timing chart of the first embodiment of the semiconductor memory device of the present invention.

FIG. 4 is a configuration diagram of a second embodiment of the semiconductor memory device of the present invention.

FIG. 5 is a timing chart of a second embodiment of the semiconductor memory device of the present invention.

FIG. 6 is a configuration diagram of a third embodiment of the semiconductor memory device of the present invention.

FIG. 7 is a timing chart of a third embodiment of the semiconductor memory device of the present invention.

FIG. 8 is a timing chart of a third embodiment of the semiconductor memory device of the present invention.

FIG. 9 is a configuration diagram of a fourth embodiment of the semiconductor memory device of the present invention.

FIG. 10 is a timing chart of a fourth embodiment of the semiconductor memory device of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Flash memory 11, 21 Memory cell array 12, 22 X decoder 13, 23 Y decoder 14, 24 Read circuit 31 Write circuit 32 Erase circuit 33 Control circuit 34 Address buffer 35 Address generator 36 Output circuit 41 Address input terminal 42 Data input / output terminal 43 RD / BY # terminal 51 Bank decoder 52 Comparator 61 RE1 terminal 62 RE2 terminal 63 Dedicated output terminal 65 Selector

Claims (5)

[Claims] 1. A memory cell array comprising a plurality of storage areas and storing data in the plurality of storage areas, and identification means for identifying one of the plurality of storage areas from which data is erased. And a first output means for outputting a signal to an output terminal corresponding to the one storage area identified as erasing the data. 2. A memory cell array comprising two storage areas for storing data in the two storage areas, and identification means for identifying one of the two storage areas from which data is erased. And a control means for controlling a signal indicating one storage area identified as erasing the data to be output to an existing output terminal. 3. A memory cell array comprising a plurality of storage areas for storing data in the plurality of storage areas, and an identification means for identifying a first storage area from which data is erased among the plurality of storage areas. A comparison unit that compares a second storage area storing the data with the first storage area when an instruction to read data stored in the memory cell array is supplied; A non-volatile semiconductor storage device having second output means for outputting a result. 4. The nonvolatile semiconductor memory device according to claim 3, further comprising control means for controlling the comparison result by said comparison means to output to an existing output terminal. 5. The method according to claim 1, wherein the comparison result by said comparing means is the second one.
5. The non-volatile semiconductor memory device according to claim 4, wherein when the storage area indicates the same as the first storage area, data read from the memory cell array is invalidated.