TWI734359B - Method for manufacturing optoelectronic semiconductor chip and bonded wafer used therefor - Google Patents

Abstract

The invention provides a method for manufacturing an optoelectronic semiconductor chip and a bonded wafer used in the same. Wafer materials include sapphire, silicon carbide, gallium arsenide, etc., which are used to make epitaxial layer (epitaxy) growth and serve as a substrate. This method divides the wafer into a mother wafer and a daughter wafer. After the mother wafer and the daughter wafer are bonded using appropriate bonding technology, it can withstand the warpage caused by the high temperature and stress of about 1000 degrees during the epitaxy process; epitaxy Use non-physical destruction methods to release the bond after the process. The mother wafer can be recycled. The daughter wafer and the epitaxial layer are directly used in the wafer process without thinning or a small amount of thinning. This solves the problem of the raw material and wafer processing cost of the substrate wafer for the large-size epitaxial layer, and obtains the wavelength Epitaxial layer with better uniformity.

Description

Method for manufacturing optoelectronic semiconductor chip and bonded wafer used therefor

The invention relates to a method for manufacturing a photoelectric semiconductor wafer, in particular to a method for manufacturing a photoelectric semiconductor wafer using a bonded wafer suitable for epitaxial layer growth.

Single crystal sapphire, silicon carbide, and gallium arsenide crystals are typical epitaxial materials with excellent photoelectric effect and are widely used in LEDs and power devices. Crystals such as sapphire, silicon carbide, and gallium arsenide all consume a lot of electrical energy when growing. And the larger the wafer size, the lower the yield of the crystal material. The semiconductor substrate wafer gradually transitions from 4 inches to 6 inches or 8 inches, and the cost is relatively high.

The crystal needs to go through multiple processes such as cutting, grinding, polishing, and cleaning to become a wafer; after growing an epitaxial layer on the wafer, the wafer manufacturing process needs to reduce the thickness of the entire wafer to reduce the wafer size. The thickness of the wafer is usually less than 1/3 of the wafer, that is to say, more than half of the wafer has to be polished off with a thinner at the end, resulting in a huge waste of crystal material.

Wafer thickness is one of the key factors affecting the wavelength uniformity of the epitaxial layer. The thicker the thickness, the more it can reduce the warpage caused by the stress of the epitaxial layer, thereby improving the wavelength uniformity. In order to reduce the size of the wafer and reduce the waste of packaging materials, the wafer The thickness is getting thinner and thinner, so the thickness of the substrate wafer needs to be thinner, which causes the uniformity of the wavelength of the epitaxial layer to be affected. In addition, the thicker the wafer, the more cost is spent in the wafer manufacturing process to reduce the thickness, which causes a lot of waste of crystal materials.

Therefore, the first object of the present invention is to provide a method for manufacturing optoelectronic semiconductor wafers.

Therefore, the method for manufacturing the optoelectronic semiconductor wafer of the present invention divides the substrate wafer on which the epitaxial layer is grown into a mother wafer and a daughter wafer. The mother wafer and the daughter wafer include sapphire, silicon carbide or gallium arsenide. Then, select an appropriate bonding medium to grow a bonding medium layer on the surface (as the bonding surface) on the mother wafer, the daughter wafer or both, preferably a bonding medium layer is grown on one of the surfaces, It is especially recommended to grow a bonding dielectric layer on the mother wafer as an intermediate layer. The intermediate layer includes one or any combination of silicon dioxide, aluminum nitride, and gallium nitride.

Through the intermediate layer, the mother wafer and the daughter wafer are bonded together. The bonding method is designed to bond the mother wafer and the daughter wafer in a vacuum high temperature environment of 300°C to 1000°C, and the bonding medium layer is located on the bonding surface. After the daughter wafer performs a semiconductor epitaxial process to form a semiconductor epitaxial layer on its surface, the bonding medium layer can be destroyed in a non-destructive debonding manner to separate the mother wafer from the daughter wafer and separate from the mother wafer The subsequent daughter wafer and the semiconductor epitaxial layer on the daughter wafer continue the wafer process; the mother wafer can be annealed at a high temperature after cleaning to release the stress accumulated by the epitaxial growth, and the annealed mother wafer can be recycled.

The thickness design of the mother wafer and the daughter wafer may be designed according to the thickness of the final wafer, and the thickness of the daughter wafer may be slightly thicker or equal to the thickness of the substrate wafer of the final wafer before bonding. In order to improve the yield rate, it is recommended that the thickness of the mother wafer be greater than the thickness of the daughter wafer; the minimum thickness of the mother wafer is determined by subtracting the thickness of the daughter wafer from the thickness specification of the substrate wafer on which the epitaxial layer is grown. The two sides of the mother wafer should be rough, and high hardness micropowders such as silicon carbide, boron carbide, silicon carbide, etc. can be double-sided grinding to make a stable rough surface, and the warpage (WARP) produced by wire cutting is smoothed; or The rough surface is made by techniques related to yellow light, developing, and etching. The surface of the daughter wafer for epitaxial layer growth is defined as the front side, and the opposite side to the front side is the back side. The back side is bonded to the mother wafer. The front side of the daughter wafer should be the surface that can be used to grow the epitaxial layer and be the polished surface. It is a polished surface or the same rough surface as both sides of the mother wafer. Before bonding, ozone (O ₃ ) and nitrogen (N ₂ ) gas should be used for plasma cleaning or chemical cleaning to activate the surface of the bonding medium layer. The reagent for activation treatment includes hydrogen peroxide, ammonia or a mixture of the two. The activation treatment may also be a dry treatment, such as activation by plasma.

The bonding dielectric layer can be _{a thin film formed by bonding dielectrics such as silicon dioxide (SiO 2} ), aluminum nitride (AlN), or gallium nitride, and the intermediate layer composed of bonding dielectrics needs to have a certain thickness to be uniform Bonding, for example, using 3 μm to 6 μm, can resist the bending caused by the high temperature of 1000° C. and the stress of the epitaxial layer during the growth of the epitaxial layer. The aforementioned bonding conditions need to be performed on high-temperature, vacuum bonding equipment. The non-destructive debonding method is an acid etching method, which corrodes and destroys the bonding medium layer without damaging the mother wafer and daughter wafers of the bonded wafer. The recycling of the mother wafer requires cleaning, annealing and other processes to eliminate the stress formed during the preparation of the epitaxial layer, and the mother wafer is relatively flat, which is conducive to reuse.

Preferably, the thickness of the daughter wafer is 50~400μm thicker than the final wafer, and some space for thinning adjustment is reserved. After being separated from the mother wafer, the side of the daughter wafer away from the epitaxial layer can be thinned. The thickness can be slightly thicker than the minimum thickness of the mother wafer by 100 to 1000 μm to allow for processing windows such as the thinning of the mother wafer after the daughter wafer and the mother wafer are built, or the processing process before the mother wafer is recycled. The thickness of the daughter wafer is 100 μm to 450 μm, and the thickness of the mother wafer is 300 μm to 1500 μm.

Preferably, the roughness of the front side (polished surface) of the daughter wafer is 0.08-0.2 nm; the double-sided roughness of the back side of the daughter wafer and the mother wafer is 0.1-1.2 μm.

Preferably, the thickness of the intermediate layer composed of the bonding medium is 3-6 μm.

Preferably, the bonding conditions are in a vacuum environment of 300 to 600°C. More preferably, the bonding condition is 300-400° C. in a vacuum environment, and the mother wafer and the daughter wafer are bonded at a pressure of ^{100-250 kg/cm 2 for 10-40 minutes.}

Preferably, when the bonding medium is silicon dioxide, the debonding method is to use hydrofluoric acid (HF) to corrode the bonding medium layer at room temperature.

Preferably, the method of reusing the mother wafer is cleaning with ultrasonic clean water, spin-drying, and then placing it in a high temperature annealing furnace at 1350 to 1400°C for annealing to release residual stress in epitaxial production.

Preferably, in some cases, the mother wafer may include a first mother wafer and a second mother wafer, or consist of two or more separable wafers.

The second objective of the present invention is to provide a bonded wafer.

The bonding wafer of the present invention divides the wafer into a mother wafer and a daughter wafer. After the mother wafer and the daughter wafer are bonded by an appropriate bonding technology, the wafer can withstand the high temperature and stress caused by the external delay of about 1000°C. Curve changes; use non-physical destructive methods to release the bond after extension. The mother wafer can be recycled. The daughter wafer and the epitaxial layer are directly used in the wafer process without thinning or a small amount of thinning, which solves the problem of the raw material and wafer processing cost of large-size epitaxial wafers, and obtains better wavelength uniformity The epitaxial layer.

For the sake of reducing the manufacturing cost of semiconductor devices and improving the efficiency of mass production, the more research focused on large-size wafers, large-size wafers need better resistance to process stress, because the mother wafer of the present invention is recyclable Therefore, the thickness of the mother wafer can be appropriately increased to maintain the stability of mass production, such as reducing the warpage problem during epitaxial growth, thereby improving the uniformity of epitaxial layer growth without significantly increasing production costs. The mass production and manufacturing of large-size wafers has far-reaching significance.

Other features and advantages of the present invention will be described in the following description, and partly become obvious from the description, or understood by implementing the present invention. The purpose and other advantages of the present invention can be realized and obtained through the structures specifically pointed out in the specification, the scope of the patent application and the drawings.

Several specific embodiments of the present invention will be further described in detail below in conjunction with the accompanying drawings. However, the following description and description of the embodiments do not constitute any limitation to the protection scope of the present invention.

It should be understood that the terms used in the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. It is further understood that when the terms "comprising" and "including" are used in the present invention, they are used to indicate that the stated features, wholes, steps, elements exist, and do not exclude one or more other features, wholes, steps, elements and/ Or the presence or increase of their combination.

Unless otherwise defined, all terms (including technical and scientific terms) used in the present invention have the same meanings as commonly understood by those of ordinary skill in the art to which the present invention belongs. It should be further understood that the terms used in the present invention should be understood as having meanings consistent with the meanings of these terms in the context of this specification and related fields, and should not be understood in an idealized or overly formal sense, except for the present invention. Clearly defined as such.

Before the present invention is described in detail, it should be noted that in the following description, similar elements are denoted by the same numbers.

Referring to Figure 1, the present invention provides a method for making optoelectronic semiconductor wafers to make low-cost, high-performance, and environmentally friendly wafers. Using the bonding method of the present invention, it can be used for large-size sapphire, silicon carbide or arsenic. Gallium wafers are extremely cost-effective. The method includes the following steps: providing a mother wafer 100 and a daughter wafer 200 of the same material or different materials, performing an evaporation process on one of the surfaces of the mother wafer 100 and the daughter wafer 200 to form a bonding medium layer, and The bonding medium layer has bonding characteristics. The bonding medium layer is used as the intermediate layer 300. After polishing the bonding medium layer, it is cleaned. The intermediate layer 300 is activated with ammonia and hydrogen peroxide. The purpose of the activation treatment is to promote the surface of the intermediate layer 300. The formation of hydroxyl (-OH), the hydroxyl forms a Coulomb tensile force on the Al or O of the wafer material, which is conducive to the connection of the intermediate layer 300 with the mother wafer 100 and the daughter wafer 200. The mother wafer 100 and the daughter wafer 200 are pre-aligned to each other. Align, perform a thermo-compression bonding process (for example, at a pressure of 15000 kg and a temperature of 300 to 600 degrees) to obtain bonded wafers, inspect and clean the bonded wafers, and finally store them in storage.

Referring to Figures 2 to 4 again, in detail, a mother wafer 100 and a daughter wafer 200 are provided. The material selection of the two includes but not limited to: sapphire, silicon carbide or gallium arsenide, in order to perform the subsequent high temperature bonding process ( For example, thermal compression bonding process), the ambient temperature that the wafer material can withstand should not be less than 1000°C. By providing the intermediate layer 300 between the two, in this embodiment, the non-smooth surface (rough surface) 110 of the mother wafer 100 and the side of the daughter wafer 200 opposite to the non-smooth surface 110 are made of a bonding medium material. (E.g. SiO ₂ ) is vapor-deposited to produce the intermediate layer 300 (not shown in the production process of the intermediate layer 300), and the intermediate layer 300 is subjected to mechanical chemical polishing (CMP) treatment, since the intermediate layer 300 is made by evaporation deposition mode The layer 300 needs to be polished to improve the flatness of the intermediate layer 300, and then the intermediate layer 300 on the non-smooth surface (rough surface) 110 of the mother wafer 100 and the intermediate layer 300 on the surface of the daughter wafer 200 are activated After treatment, the intermediate layer 300 is oppositely subjected to a bonding process. In the embodiment, for example, the thickness of the mother wafer 100 is 300 μm to 500 μm. In order to prevent the wafer from being broken, the thickness of the mother wafer 100 tends to increase with the increase of the wafer area. Therefore, in a large-sized wafer For example, for an 8-inch wafer, the thickness of the mother wafer 100 may reach 1500 μm, and the thickness of the daughter wafer 200 may be 100 μm to 450 μm. The daughter wafer 200 under the concept of the present invention can reach a thickness of at least 100 μm. It needs to be clearly stated that, With the improvement of wafer fabrication technology, it is possible to obtain a thinner sub-wafer 200 by adopting the technical solution of the present invention.

In some embodiments, the better the surface cleanliness of the mother wafer 100 and the daughter wafer 200, the better the quality of the grown bonding medium layer (intermediate layer 300), and the better the bonding effect. After polishing the surface of the daughter wafer 200 away from the mother wafer 100 or the surface of the mother wafer 100 away from the daughter wafer 200, the bonded wafer is cleaned. The smaller the warpage (WARP) and flatness (TTV) of the mother wafer 100 and the daughter wafer 200, the better the bonding effect, and the thickness of the bonding dielectric layer can even be reduced. The suitable bonding medium needs to have a high lattice match with the wafer material to avoid excessive deformation of the bonded wafer due to the mutual stress of temperature changes, such as silicon dioxide (SiO ₂ ), aluminum nitride (AlN), gallium nitride (GaN), etc., or any combination of more than one. The bonding medium layer (middle layer 300) can be grown on the mother wafer 100 or the bonding medium layer (middle layer 300) can be grown on both the mother wafer 100 and the daughter wafer 200, and the bonding can be done under suitable temperature and pressure. combine.

In the embodiment provided by the present invention, on the basis of the above solution, the surface roughness of the mother wafer 100 and the daughter wafer 200 relative to each other will also affect the bonding effect. The rougher the surface of the mother wafer 100 and the daughter wafer 200, the denser the bonding medium layer (intermediate layer 300) will grow; however, if the roughness is too large, holes are prone to appear, which affects the bonding effect. In this embodiment, The roughness is controlled at 0.1~1.2μm.

In this embodiment, the size of the mother wafer 100 and the daughter wafer 200 must be the same, and the diameter must be within ±0.1 mm to facilitate the alignment of the mother wafer 100 and the daughter wafer 200 during bonding. When the epitaxial layer is an LED and the sub-wafer 200 is a sapphire wafer, it is necessary to form a pattern on the surface of the sub-wafer 200 where the epitaxial layer is formed by exposure, development, etching, etc., to form a patterned sapphire substrate. PSS) in order to increase the light-emitting effect in the light-emitting semiconductor device. In implementation, the patterned sapphire wafer substrate can improve the growth quality of the epitaxial layer and reduce the defects from both the reflection and the epitaxial layer lattice matching, which is effective Improve the light-emitting efficiency of light-emitting semiconductor devices. In the bonding process of the mother wafer 100 and the daughter wafer 200, it is recommended to avoid damage to the pattern caused by the pressure during bonding before the pattern is made.

Different from other physical destruction methods, such as laser separation, a deep groove is drawn around the side of the mother wafer 100 or daughter wafer 200, and then a tool is used to cut along the deep groove in a low temperature environment to remove the mother wafer. The circle 100 is separated from the daughter wafer 200. This method will produce many chipping corners, and the reuse rate of the mother wafer 100 will be reduced. In other embodiments of the present invention, the bonding dielectric layer (intermediate layer 300) is etched by acid. For example, using hydrofluoric acid to corrode the bonding medium layer (intermediate layer 300), it can be easily separated after 40 minutes of immersion in hydrofluoric acid at room temperature without affecting the epitaxial layer and crystal of the semiconductor device. Round body (mother wafer 100 and daughter wafer 200).

5, the sub-wafer 200 is used to fabricate the epitaxial layer 210, and the epitaxial layer 210 is fabricated on the side (smooth surface) of the sub-wafer 200 away from the bonding dielectric layer (the intermediate layer 300). The epitaxial layer 210 sequentially includes an N-type layer, a P-type layer, and an active layer located between the two, and the epitaxial layer 210 is fabricated, for example, by depositing semiconductor materials by metal organic chemical vapor deposition (MOCVD). .

6 and 7, after the epitaxial layer 210 is fabricated, the intermediate layer 300 is unwound, and the mother wafer 100 and the daughter wafer 200 are separated. The sub-wafer 200 continues the wafer fabrication process, for example, using photoresist etching to make a chip pattern on the side of the epitaxial layer 210 away from the sub-wafer 200, remove part of the P-type layer until the N-type layer is exposed, and then place the P-type layer and /Or an insulating protective layer or a transparent conductive diffusion layer is fabricated on the surface of the exposed N-type layer, and finally a wafer electrode connected with the P-type layer and the exposed N-type layer is fabricated to form a light-emitting semiconductor wafer structure.

At the same time, the separated mother wafer 100 can be annealed at a high temperature and recycled again to make a bonded wafer again. The sub-wafer 200 is thinned to meet the requirements of the wafer process. The thinning thickness of the sub-wafer 200 of the present invention can be significantly lower than the thinning thickness of the substrate wafer in the prior art. Taking a substrate wafer with a thickness of 750 μm as an example, the present invention only needs to remove about 200 μm wafer material. A wafer substrate wafer of 100 μm is obtained, and as a comparison, the prior art requires the removal of 650 μm, which is more than 3 times that of the present invention. In industrial production, the method of grinding and removal is usually used to remove the excess substrate. However, the efficiency of the grinding process to remove the substrate is low, and it will also consume the grinding wheel, which leads to a longer process time and aggravates the loss of production spare parts such as the grinding wheel. Compared with the prior art, the present invention saves production cost, shortens the thinning time, and also reduces the industrial waste generated, and plays a positive role in promoting the industrialization of large wafers with a size of six inches and above, for example.

In some embodiments, the thickness of the mother wafer 100 can be adjusted according to actual needs, and is further designed to include a bonding composition of the first mother wafer and the second mother wafer, which can be removed one by one to control the substrate crystal. The thickness of the circle is controlled.

However, the above are only examples of the present invention. When the scope of implementation of the present invention cannot be limited by this, all simple equivalent changes and modifications made in accordance with the scope of the patent application of the present invention and the content of the patent specification still belong to Within the scope covered by the patent of the present invention.

100: master wafer 110: non-smooth surface 300: middle layer 200: Sub-wafer 210: epitaxial layer

Other features and effects of the present invention will be clearly presented in the embodiments with reference to the drawings, in which: Figure 1 shows the manufacturing process flow of bonded wafers; and 2 to 7 are schematic diagrams of the manufacturing process of optoelectronic semiconductor products and corresponding bonded wafer photos.

100: master wafer

110: non-smooth surface

300: middle layer

200: Sub-wafer

210: epitaxial layer

Claims (18)

A method for manufacturing optoelectronic semiconductor wafers includes the following steps: step 1, providing a mother wafer and a daughter wafer, and synthesizing them into a bonded wafer through an intermediate layer bonding disposed between the two; step 2, in the child wafer The epitaxial layer is made on a surface of the wafer away from the intermediate layer; and step 3, the intermediate layer is unwound, the mother wafer and the daughter wafer are separated, the daughter wafer and the epitaxial layer after the unwound continue to make the wafer process, and the unwrapped The mother wafer is recycled after being annealed at a high temperature. The method for manufacturing an optoelectronic semiconductor wafer according to claim 1, wherein the side of the unwrapped sub-wafer is thinned away from the epitaxial layer. The method for manufacturing an optoelectronic semiconductor wafer according to claim 1, wherein, in step 1, an intermediate layer is formed on the opposite side of the mother wafer and the daughter wafer or only one of the intermediate layers is formed on the opposite side of the mother wafer and the daughter wafer before bonding. The method for manufacturing an optoelectronic semiconductor wafer according to claim 1, wherein the mother wafer and the daughter wafer include sapphire, silicon carbide, or gallium arsenide. The method for manufacturing an optoelectronic semiconductor wafer according to claim 1, wherein the thickness of the sub-wafer is 100 μm to 450 μm. The method for manufacturing an optoelectronic semiconductor wafer according to claim 1, wherein the thickness of the mother wafer is 300 μm to 1500 μm. The method for manufacturing an optoelectronic semiconductor wafer according to claim 1, wherein the ambient temperature that the mother wafer and/or daughter wafer can withstand is not less than 1000°C. The method for manufacturing an optoelectronic semiconductor wafer as described in claim 1, which Wherein, the intermediate layer includes one or any combination of silicon dioxide, aluminum nitride, and gallium nitride. The method for manufacturing an optoelectronic semiconductor wafer according to claim 1, wherein, in step 3, the intermediate layer can be removed by an etching process. The method for manufacturing an optoelectronic semiconductor wafer according to claim 1, wherein the mother wafer is composed of at least a first mother wafer and a second mother wafer. The method for manufacturing an optoelectronic semiconductor wafer according to claim 1, wherein, in step 1, the intermediate layer is activated before bonding. The method for manufacturing an optoelectronic semiconductor wafer according to claim 11, wherein the reagent for the activation treatment includes hydrogen peroxide, ammonia, or a mixture of the two. The method for manufacturing an optoelectronic semiconductor wafer according to claim 11, wherein the activation treatment is a dry treatment, and activation is performed by plasma. A bonded wafer, as a growth substrate for producing optoelectronic semiconductor wafers, includes: a bonded wafer, including a mother wafer, a daughter wafer, and an intermediate layer between the two, wherein the mother wafer is at least composed of The first mother wafer and the second mother wafer are composed. The bonded wafer according to claim 14, wherein the thickness of the sub-wafer is 100 μm to 450 μm. The bonded wafer according to claim 14, wherein the mother wafer is 300 μm to 1500 μm. The bonded wafer according to claim 14, wherein the thickness of the intermediate layer is 3 μm to 6 μm. The bonded wafer according to claim 14, wherein the sub-wafer is far away from the One surface of the mother wafer is a smooth surface.

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