TWI543273B - Bonded semiconductor structures formed by methods of forming bonded semiconductor structures in 3d integration processes using recoverable substrates - Google Patents

Description

Bonded semiconductor construction using a recyclable substrate in a three-dimensional spatial accumulation process

The present invention relates to a method of forming a bonded semiconductor structure using a three-dimensional integration technique and a bonded semiconductor structure formed using the same.

The three dimensional integration of two or more semiconductor structures can bring many benefits to microelectronic applications. For example, a three-dimensional spatial accumulation of microelectronic components can improve electrical performance and power consumption while reducing the area occupied by components. For related information, see The Handbook of 3D Integration, edited by P. Garrou et al. (Wiley-VCH Publishing, 2008).

The three-dimensional spatial accumulation of the semiconductor structure can be achieved by attaching a semiconductor die to other one or more semiconductor dies (ie, die-to-die (D2D)), A semiconductor die is attached to one or more semiconductor wafers (ie, die-to-wafer (D2W)), and a semiconductor wafer is attached to one or more other semiconductor wafers (ie, wafer-to-wafer Round (W2W)).

The bonding technique used to bond a semiconductor structure to another semiconductor structure can be classified in different ways. One is to classify the two semiconductor structures by bonding an intermediate material between the two semiconductor structures, and the second is a button junction. Whether the interface allows electrons (ie, current) to be classified through the interface. The so-called "direct bonding method" is a method of establishing a direct solid-to-solid chemical bond between two semiconductor structures to bond them together without using an intermediate bonding material between the two semiconductor structures. A metal-to-metal direct bonding method has been developed to bond a metal material on a surface of a first semiconductor structure to a metal material on a surface of a second semiconductor structure.

The metal-to-metal direct bonding method can also be classified according to the temperature range at which each method operates. For example, some metal-to-metal direct bonding methods are performed at relatively high temperatures, thus causing at least partial melting of the metallic material at the bonding interface. Such direct bonding processes may not be suitable for bonding processed semiconductor structures containing one or more component structures, as their relatively high temperatures may adversely affect previously formed component structures.

The "hot press bonding" method is performed at a temperature between 200 ° C (200 ° C) and approximately 500 ° C (500 ° C), usually between approximately 300 ° C (300 ° C) and approximately Celsius A direct bonding method of applying pressure between the bonding surfaces between 400 degrees (400 ° C).

Other direct bonding methods have also been developed, which can be carried out at temperatures of 200 degrees Celsius (200 ° C) or lower. For such direct bonding processes performed at 200 degrees Celsius (200 ° C) or lower, this specification is referred to as an "ultra-low temperature" direct bonding process. The ultra-low temperature direct bonding process can be carried out by careful removal of surface impurities and surface compounds (eg, native oxide layers), and by increasing the area of intimate contact between the two surfaces on an atomic scale. The area of intimate contact between the two surfaces is typically achieved by grinding the bonding surfaces to reduce the surface roughness to a value close to the atomic scale, applying pressure between the bonding surfaces to cause plastic deformation, or simultaneously grinding the bonds. The surface of the junction and the application of pressure to achieve such plastic deformation.

Some ultra-low temperature direct bonding methods can be applied without applying pressure at the bonding interface between the bonding surfaces, but in other ultra-low temperature direct bonding methods, in order to achieve a suitable bonding strength at the bonding interface, the bonding surface can be applied. Pressure is applied to the bonding interface between the two. In the technical field of the present invention, an ultra-low temperature direct bonding method for applying pressure between bonding surfaces is generally referred to as a "surface assisted bonding" or "SAB" method. Therefore, in this specification, "surface auxiliary bonding" and "SAB" mean and include a first material at a temperature of 200 degrees Celsius (200 ° C) or lower. The material abuts against a second material and applies pressure at the bonding interface between the bonding surfaces to directly bond the first material to any direct bonding process of the second material.

Silicon (Si) and glass substrates are generally considered to be base substrates on which semiconductor components can be fabricated for high bandwidth performance and for heterogeneous three-dimensional integration of the first level. Integration). In general, the interposer is a planar structure comprising a plurality of layers of material that are interposed between two or more different dies and/or wafers in a three-dimensional spatial accumulation process. The interposer will be used for intermediate processing steps during the integration of the 3D integrated circuit (3D-IC). The main reason for the development of 矽 interposers is the high demand for high-density wafer-to-package interconnects, the matching of thermal expansion coefficients (CTE), and for passive components (eg The importance of integrating resistors, inductors, etc.) into the interposer. For example, the interposer may include a through substrate via (TSV) in addition to a decoupling capacitor and a voltage regulator. In addition, the use of the 矽 interposer can also achieve the purpose of greatly reducing the size of the appearance.

After forming a through-substrate via (TSV) in the tantalum interposer and forming a redistribution layer (RDL) on the tantalum interposer, the tantalum interposer is typically thinned. Such thinning processes often involve the loss of expensive tantalum materials. In addition, the TSV layer and the RDL layer filled with copper are often thinned as the interposer is thinned. After forming the TSV layer and the RDL layer, and after thinning the interposer, mechanical strain may be generated in the interposer. This strain may cause warpage of the interposer, resulting in breakage or other mechanical damage of the interposer. The warp-deformed interposer may also warp the known good (KGD) assembled on the interposer, thereby significantly affecting the yield of the operative elements fabricated on or above the interposer.

The purpose of this summary is to present a series of concepts in a concise form. These concepts are further detailed in the exemplary embodiments of the invention. This summary is not intended to identify key features or essential features of the claimed subject matter, and is not intended to limit the scope of the claimed subject matter.

In some embodiments, the present invention encompasses a three-dimensional spatial accumulation technique using a recyclable substrate and provides a solution to overcome the problem of generally limited yield due to strain generated within the interposer. Moreover, some embodiments may involve direct bonding techniques that allow the structures to be aligned and bonded at low temperatures and low pressures in a three dimensional space accumulation process.

In some embodiments, the invention includes a method of forming a bonded semiconductor structure. In accordance with such methods, a first substrate structure can be provided that includes a relatively thin layer of material on a relatively thick substrate body. A plurality of thinner material layers are formed through the through wafer interconnect and through the first substrate structure. At least one processed semiconductor structure is bonded over the thinner material layer and at least one of the at least one processed semiconductor structure is opposite to a thinner material layer of the first substrate structure opposite the one side of the thicker substrate body A conductive component is electrically coupled to at least one of the through-wafer interconnects of the through-wafer interconnects. A second substrate structure is bonded over the at least one processed semiconductor structure opposite the at least one processed semiconductor structure opposite the first substrate structure. The thicker substrate body of the first substrate structure is removed leaving a thinner layer of material of the first substrate structure bonded to the at least one processed semiconductor structure. At least one of the through-wafer interconnects of the through-wafer interconnects can be electrically coupled to one of the conductive features of the other structure.

In other embodiments, the invention includes bonded semiconductor structures formed using the methods disclosed herein. For example, an embodiment of the bonded semiconductor structure of the present invention can include a first substrate structure including a plurality of through wafer interconnects through a thinner layer of material and temporarily bonded to the material One of the layers is a thicker substrate body. Multiple processed semiconductor structures can be electrically coupled to The through-wafer interconnects, and a second substrate structure may be temporarily bonded over the processed semiconductor structures, with the processed semiconductor structures being opposite one side of the first substrate structure.

The description of the present specification is not intended to be an actual description of any particular semiconductor structure, component, system or method, but is merely an idealized description for describing embodiments of the invention.

The use of any headings in this specification should not be construed as limiting the scope of the embodiments of the invention, which is defined by the scope of the following claims and their legal equivalents. The concepts described under any particular heading also generally apply to the rest of the specification.

This specification is hereby incorporated by reference. Moreover, the cited references are not to be construed as a prior art, regardless of the description of the features of the invention.

In the present specification, the term "semiconductor structure" means and includes any structure used in forming a semiconductor element. For example, a semiconductor structure includes a die and a wafer (eg, a carrier substrate and an element substrate), and the assembled structure or composite structure includes two or more dies that are integrated with each other in three dimensions and/or Wafer. The semiconductor structure includes, in addition to the intermediate structure formed during the fabrication of the semiconductor device, a completely fabricated semiconductor device.

In the present specification, the term "processed semiconductor structure" means and includes any semiconductor structure containing at least one or more element structures that have been partially formed. The processed semiconductor structure is a subset of the semiconductor structure, and all of the processed semiconductor structures are semiconductor structures.

In the present specification, the term "bonded semiconductor structure" means and includes any structure containing two or more semiconductor structures attached together. Bonded semiconductor structure is one of semiconductor structures The set, all bonded semiconductor structures are semiconductor structures. In addition, bonded semiconductor structures containing one or more processed semiconductor structures are also processed semiconductor structures.

In the present specification, the term "elemental structure" means and includes any portion of a processed semiconductor structure that is, comprises or defines at least a portion of an active or passive component of a semiconductor component, and the semiconductor component It is then formed above or in the semiconductor structure. For example, the component structure includes active and passive components of the integrated circuit, such as transistors, transducers, capacitors, resistors, conductive lines, conductive vias, and conductive contact pads.

In the present specification, the term "through-wafer interconnect" or "TWI" means and includes any conductive via that penetrates at least a portion of a first semiconductor structure, spanning the first semiconductor structure and a second semiconductor An interface between the structures provides a structural and/or electrical interconnection between the first semiconductor structure and the second semiconductor structure. In the technical field of the present invention, there are other names for penetrating wafer interconnects, such as "through silicon vias", "through substrate vias", and "through". Through-wafer vias, or the abbreviation of the above name, such as "TSV" or "TWV". The direction through which the through-wafer interconnect penetrates a semiconductor structure is generally substantially perpendicular to the substantially planar major surfaces of the semiconductor structure (ie, parallel to the "Z" axis).

In accordance with some embodiments of the present invention, a recyclable substrate structure is temporarily bonded to a semiconductor structure and used to form a bonded semiconductor structure. The recyclable substrate structures are removed from the semiconductor structures at different times during the formation of the bonded semiconductor structure.

The recyclable substrate structures provide support for the interposer throughout the processing stage. In addition, the bondable interface between the recyclable substrate structure and the interposer is manipulated to control the aspect ratio of the TSV and the final thickness of the interposer (ie, a thinner interposer results in a lower TSV aspect ratio) ).

1A through 1C illustrate the fabrication of a substrate structure 120 (Fig. 1C) that may be employed in accordance with some embodiments of the present invention. Referring to FIG. 1A, a substrate structure 100 is provided that includes a relatively thin layer of material 102 on a relatively thick substrate body 104. In some embodiments, the substrate structure 100 can comprise a wafer level substrate having an average diameter of hundreds of meters or more. As an example of non-limiting properties, the thinner material layer 102 can have an average thickness of about 200 microns (200 μm) or less, about 100 microns (100 μm) or less, or even about 50 microns (50 μm). ) or thinner. The thicker substrate body 104 has an average thickness, for example, of between about 300 micrometers (μm) and 750 micrometers or more.

The thinner material layer 102 can comprise a semiconductor material such as tantalum or niobium. Such a semiconductor material may be polycrystalline or at least substantially composed of a single crystal material, and such semiconductor material may be doped or undoped. In other embodiments, the thinner material layer 102 may comprise a ceramic material such as an oxide (eg, yttrium oxide (SiO ₂ ), aluminum oxide (Al ₂ O ₃ ), etc.), a nitride (eg, nitride). Niobium (Si ₃ N ₄ ), boron nitride (BN), etc., or an oxynitride (such as lanthanum oxynitride (SiON)).

The thicker substrate body 104 can have a composition different from that of the thinner material layer 102, but can itself comprise a semiconductor material or a ceramic material as described above with respect to the thinner material layer 102. In other embodiments, the thicker substrate body 104 can comprise a metal or metal alloy.

In some embodiments, the thinner material layer 102 can be temporarily attached to the thicker substrate body 104 using a temporary bonding technique, such as U.S. Patent Application Serial No. 12, filed on Jul. 15, 2010, in the name of Sadaka et al. The technology disclosed in /837,326, the entire contents of which is incorporated herein by reference.

The thicker substrate body 104 can comprise a portion of the substrate structure 100 that is recyclable and reusable, as described in more detail below.

Referring to FIG. 1B, a plurality of through wafer interconnects 112 may be formed and penetrated through the thinner material layer 102 to form the substrate structure 110 of FIG. 1B. The various processes for forming the through-wafer interconnects 112 are known in the art to which the present invention pertains and may be employed in embodiments of the present invention. As a non-limiting example, a mask layer with a pattern may be provided over the exposed major surface of the thinner material layer 102. The patterned mask layer can include a plurality of apertures that extend through the pattern mask layer at locations where the through wafer interconnects 112 are to be formed through the thinner material layer 102. The vias through the thinner material layer 102 can then be etched using an etch process such as an anisotropic wet chemical etch process or an anisotropic dry reactive ion etch process. Another example may include performing a laser drilling over the exposed major surface of the thinner material layer 102 to form a via. After forming the via holes, the pattern mask layer can be removed, and then the via holes are filled with one or more conductive metals or metal alloys (such as copper or a copper alloy) or polycrystalline germanium to form The through wafer interconnects 112. For example, one or more of a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, an electroless plating process, and an electrolytic plating process can be used to provide conductive materials in the vias and form the vias. Wafer interconnect 112.

After forming the through-wafer interconnects 112 through the thinner material layer 102, one or more redistribution layers (RDL) may be applied to the thinner material layer 102 opposite one of the thicker substrate bodies 104. 122 is formed over the thinner material layer 102 to form the substrate structure 120 shown in FIG. 1C. As is known in the art to which the present invention pertains, a redistribution layer can be used to redistribute the position of an electrical component of a first structure or component to accommodate a pattern of conductive features on another structure or component to be coupled. In other words, a redistribution layer may have a first conductive component pattern in its first mask and a second, different conductive component pattern on a second side opposite the first surface. As shown in FIG. 1C, the redistribution layer 122 can include a plurality of electrically conductive features 124 disposed within and surrounded by a dielectric material 126. The conductive features 124 can include one or more of a conductive pad, laterally extending conductive or conductive traces, and longitudinally extending conductive vias. In addition, the redistribution layer 122 may comprise a plurality of layers formed by sequentially covering one layer, wherein each layer includes a conductive member 124 and a dielectric material 126, and the conductive member 124 in one layer may be connected to the conductive member 124 of the adjacent layer. There is direct physical contact and electrical contact, such that the conductive members 124 of the redistribution layer 122 extend from the surface of the redistribution layer 122 continuously through the dielectric material 126 to the redistribution layer 122. The opposite side. On the side of the redistribution layer 122 adjacent to the thinner material layer 102 and the through-wafer interconnects 112, the patterns of the conductive members 124 in the redistribution layer 122 can be matched with the patterns The patterns of the through-wafer interconnects 112 are complementary such that the through-wafer interconnects 112 have direct physical and electrical contact with the corresponding conductive features 124 of the redistribution layer 122. As described above, the pattern of the conductive members 124 in the redistribution layer 122 may be redistributed from one surface of the redistribution layer 122 across the thickness of the redistribution layer 122 to the other side of the redistribution layer 122.

The redistribution layer 122 can provide the possibility of forming a customized routing pattern. For example, the wiring pattern formed by the customized redistribution layer may be a mirror image of a processed semiconductor structure or a plurality of structural metallization layers, and the processed semiconductor structure or structures will be later Bonded to the surface of the thinner material layer 102.

The redistribution layer 122 may also provide the possibility of "fan-in" and/or "fan-out". For example, in the case of a fan-in redistribution layer, in addition to other limitations due to the proximity effects of the component structure, the component structure (eg, a wafer component) limits the area available for the contact and passive component structures. . In the case of a fan-out redistribution layer, the fan-in limit is eliminated, providing flexibility for routing using standard CMOS back-end processes. Passive components formed in such redistribution layers can utilize thick metal and low-k dielectric materials available in the redistribution layer. Thus, passive components formed in such redistribution layers exhibit better performance characteristics than passive components fabricated on component structures, such as a wafer component.

Referring to FIG. 1D, after the redistribution layer 122 is formed, at least one processed semiconductor structure 132A can be bonded to the thinner material layer 102 of the substrate structure 120 opposite to one of the thicker substrate bodies 104. Above the thin material layer 102 to form the structure 130 of Figure 1D. For example, the at least one processed semiconductor structure 132A can be directly bonded to the redistribution layer 122, as shown in FIG. 1D.

In some embodiments, a plurality of processed semiconductor structures 132A, 132B, 132C can be bonded to the thinner material layer on a side of the thinner material layer 102 of the substrate structure 120 opposite one of the thicker substrate body 104. The redistribution layer 122 above 102 is as shown in FIG. 1D. The processed semiconductor structures 132A, 132B, 132C may be juxtaposed in a lateral direction along a common plane, the common flat The face is oriented parallel to one of the major surfaces of the first substrate structure 120, as shown in Figure ID. In other words, each of the processed semiconductor structures 132A, 132B, 132C can occupy a different area on the substrate structure 120, and a plane can be drawn from its position parallel to the first substrate structure. One of the major surfaces of 120 passes through each of the processed semiconductor structures 132A, 132B, 132C.

One or more of the processed semiconductor structures 132A, 132B, 132C may comprise, for example, semiconductor dies (made of germanium or other semiconductor materials), and may also include electronic signal processors, memory elements, MEMS (MEMS) And one or more of photovoltaic elements (eg, light-emitting diodes, lasers, photodiodes, solar cells, etc.).

When the processed semiconductor structures 132A, 132B, and 132C are bonded to the substrate structure 120, the conductive members 134 of the processed semiconductor structures 132A, 132B, and 132C can be electrically connected to the redistribution layer 122. Conductive features 124 and the through-wafer interconnects 112 that extend through the thinner material layer 102 are coupled.

The bonding process used to bond the processed semiconductor structures 132A, 132B, 132C to the substrate structure 120 can be performed at one or more temperatures of about 400 ° C or less. In some embodiments, the processed semiconductor structures 132A, 132B, 132C can be bonded to the substrate using a hot press direct bonding process implemented at one or more temperatures of about 400 ° C or less. Structure 120. In other embodiments, the processed semiconductor structures 132A, 132B, 132C can be bonded to the substrate structure using an ultra-low temperature direct bonding process implemented at one or more temperatures of about 200 ° C or less. 120. In some examples, the bonding process can be carried out at a temperature of about room temperature. Bonding at these lower temperatures can avoid unintentional The component structures in the processed semiconductor structures 132A, 132B, 132C are damaged. Moreover, in some embodiments, the bonding process can include a surface assist bonding process. The direct bonding process can include a direct bonding process of an oxide to oxide (eg, ceria versus cerium oxide), and/or a direct bonding process of a metal to metal (eg, copper to copper).

In some embodiments, additional processed semiconductor structures may be stacked over the processed semiconductor structures 132A, 132B, 132C and associated with the processed semiconductor structures 132A using one or more three-dimensional spatial accumulation processes. 132B and 132C are electrically and physically coupled. An example of such processes is described below with reference to Figures 1E through 1H.

Referring to FIG. 1E, after the processed semiconductor structures 132A, 132B, 132C are bonded to the substrate structure 120, a low strain dielectric material 138 can be deposited over the processed semiconductor structures 132A, 132B, 132C. And around to form the structure 140 of FIG. 1E. The dielectric material 138 can comprise, for example, a polymeric material or an oxide material (e.g., yttria), and the dielectric material 138 can utilize, for example, a spin coating process, a chemical vapor deposition (CVD). A process or a physical vapor deposition (PVD) process is deposited.

The dielectric material 138 can be deposited in a conformal manner over the structure 130 of FIG. 1D such that the exposed major surface 139 of the dielectric material 138 includes peaks and valleys. The peaks may be located above the processed semiconductor structures 132A, 132B, 132C, which may be located above the area between the processed semiconductor structures 132A, 132B, 132C, as shown in FIG. 1E.

Referring to FIG. 1F, the exposed major surface 139 of the dielectric material 138 can be planarized, and a portion of the dielectric material 138 can be removed to pass the processed semiconductor structures 132A, 132B, 132C through the dielectric. Material 138 is exposed and forms structure 150 as shown in FIG. 1F. For example, a chemical etching process (dry or wet), a mechanical polishing process, or a chemical mechanical polishing (CMP) process can be used to planarize the exposed major surface 139 of the dielectric material 138 and remove the dielectric. A portion of the electrical material 138 and exposes the processed semiconductor structures 132A, 132B, 132C through the dielectric material 138.

In some embodiments, the processed semiconductor structures 132A, 132B, 132C can comprise processed semiconductor structures of different heights. In this case, the dielectric material 138 can be planarized to expose the highest processed semiconductor structure, followed by a combination of grain thinning and dielectric polishing to flatten the structure 150. .

As shown in FIG. 1G, an additional plurality of through wafer interconnects 162 can be formed and at least partially passed through the processed semiconductor structures 132A, 132B, 132C to form the structure 160. The additional through-wafer interconnects 162 formed may extend from the exposed major surfaces of the processed semiconductor structures 132A, 132B, 132C through the processed semiconductor structures 132A, 132B, 132C to the processed Conductive features 134 within semiconductor structures 132A, 132B, 132C. The through wafer interconnects 162 can be formed as described above with respect to forming the through wafer interconnects 112. However, the temperature of the processes can be limited to about 400 ° C or less to avoid damaging the component structures within the processed semiconductor structures 132A, 132B, 132C.

Referring to FIG. 1H, after forming the additional through-wafer interconnects 162, additional processed semiconductor structures 132D, 132E, 132F may be provided in the vertical direction using the processes described above with respect to FIGS. 1D through 1G. The upper portion is over the processed semiconductor structures 132A, 132B, 132C to form the bonded semiconductor structure 170 shown in FIG. 1H. As an example, a processed semiconductor structure 132D can be directly bonded to the processed semiconductor structure 132A, a processed semiconductor structure 132E can be directly bonded to the processed semiconductor structure 132B, and a processed semiconductor structure 132F can be Direct bonding to the processed semiconductor structure 132C. The bonding process temperature may be limited to about 400 ° C or lower to avoid damaging the component structures in the processed semiconductor structures 132A to 132F, and the bonding processes may include a non-hot pressing direct bonding process. Or an ultra-low temperature direct bonding process. Moreover, in some embodiments, the direct bonding processes can include surface assisted bonding processes.

In this configuration, the processed semiconductor structures 132D, 132E, 132F are respectively disposed in the longitudinal direction of the processed semiconductors along a line oriented perpendicular to the major surfaces of the first substrate structure 120. Above the structures 132A, 132B, 132C. For example, the processed semiconductor structure 132A and the processed semiconductor structure 132D are oriented along a common line perpendicular to one of the major surfaces of the first substrate structure 120, and are disposed one above the other in the longitudinal direction. One is below. In other words, a common line can be drawn from the processed semiconductor structure 132A and the processed semiconductor structure 132D, the common line passing through the processed semiconductor structure 132A and the processed semiconductor structure 132D perpendicular to the first The major surfaces of a substrate structure 120.

After the processed semiconductor structures 132D, 132E, 132F are bonded to the processed semiconductor structures 132A, 132B, 132C, an additional through wafer interconnect 172 can be formed to at least partially pass through the processed Semiconductor structures 132D, 132E, 132F. The additional through-wafer interconnects 172 formed may extend from the exposed major surfaces of the processed semiconductor structures 132D, 132E, 132F through the processed semiconductor structures 132D, 132E, 132F to the penetrations Wafer interconnect 162 or other conductive features of the processed semiconductor structures 132A, 132B, 132C. The through wafer interconnects 172 can be formed in accordance with the foregoing description of forming the through wafer interconnects 112. However, the temperature of the processes can be limited to about 400 ° C or less to avoid damaging the component structures within the processed semiconductor structures 132A through 132F.

The processes described above in connection with Figures 1D through 1G may be repeated one or more times as needed to accumulate any number of other processed semiconductor structural layers in the longitudinal direction in the three-dimensional spatial accumulation process. Above the semiconductor structures 132A-132F.

Referring to FIG. 1I, a second substrate structure 182 may be bonded over the processed semiconductor structures 132A-132F to form a pattern on the surface of the processed semiconductor structures 132A-132F opposite to the substrate structure 120. The semiconductor structure 180 is bonded to 1I.

The composition of the second substrate structure 182 can be at least substantially homogeneous, or the second substrate structure 182 can comprise a multilayer structure comprising a plurality of layers having different compositions. As a non-limiting example, the second substrate structure 182 can comprise a semiconductor material such as tantalum or niobium. Such a semiconductor material may be polycrystalline or at least substantially composed of a single crystal material, and such semiconductor material may be doped or undoped. In other embodiments, the second substrate structure 182 may comprise a ceramic material such as an oxide (eg, yttrium oxide (SiO ₂ ), aluminum oxide (Al ₂ O ₃ ), etc.), a nitride (eg, nitrogen). Hydrazine (Si ₃ N ₄ ), boron nitride (BN), etc., or an oxynitride (such as cerium oxynitride (SiON)). In some embodiments, the second substrate structure 182 can also comprise a metal or metal alloy.

The second substrate structure 182 can have an average thickness of, for example, between about 1.5 micrometers (μm) and a few centimeters.

In some embodiments, the second substrate structure 182 can be utilized as described above, using a technique such as that disclosed in U.S. Patent Application Serial No. 12/837,326, the entire entire entire entire entire entire entire- Attached to the semiconductor structure 170 of FIG. 1H. The second substrate structure 182 can be directly bonded to the exposure sheets of the dielectric material 174 of the processed semiconductor structures 132D-132F. One or more of the exposed surfaces of the processed semiconductor structures 132D-132F that penetrate the wafer interconnect 172.

Referring to FIG. 1J, after the second substrate structure 182 is temporarily bonded to the semiconductor structure 170 (FIG. 1H), the thicker substrate body 104 of the first substrate structure 120 can be bonded or otherwise removed. The thinner material layer 102 leaving the first substrate structure 120 and the through wafer interconnects 112 extending through the material layer are bonded to the redistribution layer 122 and the processed semiconductor structures 132A-132F. For example, the thicker substrate body 104 can be separated and recovered from the thinner material layer 102 in a manner that does not cause significant or unrepairable damage to the thicker substrate body 104.

As an option, a conductive bump 192 can be provided on the exposed end of each through wafer interconnect 112 to form the bonded semiconductor structure 190 of FIG. The conductive bumps 192 may comprise a conductive metal or metal alloy, such as a reflow solderable alloy, and the conductive bumps 192 may cause the through-wafer interconnects 112 in the bonded semiconductor structure 190 to be in the structure. It is electrically and electrically coupled to the conductive component of another structure 202, which may be one of the higher level substrates or components, or one of the higher level substrates or components.

For example, as shown in FIG. 1K, the bonded semiconductor structure 190 of FIG. 1J can be structurally and electrically coupled to the structure 202. For example, the structure 202 can include another processed semiconductor structure or a printed circuit board. As shown in FIG. 1J, the structure 202 can include a plurality of conductive features 204 and a surrounding dielectric material 206. For example, the conductive members 204 can include a bond pad. The conductive bumps 192 can be aligned and abutted against the conductive features 204. The conductive bumps 192 can be heated to cause the materials of the conductive bumps 192 to reflow. Thereafter, the material can be cooled and cured to form the through-wafer interconnects 112 and the conductive features in the structure 202. 204 structural and electrical bonding.

Referring to FIG. 1L, after the through-wafer interconnects 112 are structurally and electrically coupled to the conductive features 204 of the structure 202, the second substrate structure 182 (FIG. 1K) can be removed. To form the bonded semiconductor structure 210 shown in FIG. 1L.

After the thicker substrate body 104 and the second substrate structure 182 of the first substrate structure 120 are removed from the bonded semiconductor structure, the thicker substrate body 104 and/or the second substrate structure 182 can be Recycle and reuse. For example, the thicker substrate body 104 and/or the second substrate structure 182 can be formed in the foregoing method of forming a bonded semiconductor structure (eg, a bonded semiconductor structure similar to one of the bonded semiconductor structures 210 of FIG. 1L). Use one or more times.

The bonded semiconductor structure 210 of Figure 1L can be further processed as needed to suit its intended use. As a non-limiting example, a protective coating or cladding material may be provided over at least a portion of the bonded semiconductor structure 210, and/or between and around the structure 202 and each of the conductive bumps 192. Between the layers of material 102, a protective bonding material is provided.

In some embodiments of the invention, one or more of the substrate structures temporarily bonded to the semiconductor structure and removed from the semiconductor structure as described herein during the method of forming the bonded semiconductor structure may A semiconductor-on-insulator (SeOI) substrate, such as a silicon-on-insulator (SOI) substrate, is included.

For example, FIG. 2A presents an example of one of the semiconductor-on-insulator substrates 300 that may be employed in embodiments of the present invention. The semiconductor-on-insulator substrate 300 includes a layer of semiconductor material 302 disposed over a dielectric insulating layer 303, which may be disposed on a relatively thick substrate body 304. In such a substrate structure, the insulating layer 303 is commonly referred to as a "buried" layer, such as a "embedded oxide" layer.

The semiconductor material layer 302 and the insulating layer 303 are relatively thinner than the thicker substrate body 304. As an example of non-limiting properties, the semiconductor material layer 302 can have an average thickness of about 10 microns (10 μm) or less, about 100 nanometers (100 nm) or less, or even about 10 nanometers (10). Nm) or thinner. The insulating layer 303 may have an average thickness of about 1 micrometer (1 μm) or less, about 200 nanometers (200 nm) or less, or even about 10 nanometers (10 nm) or less. The thicker substrate body 304 can have an average thickness, for example, between about 750 micrometers (μm) and a few centimeters.

The layer of semiconductor material 302 can comprise a semiconductor material such as tantalum or niobium. Such a semiconductor material may be polycrystalline or at least substantially composed of a single crystal material, and such semiconductor material may be doped or undoped. The insulating layer 303 may comprise a ceramic material such as an oxide (eg, yttrium oxide (SiO ₂ ), aluminum oxide (Al ₂ O ₃ ), etc.), a nitride (eg, tantalum nitride (Si ₃ N ₄ ), Boron nitride (BN), etc., or an oxynitride (such as cerium oxynitride (SiON)). The thicker substrate body 304 may have a composition different from that of the semiconductor material layer 302 and/or the insulating layer 303, but may itself include the semiconductor material layer 302 and the insulating layer 303 described above. A semiconductor material or a ceramic material. In other embodiments, the thicker substrate body 304 may comprise a metal or metal alloy, although another material selected to exhibit a matching CTE is preferred.

Referring to FIG. 2B, a plurality of through wafer interconnects 312 can be formed and penetrated through the layer of semiconductor material 302 to form the substrate structure 310 of FIG. 2B, as discussed above with respect to FIG. 1B through the wafer interconnect 112. Said. After forming the through-wafer interconnects 312 through the semiconductor material layer 302, the substrate structure 310 can be processed to form a pattern as previously described with reference to FIGS. 1C through 1I. The bonded semiconductor structure 380 shown in 2C. The bonded semiconductor structure 380 is substantially similar to the bonded semiconductor structure 180 of FIG. 1I, but includes the substrate structure 310 of FIG. 2B having a redistribution layer 122 thereon in place of the first substrate structure 120.

After forming the bonded semiconductor structure 380 of FIG. 2C, the insulating layer 303 and the substrate body 304 can be removed from the bonded semiconductor structure 380 as previously described. The substrate body 304 can be recovered and reused as described above. After the insulating layer 303 and the substrate body 304 are removed, the obtained bonded semiconductor structure can be processed as described above with reference to FIGS. 1J to 1L.

As mentioned above with respect to the description of FIG. 1K, in some embodiments, the additional structure 202 to which the bonded semiconductor structure 190 of FIG. 1J is attached may comprise another processed semiconductor structure. An example of such a method is described below with reference to Figures 3A through 3D.

3A illustrates a bonded semiconductor structure 400 that can be removed from the bonded substrate structure 180 by removing the substrate body 104 of the first substrate structure 120 as previously described with reference to FIGS. 1I and 1J. The conductive bumps 192 (FIG. 1J) are formed on the through-wafer interconnect 112.

Referring to FIG. 3B, an additional processed semiconductor structure 412 can be directly bonded to the material layer 102, the through wafer interconnects 112, or both the material layer 102 and the through wafer interconnects 112.

As an example of non-limiting properties, the additional processed semiconductor structure 412 can include a semiconductor die, and can also include an electronic signal processor, a memory component, and a photovoltaic component (eg, a light emitting diode, a laser, a photodiode, One or more of solar cells, etc.).

Bonding the additional processed semiconductor structure 412 to the material layer 102 and/or the through wafer interconnects 112 can be performed at one or more temperatures of about 400 ° C or less. In some embodiments, the bonding process can comprise a hot press direct bonding process performed at one or more temperatures of about 400 ° C or less. In other embodiments, the bonding process can An ultra-low temperature direct bonding process carried out at one or more temperatures of about 200 ° C or less. In some examples, the bonding process can be carried out at a temperature of about room temperature. Moreover, in some embodiments, the bonding process can include a surface assist bonding process. The direct bonding process can include a direct bonding process of an oxide to oxide (eg, ceria versus cerium oxide), and/or a direct bonding process of a metal to metal (eg, copper to copper).

As shown in FIG. 3B, an additional through wafer interconnect 414 can be formed through and through the additional processed semiconductor structure 412. The additional through wafer interconnects 414 can be formed and penetrate the additional processed semiconductor structure before or after the additional processed semiconductor structure 412 is directly bonded to the material layer 102 and/or the through wafer interconnects 112. Structure 412. At least some of the through-wafer interconnects 414 may extend through the through-wafer interconnects 112 in the material layer 102 and be structurally and electrically coupled to the through-wafer interconnects 112.

As an option, a conductive bump 416 may be provided on the exposed end of each through wafer interconnect 414 to form the bonded semiconductor structure 410 of FIG. 3B in accordance with the foregoing description of the conductive bumps 192 with reference to FIG. 1J. .

Referring to FIG. 3C, the bonded semiconductor structure 410 of FIG. 3B can be structurally and electrically coupled to a structure 422. For example, the structure 422 can include another processed semiconductor structure or a printed circuit board. As shown in FIG. 3C, the structure 422 can include a plurality of conductive features 424 and a surrounding dielectric material 426. For example, the conductive members 424 can include a bond pad. The conductive bumps 416 can be aligned and abutted against the conductive features 424. The conductive bumps 416 can be heated to cause the materials of the conductive bumps 416 to reflow. Thereafter, the material can be cooled and cured to form the through-wafer interconnects 414 and the conductive features in the structure 422. 424 structural and electrical bonding.

Referring to FIG. 3D, after the through-wafer interconnects 414 are structurally and electrically coupled to the conductive features 424 of the structure 422, the second substrate structure 182 (FIG. 3C) can be viewed from FIG. 3D. The bonded semiconductor structure 430 is shown removed. For example, the second substrate structure 182 can be removed using a mechanical splitting process, an etch process, or a combination of such processes to form the bonded semiconductor structure 430.

After the thicker substrate body 104 and the second substrate structure 182 of the first substrate structure 120 are removed from the bonded semiconductor structure, the thicker substrate body 104 and/or the second substrate structure 182 It can be recycled and reused as discussed above.

The bonded semiconductor structure 430 of Figure 3D can be further processed as needed to suit its intended use. As a non-limiting example, a protective coating or cladding material may be provided over at least a portion of the bonded semiconductor structure 430, and/or between the structure 422 and the conductive bumps 416 A protective bonding material is provided between the surrounding processed semiconductor structures 412.

In accordance with the methods described above, the second substrate structure 182 is bonded to the processed semiconductor structures 132A-132F until the bonded semiconductor structures 200, 420 are bonded to the additional structures 202, 422. Thereafter, warpage, cracking, and other damage that may be caused by differences in thermal expansion coefficients of different materials and components in the bonded semiconductor structures may be avoided or reduced.

Exemplary embodiments of other non-limiting properties of the invention are described below.

Embodiment 1 : A method of forming a bonded semiconductor structure, comprising: providing a first substrate structure comprising a relatively thin layer of material on a relatively thick substrate body; forming a plurality of penetrations Wafer interconnecting through a thinner layer of material of the first substrate structure; at least one processed half of the relatively thinner material layer of the first substrate structure opposite one of the relatively thicker substrate bodies A conductor structure is bonded over the relatively thin layer of material and electrically coupling at least one of the at least one processed semiconductor structure to at least one of the through-wafer interconnects Bonding a second substrate structure over the at least one processed semiconductor structure at a side of the at least one processed semiconductor structure opposite the first substrate structure; removing the first substrate structure relatively Thick substrate body and leaving a relatively thin layer of material of the first substrate structure bonded to the at least one processed semiconductor structure; and interconnecting at least one of the through wafer interconnects Electrically coupled to one of the electrically conductive components of another structure.

Embodiment 2: The method of Embodiment 1, further comprising removing the at least one through-wafer interconnect of the through-wafer interconnects after electrically coupling to the conductive features of the other structure The second substrate structure.

Embodiment 3: The method of Embodiment 1 or Embodiment 2, wherein providing the first substrate structure further comprises temporarily bonding the thinner material layer to the thicker substrate body, and wherein the first substrate is removed Bonding a relatively thick substrate body of the structure and leaving a relatively thin layer of material of the first substrate structure to the at least one processed semiconductor structure includes separating the thicker substrate body from the thinner material layer.

The method of any one of embodiments 1 to 3, further comprising forming at least one redistribution layer on the one side of the thinner material layer of the first substrate structure opposite to the one side of the thicker substrate body After the thinner material layer is over, the at least one processed semiconductor structure is bonded over the thinner material layer of the first substrate structure, and wherein the at least one processed semiconductor structure is bonded to the first substrate Overlying the thinner layer of material comprises bonding the at least one processed semiconductor structure to the redistribution layer.

The method of any one of embodiments 1 to 4, wherein the at least one processed semiconductor structure is bonded above the thinner material layer of the first substrate structure at less than about 400 ° C. The at least one processed semiconductor structure is bonded over the thinner layer of material of the first substrate structure at one or more temperatures.

The method of any one of embodiments 1 to 5, wherein bonding the at least one processed semiconductor structure over the thinner material layer of the first substrate structure comprises using an ultra-low temperature direct bonding process At least one processed semiconductor structure is bonded over a thinner layer of material of the first substrate structure.

The method of any one of embodiments 1 to 6, wherein bonding the at least one processed semiconductor structure over the thinner material layer of the first substrate structure comprises bonding a plurality of processed semiconductor structures Above the thinner material layer of the first substrate structure.

Embodiment 8: The method of Embodiment 7, wherein at least some of the processed semiconductor structures are arranged one after another in a lateral direction along a common plane, the common plane being oriented parallel to the first One of the main surfaces of the substrate structure.

The method of embodiment 8, wherein at least some of the processed semiconductor structures of the processed semiconductor structures are stacked one above the other along a common line, the common lines being oriented perpendicular to the first One of the main surfaces of the substrate structure.

Embodiment 10: The method of Embodiment 7, wherein at least some of the processed semiconductor structures of the processed semiconductor structures are stacked one above the other along a common line, the common lines being oriented perpendicular to the first One of the main surfaces of the substrate structure.

Embodiment 11: The method of any of embodiments 1 to 10, further comprising selecting the other structure to include another processed semiconductor structure.

Embodiment 12: The method of any of embodiments 1 to 11, further comprising selecting the other structure to include a printed circuit board.

The method of any one of embodiments 1 to 12, further comprising selecting the first substrate structure to comprise a semiconductor-on-insulator (SeOI) substrate.

Embodiment 14: The method of Embodiment 13, further comprising selecting the first substrate structure to comprise a SOI substrate.

The method of any one of embodiments 1 to 14, further comprising forming an additional plurality after bonding the at least one processed semiconductor structure over the thinner material layer of the first substrate structure The wafer interconnect is penetrated through the at least one processed semiconductor structure.

The method of any one of embodiments 1 to 15, further comprising reusing the second substrate structure and the thicker substrate body of the first substrate structure in a method of forming a bonded semiconductor structure one of them.

Embodiment 17: An intermediate structure formed during fabrication of a bonding semiconductor structure, the intermediate structure comprising: a first substrate structure comprising: a plurality of layers extending through a relatively thin layer of material a through-wafer interconnect, and a relatively thick substrate body temporarily bonded to the material layer; electrically coupled to the plurality of processed semiconductor structures that penetrate the wafer interconnect; and a A second substrate structure, the second substrate structure being temporarily bonded over the processed semiconductor structures on the side of the processed semiconductor structures opposite one of the first substrate structures.

Embodiment 18: The intermediate structure of Embodiment 17, wherein the first substrate structure comprises a semiconductor-on-insulator (SeOI) substrate.

Embodiment 19: The intermediate structure of Embodiment 17 or Embodiment 18, wherein the thinner material layer has an average thickness of about 100 nanometers (100 nm) or less.

Embodiment 20: The intermediate structure of any one of embodiments 17 to 19, wherein at least some of the processed semiconductor structures are arranged one after another in a lateral direction along a common plane, the common plane being oriented Is parallel to one of the major surfaces of the first substrate structure.

Embodiment 21: The intermediate structure of any one of embodiments 17 to 20, wherein at least some of the processed semiconductor structures of the processed semiconductor structures are stacked one above the other along a common line, the common lines being oriented Is perpendicular to one of the major surfaces of the first substrate structure.

The above-described exemplary embodiments are not intended to limit the scope of the invention, as these embodiments are only examples of the embodiments of the invention, and the invention is defined by the scope of the appended claims and their legal equivalents. Any equivalent embodiments are within the scope of the invention. In fact, various modifications of the invention, such as a substitute for a useful combination of the elements, in addition to those shown and described herein, will be apparent from the description of the specification. Become obvious. In other words, one or more of the features of any one of the exemplary embodiments described herein may be combined with one or more features of another exemplary embodiment described herein as an additional embodiment of the invention. Such modifications and embodiments are also within the scope of the appended claims.

100, 110, 120, 310‧‧‧ substrate structure

102‧‧‧Material layer

104, 304‧‧‧ Thick substrate body

112, 162, 172, 312, 414‧‧‧through wafer interconnects

122‧‧‧ redistribution layer

124, 204‧‧‧ conductive parts

126, 138, 174‧‧‧ dielectric materials

130, 140, 150, 160, 422‧‧‧ structures

132A, 132B, 132C, 132D, 132E, 132F‧‧‧ processed semiconductor structures

134, 424‧‧‧ conductive parts

139‧‧‧Exposed main surface

170, 180, 190, 200, 210, 380, 410, 420, 430‧‧ ‧ bonded semiconductor structures

182‧‧‧Second substrate structure

192, 416‧‧‧ conductive bumps

206, 426‧‧‧ Around dielectric materials

300‧‧‧Insulator-on-semiconductor substrates

302‧‧‧Semiconductor material layer

303‧‧‧Dielectric insulation

412‧‧‧Additional processed semiconductor structures

While the specification has been described in the specification of the invention, and the claims of the invention are intended to be 1A to 1L are simplified cross-sectional views of a semiconductor structure, showing a bonded semiconductor structure formed in accordance with an exemplary embodiment of the present invention; 2A to 2C are simplified cross-sectional views of a semiconductor structure showing other embodiments of the method of forming a bonded semiconductor structure of the present invention; and Figs. 3A to 3D are simplified cross-sectional views of the semiconductor structure, showing the bonded semiconductor structure of the present invention Further embodiments of the method of formation.

100‧‧‧Material structure

102‧‧‧Material layer

104‧‧‧ Thick substrate body

Claims (5)

Forming an intermediate structure during fabrication of the bonding semiconductor structure, the intermediate structure comprising: a first substrate structure comprising: a plurality of through wafer interconnects extending through a relatively thin layer of material; a relatively thick substrate body temporarily bonded to the relatively thin material layer; at least one redistribution layer over the relatively thin material layer of the first substrate structure, attached to the first substrate a relatively thin layer of material opposite the one side of the relatively thick substrate body; a plurality of processed semiconductor structures electrically coupled to the through wafer interconnects, wherein the at least one redistribution layer is located Between the through wafer interconnects and the processed semiconductor structures; and a second substrate structure temporarily bonded to the processed semiconductor structures opposite one of the first substrate structures The semiconductor structure has been processed above. The intermediate structure of claim 1, wherein the first substrate structure comprises a semiconductor-on-insulator (SeOI) substrate. The intermediate structure of claim 1, wherein the relatively thin material layer has an average thickness of about 100 nanometers (100 nm) or less. Such as the intermediate structure of claim 1 of the patent scope, wherein the processed semiconductors At least some of the processed semiconductor structures in the structure are disposed one after another in a lateral direction along a common plane that is oriented parallel to one of the major surfaces of the first substrate structure. The intermediate structure of claim 4, wherein at least some of the processed semiconductor structures are stacked one above the other along a common line, the common line being oriented perpendicular to the first One of the main surfaces of the substrate structure.