TWI517226B - Methods for directly bonding together semiconductor structures, and bonded semiconductor structures formed using such methods - Google Patents

Description

Method of forming an adherent semiconductor structure comprising two or more processed semiconductor structures carried by a common substrate and semiconductor structures formed using such methods

Embodiments of the present invention generally relate to methods of forming semiconductor devices including two or more semiconductor structures bonded to a common substrate, and semiconductor devices formed using such methods.

Three-dimensional integration of two or more semiconductor constructions can bring many benefits to microelectronic applications. For example, a three-dimensional spatial accumulation of microelectronic components can improve electrical performance and power consumption while reducing the bottom area of the device. For related information, see The Handbook of 3D Integration, edited by P. Garrou et al. (Wiley-VCH Publishing, 2008).

The three-dimensional spatial accumulation of the semiconductor structure can be achieved by attaching a semiconductor die to an additional one or more semiconductor dies (ie, die-to-die (D2D)), A semiconductor die attaches to one or more semiconductor wafers (ie, die-to-wafer (D2W)), and attaches a semiconductor wafer to an additional one or more semiconductor wafers (ie, wafer-to-wafer Round (W2W)).

Typically, these individual semiconductor structures (e.g., dies or wafers) can be quite thin and difficult to handle with devices that process semiconductor construction. Thus, so-called "carrier" dies or wafers can be attached to the actual semiconductor construction in which the active and passive components of the semiconductor device are contained. The carrier dies or wafers typically do not contain any active or passive components of the semiconductor device to be formed. Such carrier dies or wafers are referred to herein as "carrier substrates." The carrier substrates increase the overall thickness of the semiconductor structures and facilitate processing of the semiconductor structures by the processing device (via providing structural support to the relatively thin semiconductor structures) for processing Attached to the active and/or passive components of the semiconductor structures, the semiconductor structures will include active and passive components of a semiconductor device to be fabricated thereon. In the present specification, such semiconductor constructions will ultimately comprise active and/or passive components of a semiconductor device to be fabricated thereon, or will eventually include an active semiconductor device to be fabricated thereon upon completion of the process And/or passive components, referred to as "device substrates."

Adhesion techniques for adhering a semiconductor structure to another semiconductor construction can be categorized in different ways, one way of classifying whether an intermediate material is provided between the two semiconductor structures to adhere them together, The two ways are to classify whether the bonding interface allows electrons (ie, current) to pass through the interface. By "direct adhesion method" is meant establishing a direct solid-to-solid chemical bond between two semiconductor structures to adhere them together without the need to bond them together using an intervening adhesion material between the semiconductor structures. The method. A direct metal-to-metal adhesion method has been developed to adhere a metal material of a surface of a first semiconductor structure to a metal material of a surface of a second semiconductor structure.

Direct metal-to-metal adhesion methods can also be classified according to the temperature range at which each method operates. For example, some direct metal-to-metal adhesion methods are performed at relatively high temperatures, thereby causing at least partial melting of the metallic material at the adhesion interface. Such direct adhesion processes may not be suitable for adhering processed semiconductor structures that include one or more device configurations, as their elevated temperatures may adversely affect the device configuration that was formed earlier.

The "hot press adhesion" method is at a high temperature between 200 degrees Celsius (200 ° C) and about 500 degrees Celsius (500 ° C), usually between about 300 degrees Celsius (300 ° C) and about 400 degrees Celsius (400 Between °C), a direct adhesion method that applies pressure between the adhesion surfaces.

Additional direct adhesion methods have been developed which can be carried out at temperatures of 200 degrees Celsius (200 ° C) or lower. For such direct adhesion processes performed at temperatures of 200 degrees Celsius (200 ° C) or lower, this specification is referred to as an "ultra-low temperature" direct adhesion process. The ultra-low temperature direct adhesion method can be carried out by carefully removing surface impurities and surface compounds (for example, native oxide layers), and by increasing the area of intimate contact between the two surfaces on an atomic scale. The area of intimate contact between the two surfaces is typically achieved by grinding the adhesion surfaces to reduce the surface roughness to a value close to the atomic scale, applying pressure between the adhesion surfaces to cause plastic deformation, or both grinding Some of the adhesive surfaces apply pressure to this plastic deformation.

Some ultra-low temperature direct adhesion methods may not require application of pressure at the adhesion interface between the adhesion surfaces, but in other ultra-low temperature direct adhesion methods, pressure may be applied at the adhesion interface between the adhesion surfaces to achieve a suitable interface at the adhesion interface. Adhesion strength. In the art to which the present invention pertains, an ultra-low temperature direct adhesion method for applying pressure between the adhesion surfaces is generally referred to as a "surface assisted adhesion" or "SAB" method. Therefore, in the present specification, "surface-assisted adhesion" and "SAB" mean and include a first material against a second material at a temperature of 200 degrees Celsius (200 ° C) or lower, and The adhesion interface between the adhesion surfaces applies pressure to cause the first material to adhere directly to any direct adhesion process of the second material.

The carrier substrate is typically attached to the device substrate using an adhesive. Similar adhesion methods can also be used to secure a semiconductor structure to another semiconductor structure that includes active and/or passive components of one or more semiconductor devices.

The electrical connections of the semiconductor die may not match the electrical connections of other semiconductor structures to which they are connected. An interposer (i.e., an additional configuration) can be placed between the two semiconductor structures or between any of the semiconductor dies and a semiconductor package for rewiring and aligning the appropriate electrical connections. The interposer can have one or more conductive traces and vias that are used to create proper contact between the desired semiconductor structures.

Embodiments of the present invention may provide methods and configurations for forming semiconductor devices having two or more semiconductor structures carried by a common substrate. An electrical connection can be provided between the two or more of the plurality of semiconductor structures through the common substrate. This Summary is provided to introduce a series of concepts in a simplified form, which are further described in detail in the embodiments of the present invention. This summary is not intended to identify key features or essential features of the claimed subject matter, and is not intended to limit the scope of the claimed subject matter.

In some embodiments, the invention includes a method of forming a semiconductor device. In accordance with such methods, a substrate can be provided which includes a layer of semiconductor material on a layer of electrically insulating material. A first metallization layer comprising a plurality of electrically conductive members may be formed on the first side of the layer of semiconductor material opposite the layer of electrically insulating material. A plurality of inter-wafer via connections are formed to at least partially pass through the substrate. At least one of the inter-wafer via connections may pass through the metallization layer and the layer of semiconductor material. A second metallization layer comprising a plurality of electrically conductive members may be formed on the substrate on a second side of the layer of semiconductor material opposite the first side of the layer of semiconductor material. Provided between the first processed semiconductor structure carried by the substrate on one of the first sides of the layer of semiconductor material, and by the substrate between one of the first processed semiconductor structures of the first side of the layer of semiconductor material (eg Forming an electrical path through the first metallization layer, the substrate, and the second metallization layer.

In additional embodiments, the invention includes semiconductor structures formed using the methods described herein. For example, in additional embodiments, the present invention comprises a semiconductor device comprising: a substrate comprising a layer of semiconductor material; a first metallization layer on the substrate, the first of the layers of semiconductor material And a second metallization layer on the substrate positioned on a second side of the layer of semiconductor material opposite the first side of the layer of semiconductor material. A plurality of wafers are connected to the semiconductor material at least partially through the first metallization layer and the substrate. A first processed semiconductor structure can be carried by the substrate on a first side of the layer of semiconductor material, and a second processed semiconductor structure can also be carried by the substrate on a first side of the layer of semiconductor material. At least one electrical path may be from the first processed semiconductor structure, through one of the first metallization layer conductive members, the inter-wafer via connections, one of the first inter-wafer via connections, the second metal One of the conductive layers and one of the inter-wafer via connections are electrically connected to the second wafer and extend to the second processed semiconductor structure.

The descriptions of the present invention are not intended to be an actual description of any particular material, device, system, or method, but are merely intended to describe an idealized representation of an embodiment of the invention.

The use of any headings in this specification is not intended to limit the scope of the embodiments of the invention, which is defined by the scope of the following claims and their legal equivalents. The concepts described under any particular heading also generally apply to the rest of the specification.

The disclosure is hereby incorporated by reference in its entirety for all purposes in the extent of the disclosure. In addition, the cited references, regardless of how the description describes the features of the invention, are not admitted as prior art.

In the present specification, the term "semiconductor device" means and includes any device containing one or more semiconductor materials, which can function as a device or system that is functionally integrated into an electronic or optoelectronic device. Item or multiple functions. Semiconductor devices include, but are not limited to, electronic signal processors, memory devices, such as random access memory (RAM), dynamic random access memory (DRAM), flash memory, etc., optoelectronic devices (eg, Light-emitting diodes, laser diodes, solar cells, etc., and devices comprising two or more such devices that are operatively coupled to each other.

In the present specification, the term "semiconductor construction" means and includes any configuration used or formed during the fabrication of a semiconductor device. Semiconductor structures include, for example, dies and wafers (eg, carrier substrates and device substrates), and combinations or composites of two or more dies and/or wafers that are stacked in a three-dimensional manner with each other. structure. The semiconductor construction also includes a fully assembled semiconductor device and an intermediate structure formed during fabrication of the semiconductor device.

In the present specification, the term "processed semiconductor construction" means and includes any semiconductor construction that includes at least one or more device configurations that have been partially formed. Processed semiconductors are constructed as a subset of semiconductor structures, all of which are semiconductor structures.

In the present specification, the term "adhesive semiconductor construction" means and includes any configuration containing two or more semiconductor structures attached together. Adhesive semiconductor structures are a subset of semiconductor structures, all of which are semiconductor structures. In addition, the bonded semiconductor construction comprising one or more processed semiconductor structures is also a processed semiconductor construction.

In the present specification, the term "device configuration" means and includes any portion of a processed semiconductor structure that is, contains, or defines at least a portion of an active or passive component of a semiconductor device to be Formed on or in the semiconductor structure. For example, the device configuration includes active and passive components of the integrated circuit, such as transistors, transducers, capacitors, resistors, conductive lines, conductive vias, and conductive contact pads.

In the present specification, the term "through-wafer via" or "TWI" refers to and includes any conductive via that passes through at least a portion of a first semiconductor structure that spans the first semiconductor structure and a second semiconductor. An interface between the structures to provide a structural and/or electrical interconnection between the first semiconductor structure and the second semiconductor structure. In the technical field of the present invention, there are other names for inter-wafer via connections, such as "through silicon vias/through substrate vias" or "TSV", and "wafers". Through wafer vias or TWV. The TWI typically passes through the semiconductor structure in a direction substantially perpendicular to one of the substantially planar major surfaces in a semiconductor structure (i.e., in a direction parallel to one of the "Z" axes).

In the present specification, the term "active surface" is used in relation to a processed semiconductor construction and refers to and includes one of the processed semiconductor constructions that exposes the major surface that has been treated or will be processed. So that one or more device configurations are formed in and/or on the exposed major surface of the processed semiconductor construction.

In the present specification, the term "metallization layer" means and includes a layer of a processed semiconductor structure comprising one or more of conductive lines, conductive vias, and conductive contact pads for use along At least a portion of an electrical path conducts current.

In the present specification, the term "back surface" is used in connection with a processed semiconductor construction and refers to and includes one of the treated semiconductor structures exposing a major surface that is active with one of the processed semiconductor structures. One side of the opposite side of the surface.

In this specification, the term "three-five semiconductor materials" means and includes most of one or more Group IIIA elements (B, Al, Ga, In, and Ti) in the periodic table and one or more VAs. Any material of a family element (N, P, As, Sb, and Bi).

Embodiments of the invention include methods and configurations for forming semiconductor structures, and more particularly semiconductor structures including bonded semiconductor structures, and methods of forming such bonded semiconductor structures.

In some embodiments, the formed inter-wafer via bonding may pass through at least a portion of a semiconductor-on-insulator (SeOI) substrate, and one or more metallization layers formed may cover at least the SeOI substrate. portion. The processed semiconductor structure (eg, a semiconductor device) can be carried by at least a portion of the SeOI substrate, and the electrical paths between the processed semiconductor structures (and, optionally, other structures or substrates) can utilize The conductive members of the metallization layer and the wafers are connected by a transparent connection. Embodiments of the methods and configurations of the present invention may be employed for different purposes, such as for a three dimensional spatial accumulation process and for forming a three dimensional spatial accumulation configuration.

Figure 1 presents one of the substrates that may be employed in embodiments of the present invention. The substrate 100 comprises a relatively thin layer of semiconductor material 104. In some embodiments, the layer of semiconductor material 104 can be at least substantially a single crystalline semiconductor material.

As an example of non-limiting properties, the layer of semiconductor material 104 may comprise a single crystal germanium, germanium, or a tri-five semiconductor material, and may be doped or undoped. In some embodiments, the layer of semiconductor material 104 can comprise an epitaxial layer of one of the semiconductor materials.

In some embodiments, the average thickness of the layer of semiconductor material 104 can be about 1 micron (1 μm) or less, about 500 nanometers (500 nm) or less, or even about 10 nanometers (10 nm) or less. .

Alternatively, the layer of semiconductor material can be disposed over and carried by a substrate 106. As an example of non-limiting properties, the substrate 106 can include one or more dielectric materials such as an oxide (eg, yttrium oxide (SiO ₂ ) or aluminum oxide (Al ₂ O ₃ )), a nitride (eg, nitrogen). Plutonium (Si ₃ N ₄ ) or boron nitride (BN)) and the like. In additional embodiments, the substrate 106 can comprise a semiconductor material such as any of the above described with respect to the semiconductor material 104. In some embodiments, the substrate 106 can also include a multilayer construction comprising one or two different materials.

In some embodiments, the substrate 100 can comprise a substrate of the type known as "Semiconductor-on-Second (SeOI)" in the art to which the present invention pertains. For example, the substrate 100 can comprise a substrate of the type known as "SOI" in the art to which the present invention pertains. In such embodiments, a layer of electrically insulating material 105 may be disposed between the layer of semiconductor material 104 and a substrate 106. The electrically insulating material 105 can comprise a layer referred to as "embedded oxide (BOX)" in the art to which the present invention pertains. The electrically insulating material 105 may comprise, for example, a ceramic material such as a nitride such as tantalum nitride (Si ₃ N ₄ ) or an oxide such as hafnium oxide (SiO ₂ ) or aluminum oxide (Al ₂ O). ₃ )). In some embodiments, the average electrical thickness of the layer of electrically insulating material 105 can be about 1 micron (1 μm) or less, about 300 nanometers (300 nm) or less, or even about 10 nanometers ( 10 nm) or thinner.

As an example, one non-limiting nature, the substrate 1 shown in FIG. 100 may be applied in the technical field of the present invention referred to as SMART-CUT ^TM process are to be formed. For example, as shown in FIG. 2, a relatively thick layer of semiconductor material 104 ' can be adhered to one of the layers of electrically insulating material 105 to expose the major surface 107. The composition of the relatively thick semiconductor material 104 ' may be identical to the composition of the layer of semiconductor material 104 to be provided over the substrate 106, and the layer of semiconductor material 104 may be formed from the relatively thick semiconductor material 104 ' of the layer. And includes a relatively thin portion of the relatively thick semiconductor material 104 ' of the layer.

In some embodiments, an adhesive material (not shown) can be used to adhere the relatively thick semiconductor material 104 ' to the major surface 107 of the layer of electrically insulating material 105. Such an adhesive material may include, for example, one or more of cerium oxide, cerium nitride, and a mixture thereof. Such an adhesive material may be formed or otherwise provided to one or both of the layer of electrically insulating material 105 and the contiguous surface of the relatively thick semiconductor material 104 ' to enhance adhesion therebetween.

In some embodiments, the layer of relatively thick semiconductor material 104 ' can be adhered to the layer of electrically insulating material 105 at a temperature of about 400 ° C or less, or even at a temperature of about 350 ° C or less. However, in other embodiments, the adhesion process can be performed at higher temperatures.

After the relatively thick semiconductor material 104 ' is adhered to the layer of electrically insulating material 105, the relatively thick semiconductor material 104 ' can be thinned to form the relatively thin semiconductor material 104 of FIG. One portion 110 of the relatively thick semiconductor material 104 ' can be removed from the relatively thin semiconductor material 104, leaving the relatively thin semiconductor material 104 on the major surface 107 of the layer of electrically insulating material 105.

As an example of a non-limiting nature, SMART-CUT ^TM may be used in the process is relatively thick layer of semiconductor material 104 'of the portion 110 of the relatively thin semiconductor material 104, 105 of the substrate 106 and the separation layer of electrically insulating material. Such processes are detailed, for example, in U.S. Patent No. RE 39,484 (issued to Bruel on February 6, 2007), U.S. Patent No. 6,303,468 (issued to Aspar et al. on October 16, 2001), and U.S. Patent No. 6,335,258 (2002) Issued to Aspar et al. on January 1st, US Patent 6,756,286 (issued to Moriceau et al. on June 29, 2004), US Patent 6,809,044 (issued to Aspar et al. on October 26, 2004), and US Patent 6,946,365 The complete disclosure of these patents is hereby incorporated by reference in its entirety in its entirety in its entirety.

Briefly, a plurality of ions (e.g., one or more of a hydrogen ion, a helium ion, or an inert gas ion) can be implanted along the ion implantation plane 112 to the layer of semiconductor material 104 ' . In some embodiments, the ions may implant the layer of semiconductor material 104 ' before the layer of semiconductor material 104 ' is adhered to the layer of electrically insulating material 105 and the substrate 106.

The ions can be implanted in a direction substantially perpendicular to one of the layers of semiconductor material 104 ' . The skilled in the present invention are known in the art, carried by one of the plurality of ion implantation energy function when the layer of semiconductor material 104 'depth of ion implantation at least in part for some of the layer of semiconductor material 104'. In general, ions implanted at lower energies have a relatively shallow depth of implantation, and ions implanted at higher energies have a relatively deep implant depth.

The ions may be implanted into the layer of semiconductor material 104 ' at a predetermined energy selected to implant the ions into the layer of semiconductor material 104 ' to a desired depth. The ions may implant the layer of semiconductor material 104 ' before the layer of semiconductor material 104 ' is adhered to the layer of electrically insulating material 105 and the substrate 106. As a specific example of non-limiting properties, the ion implantation plane 112 can be disposed within the layer of semiconductor material 104 ' at a depth from the surface of the layer of semiconductor material 104 ' such that the layer is relatively thin. The average thickness falls within the range of about 1,000 nanometers (1,000 nm) to about 100 nanometers (10 nm). As is known in the art to which the present invention pertains, it is inevitable that at least some of the ions may be implanted at an undesired depth and as a surface from the layer of semiconductor material 104 ' (e.g., prior to adhesion) to the A plot of ion concentration as a function of depth within the layer of semiconductor material 104 ' may show a curve that is generally bell-shaped (symmetric or asymmetrical) having a maximum at the desired implant depth.

After implanting ions into the layer of semiconductor material 104 ' , the ions can define an ion implantation plane 112 (shown in phantom in Figure 2) within the layer of semiconductor material 104 ' . The ion implanter 112 may include the planar layer of semiconductor material 104 'or a layer within a zone, with the layer of semiconductor material 104' with the highest ion concentration plane within the alignment (e.g., around the center thereof). The ion implantation may be plane 112 'define a weakened region within illustrating, in a subsequent process, the layer of semiconductor material 104' in the layer of semiconductor material 104 may be split along weakened area or the peeling. For example, the layer of semiconductor material 104 ' can be heated to cause the layer of semiconductor material 104 ' to peel or cleave along the ion implantation plane 112. In some embodiments, the temperature of the layer of semiconductor material 104 ' may be maintained at about 400 ° C or less, or even about 350 ° C or less during the stripping process. However, in other embodiments, the stripping process can be performed at a higher temperature. Alternatively, a mechanical force may be applied to the layer of semiconductor material 104 ' to cause or assist in stripping the layer of semiconductor material 104 ' along the ion implantation plane 112.

In an additional embodiment, the relatively thin semiconductor material 104 can be adhered to the layer of electrically insulating material 105 and the substrate 106 via a relatively thick semiconductor material 104 ' (eg, a layer having an average thickness greater than about 100 microns). and then the substrate 106 from the side opposite to the relatively thick layer of semiconductor material 104 'thinning, is provided on top of the layer of electrically insulating material 105 and the substrate 106. For example, the 'exposed major surface of one material is removed, so that a relatively thick layer of semiconductor material 104' from the relatively thick layer of semiconductor material 104 is thinned. For example, a chemical process (such as a wet or dry chemical etching process), a mechanical process (such as a grinding or honing process), or a chemical mechanical polishing (CMP) process can be used to make the material relatively thick from the layer. The exposure of the semiconductor material 104 ' is primarily surface removed. In some embodiments, such processes can be carried out at temperatures of about 400 ° C or less, or even about 350 ° C or less. However, in other embodiments, such processes can be performed at higher temperatures.

In other embodiments, the relatively thin layer of semiconductor material 104 may be formed in situ on the surface 107 of the layer of electrically insulating material 105. For example, the substrate 100 of FIG. 1 can be formed by depositing a semiconductor material such as tantalum, polysilicon or amorphous germanium on a surface 107 of the layer of electrically insulating material 105 to a desired thickness. In some embodiments, the deposition process can be carried out at a temperature of about 400 ° C or less, or even about 350 ° C or less. For example, as is known in the art, a low temperature deposition process for forming a relatively thin layer of semiconductor material 104 can be practiced using a plasma enhanced chemical vapor deposition process. In other embodiments, however, the deposition process can be performed at higher temperatures.

In some embodiments, the substrate 100 of FIG. 1 can include a relatively small grain grade configuration. In other embodiments, the substrate 100 can include a relatively large wafer having an average diameter of about 100 mm or greater, about 300 mm or greater, or even about 400 mm or greater. In such embodiments, a plurality of processed semiconductor structures 120 can be fabricated in and on different regions of the substrate 100, as shown in the simplified schematic diagram of FIG. The processed semiconductor structures 120 can be arranged on the substrate 100 in a neat sequence or grid.

An example of a method of making the processed semiconductor structures 120 using the substrate 100 is described below with reference to Figures 4 and 5.

Referring to FIG. 4, a plurality of transistors 122 may be formed in and on selected regions of the layer of semiconductor material 104 that correspond to regions in which the processed semiconductor structure 120 (FIG. 3) is to be formed. The transistors 122 are outlined in Figure 4. As is known in the art, each of the transistors 122 includes a source region and a drain region separated by a channel region. The source, drain and channel regions may be formed in the layer of semiconductor material 104. A gate structure can be formed over the layer of semiconductor material 104 vertically above the source region and the channel region of the drain region. Although only three transistors 122 are shown in FIG. 4 for simplicity, in practice each processed semiconductor structure 120 may include thousands, millions, or even more transistors 122.

Referring to FIG. 5, a first metallization layer 124 can be formed on a first side of the layer of semiconductor material 104 opposite the layer of electrically insulating material 105. The first metallization layer 124 includes a plurality of conductive features 126. The conductive features 126 can include one or more of vertically extending conductive vias, horizontally extending conductive traces, and conductive contact pads. At least some of the conductive members 126 can be in electrical contact with corresponding components of the transistors 122, such as the source regions, the drain regions, and the gate structures of the transistors 122. The conductive members 126 can be formed from and include a metal. The first metallization layer 124 can be formed in a layer-by-layer process in which a plurality of metal layers and a dielectric material 125 are alternately deposited and patterned to form the conductive features. 126, the conductive features 126 can be embedded in and surrounded by a dielectric material 125. The conductive features 126 can be used to route or redistribute electrical paths from the locations of the different active components of the transistors 122 to other remote locations. Thus, in some embodiments, the first metallization layer 124 can comprise a redistribution layer (RDL) as referred to in the art to which the present invention pertains.

In the embodiment of FIG. 5, the conductive members 126 are formed in the first metallization layer 124. Above the regions where the transistors 122 have been formed in the substrate 100, the regions are generally referred to as active regions. However, it is not above the other regions of the substrate 100 that do not contain any of the transistors 122, which are commonly referred to as inactive regions.

Figures 6A through 6F illustrate the fabrication of one of the bonded semiconductor structures shown in Figure 6F, which includes two or more processed semiconductor structures (e.g., semiconductor devices) carried by a portion of the substrate 100. Moreover, the portion of the substrate 100 is used to provide a direct, continuous electrical path between two or more of the processed semiconductor structures through the portion of the substrate 100.

The method of the embodiments of the present invention may utilize the processed semiconductor construction 120 of FIG.

Referring next to FIG. 6A, a carrier substrate 140 can be selectively temporarily adhered to the exposed semiconductor structure of FIG. 5 in which one of the first metallization layers 124 exposes the major surface 128. The carrier substrate 140 can be used to facilitate handling of the semiconductor construction by a processing device in a subsequent process.

After the carrier substrate 140 is adhered to the first metallization layer 124, the substrate 106 of the substrate 100 and the layer of electrically insulating material 105 can be removed to form the configuration shown in FIG. 6B. The substrate 106 of the substrate 100 and the layer of electrically insulating material 105 may be processed by a chemical process (such as a wet or dry chemical etching process), a mechanical process (such as a grinding or honing process), or via a chemical machine. A grinding (CMP) process is removed.

After removing the substrate 106 and the layer of electrically insulating material 105, a plurality of inter-wafer via bonds 130 may be formed to pass at least partially through the layer of semiconductor material 104, at least partially through the dielectric material 125, and In the active device region, the configuration shown in Fig. 6C is formed. The inter-wafer via junctions 130 may be etched through the layer of semiconductor material 104, at least partially through the dielectric material 125, and at the vias or vias of the active device region, and then with one or more conductive A material such as copper or a copper alloy is formed by filling the holes or vias; or formed by any other method known in the art to which the present invention pertains. For example, one or more of the inter-wafer via bonds 130 can be formed and extend completely through the first metallization layer 124 and the layer of semiconductor material 104 to the carrier substrate 140. In one etching process for forming a plurality of holes or vias, the carrier substrate 140 can be used as an etch stop, which holes will eventually be filled with one or more conductive materials to form the holes. The inter-wafer is transparently connected 130. It should be noted that in some embodiments of the present invention, the conductive features 126 may also serve as an etch stop in an etching process for forming the vias or vias.

At least some of the inter-wafer via bonds 130 may contact the conductive features 126 of the first metallization layer 124 to make electrical contact with one or more of the active device components of the transistors 122.

As an example of non-limiting properties, one or more masking and etching processes can be used to form the vias or vias, and one or more of an electroless plating process and an electrolytic plating process can be used to conduct the conductive The material fills in the holes or through holes. In some embodiments, each of the processes for forming the inter-wafer via bonds 130 includes forming the holes or vias and filling the holes or vias with conductive materials. It is carried out at a temperature of 400 ° C or lower, or even 350 ° C or lower. However, in other embodiments, such processes can be performed at higher temperatures. For example, in some embodiments, when copper can be used in forming the inter-wafer via-back of line (BEOL) process, the temperature must not exceed about 400 ° C, and the other In some instances, when aluminum can be used in a BEOL process for forming a through-wafer via joint, the temperature can exceed about 400 °C.

Referring to FIG. 6D, after the substrate 106 and the layer of electrically insulating material 105 are removed and the holes or vias are defined, a second metallization layer 154 can be formed on the second layer of the semiconductor material 104. The second side is opposite the first side of the layer of semiconductor material 104 formed by the first metallization layer 124. The angle of FIG. 6D is inverted relative to the angles of FIGS. 6A through 6C because the configuration may be reversed to facilitate formation of the second metallization layer 154 on the second side of the layer of semiconductor material 104.

The second metallization layer 154 is similar to the first metallization layer 124 and also includes a plurality of conductive features 156. The conductive features 156 can include one or more of vertically extending conductive vias, horizontally extending conductive traces, and conductive contact pads. At least some of the conductive members 156 can be in electrical contact with the inter-wafer vias 130, such as the conductive members 126 of the first metallization layer 124 and the active regions of the transistors 122, such as sources. The pole zone, the bungee zone and the gate structure also have electrical contact. The conductive members 156 can be formed from and include a metal. Like the first metallization layer 124, the second metallization layer 154 can be formed in a layer-by-layer process, such as by a well-known damascene process in which multiple layers of metal and dielectric material are alternately deposited and Patterns are formed to form the conductive features 156 that may be embedded within and surrounded by a dielectric material. The conductive features 156 can be used to route or redistribute electrical paths from the second side of the layer of semiconductor material 104 to other remote locations from where the inter-wafer vias 130 are exposed. Thus, in some embodiments, the second metallization layer 154 can comprise a redistribution layer (RDL) as referred to in the art to which the present invention pertains.

In addition, as shown in FIG. 6D, some of the conductive members 156 of the second metallization layer 154 may pass through the second metallization layer 154, and the inter-wafer via bonds 130 are exposed to the layer of semiconductor material. A direct, continuous electrical connection is provided between two or more of the end faces of the second side of 104.

Figure 6E shows that the semiconductor construction is again inverted such that the second metallization layer 154 is at the bottom of the semiconductor construction (from the perspective of Figure 6D). After the conductive features 156 of the second metallization layer 154 are formed, portions of the dielectric material 125 in the first metallization layer 124 can be removed. The regions of the first metallization layer 124 to be removed may include dielectric material 125 in the inactive regions, that is, dielectric material 125 in the regions without active devices. The dielectric material 125 can be removed via an etching process such as dry etching (eg, reactive ion etching) or wet etching. To remove the dielectric material 125 in the inactive region of the processed semiconductor construction, the processed configuration shown in FIG. 6D can be separated from the carrier substrate 140 and attached to an additional carrier (not shown) ). The additional carrier can be attached to the second metallization layer 154. After the dielectric material 125 is removed from the inactive regions of the processed semiconductor structure, the vias 156' of the second metallization layer 154 are exposed, as shown in FIG. 6E.

After removing a portion of the dielectric material 125 and exposing the vias 156', the processed semiconductor structure of FIG. 6E can be diced into dies. In addition, the die can be a known good (KGD) that has been electrically tested and mounted on a package using bump technology. Next, additional dies (made with similar or different functionality or using similar or different techniques) can be stacked on top of the interposer of Figure 6E using micro-bump techniques on the active devices ( That is, the active area) and the non-active device (that is, the non-active area).

It should be noted that an insulator-on-insulator (SOI) interposer employed in embodiments of the present invention facilitates providing a fan that is generally required to match electrical wiring between the interposer and the device package in a cost effective manner. Out (or redistribute) the layer. The common practice of shrinking the package wiring to match the device wiring greatly increases the cost of the device package. In addition, the SOI interposer provides inactive regions that may be stacked with other dies (or other die stacks) fabricated using similar or different techniques and coupled to the package through the same electrical wiring.

Thus, in detail, at this stage of the process, one or more processed semiconductor structures 120 have been formed in situ on the layer of semiconductor material 104 of the substrate 100 (i.e., the remaining portion of the substrate 100) Above and below, as shown in Figure 6E. These processed semiconductor structures 120 are carried by the layer of semiconductor material 104. The one or more processed semiconductor structures 120 can include, for example, an electronic signal processor, an electronic memory device, and/or an optoelectronic device (eg, a light emitting diode, a laser diode, a solar cell, etc.).

Referring to FIG. 6F, an additional one or more processed semiconductor structures, such as the processed semiconductor structure 160A and the processed semiconductor structure 160B, may be structurally and electrically coupled to the first side of the layer of semiconductor material 104. The exposed end faces of the inter-wafer vias 130 and the vias 156' are formed to form the bonded semiconductor structure shown in FIG. 6F. The plurality of additional processed semiconductor structure 160A, 160B may be formed on the layer of semiconductor material 104 and in place of the processed semiconductor structure 120 carried by one of the surface layer of semiconductor material 104 together.

Each of the additional processed semiconductor structures 160A, 160B can include a semiconductor device such as an electronic signal processor, an electronic memory device, and/or an optoelectronic device (eg, a light emitting diode, a laser diode) Body, a solar cell, etc.). As an example of a non-limiting nature, the in situ formed processed semiconductor structure 120 can include an electronic signal processor device, and each additional processed semiconductor structure 160A, 160B can include an electronic memory device, a light emitting diode At least one of a body, a laser diode, and a solar cell.

In some embodiments, additional conductive features of the processed semiconductor structures 160A, 160B, such as conductive pads, may be structurally and electrically coupled to individual crystals using, for example, conductive solder bumps or microspheres 162. The inter-circle through connection 130 and the through hole 156 are known in the art to which the present invention pertains. Additionally, the additional processed semiconductor structures 160A and 160B can include interposers and electrical wiring structures fabricated by the methods of the present invention as described above.

One or more electrical paths may be provided to the processed semiconductor structure 120 by electrically coupling the additional processed semiconductor structures 160A, 160B to the inter-wafer via junctions 130 and vias 156'. Between each additional processed semiconductor structure 160A, 160B, the electrical paths continuously pass through the first metallization layer 124, the remaining portion of the substrate 100 (ie, via the inter-wafer via junctions 130) And the via 156' passes through the layer of semiconductor material 104) and the second metallization layer 154. These electrical paths can be used to transfer electronic signals and/or power between the processed semiconductor structures 120, 160A, 160B. Thus, the processed semiconductor structures 120, 160A, 160B can be designed and organized to operate as a single semiconductor package.

As also shown in FIG. 6F, the electrically conductive member 156 of the second metallization layer 154 can be structurally and electrically coupled to another higher level configuration, such as another substrate 170, the electrically conductive member. The substrate 170 can include, for example, an organic printed circuit board, and can also include a package grade substrate. The conductive features 156 of the second metallization layer 154 can be structurally and electrically coupled to the conductive features of the substrate 170, such as by conductive solder bumps or solder balls 172, as in the art to which the present invention pertains. know. The electrical path may also be provided to the processed semiconductor structures 120 via the first metallization layer 124, the inter-wafer via bonds 130, and the second metallization layer 154 to the conductive features of the additional substrate 170. Between 160A and 160B, such additional electrical paths may also be used to transfer electrical and/or electronic signals between the processed semiconductor structures.

Figures 7A through 7F are similar to Figures 6A through 6F and are used to present additional embodiments of the method of the present invention that can be used to form an adherent semiconductor construction comprising two of the structures carried by the configuration of Figure 5. One or more processed semiconductor constructions. However, in the embodiment of Figures 7A through 7F, the layer of electrically insulating material 105 of the substrate 100 is not removed during processing as in the embodiment of Figures 6A through 6F. The process of the method of Figures 7A through 7F is generally the same as that described above with respect to Figures 6A through 6F, and thus the details already described above are not repeated below.

The method of the additional embodiment of the present invention may again use the processed semiconductor construction 120 as shown in Figure 7A.

As shown in FIG. 7B, a carrier substrate 140 can be selectively temporarily adhered to one of the first metallization layers 124 to expose the major surface 128. After the carrier substrate 140 is adhered to the first metallization layer 124, the substrate 106 of the substrate 100 can be removed from the structure, leaving the layer of semiconductor material 104 and the layer of electrically insulating material 105. A plurality of inter-wafer via junctions 130 may be formed and passed through the first metallization layer 124, the layer of semiconductor material 104, and the layer of electrically insulating material 105 to form the configuration shown in FIG. 7C. In such methods, the carrier substrate 140 can be used as an etch stop in an etch process for forming a plurality of holes or vias that will ultimately be one or more conductive materials. Filling to form the inter-wafer via junctions 130.

Referring to FIG. 7D, a second metallization layer 154 may be formed over the second side of the layer of semiconductor material 104, the second side of which is the first layer of semiconductor material 104 having the first metallization layer 124 formed thereon. The opposite side of the other side. In other words, the second metallization layer 154 can be formed over the layer of electrically insulating material 105. With respect to the angles of Figures 7A through 7C, the angle of Figure 7D is inverted because the configuration may be reversed to facilitate the formation of the second metallization layer 154. The second metallization layer 154 is similar to the first metallization layer 124 and also includes a plurality of conductive features 156 as described herein.

Figure 7E shows that the semiconductor construction is again inverted such that the second metallization layer 154 is at the bottom of the semiconductor construction (from the perspective of Figure 7D). As shown in FIG. 7E, portions of the first metallization layer 124 and the carrier substrate 140 can be removed. For example, the region of the first metallization layer 124 that covers the layer of semiconductor material 104 but does not include any of the transistors 122 can be removed, that is, the dielectric material 125 is removed from the inactive region of the processed semiconductor structure. The dielectric material 125 can be removed via an etching process such as dry etching (eg, reactive ion etching) or wet etching. To remove the dielectric material 125 in the inactive region of the processed semiconductor construction, the processed configuration shown in FIG. 7D can be separated from the carrier substrate 140 and attached to an additional carrier (not shown) ). The additional carrier can be attached to the second metallization layer 154. After the dielectric material 125 is removed from the inactive regions of the processed semiconductor structure, the vias 156' of the second metallization layer 154 are exposed, as shown in Figure 7E.

At this stage of the process, one or more processed semiconductor structures 120 have been formed in situ on and in the layer of semiconductor material 104 remaining in the portion of the substrate 100. The processed semiconductor construction of Figure 7E can be diced into dies (and the carrier can be removed). In addition, the die can be a known good (KGD) that has been electrically tested and mounted on a package using bump technology. Next, additional dies (made with similar or different functionality or using similar or different techniques) can be stacked on top of the interposer of Figure 7E using microbumping techniques, in the active devices (ie active regions) And above the non-active device (ie, the inactive area).

Referring to FIG. 7F, an additional one or more processed semiconductor structures, such as the processed semiconductor structure 160A and the processed semiconductor structure 160B, may be structurally and electrically coupled to the first side of the layer of semiconductor material 104. The exposed end faces of the inter-wafer via 130 and the vias 156' are formed to form the bonded semiconductor structure shown in FIG. 7F.

One or more electrical paths may be provided to the processed semiconductor structure 120 by electrically coupling the additional processed semiconductor structures 160A, 160B to the inter-wafer via junctions 130 and vias 156'. Between each additional processed semiconductor structure 160A, 160B, the electrical paths continuously pass through the first metallization layer 124, the remaining portion of the substrate 100 (ie, via the inter-wafer via junctions 130) And the via 156' passes through the layer of semiconductor material 104 and the layer of electrically insulating material 105), and the second metallization layer 154. These electrical paths can be used to transfer power and/or electronic signals between the processed semiconductor structures 120, 160A, 160B.

As also shown in FIG. 7F, the conductive features 156 of the second metallization layer 154 can be structurally and electrically coupled to another higher level configuration, such as another substrate 170, the conductive features. The electrical path may also pass through the first metallization layer 124, the inter-wafer via connections 130, The second metallization layer 154 to the conductive features of the additional substrate 170 are provided between the processed semiconductor structures 120, 160A, 160B, and such additional electrical paths may also be used in the processed semiconductor structures. Power and/or electronic signals are passed between.

In still other embodiments of the method of the present invention, the first metallization layer 124 can include an additional conductive feature 126 in a region that does not correspond to the formation of the processed semiconductor structure in situ, and the first metallization layer These areas do not have to be removed during processing.

For example, FIG. 8 is similar to FIG. 5 in that it presents a first metallization layer 124 ′ that may be formed on one of the first faces of the layer of semiconductor material 104 opposite the layer of electrically insulating material 105 . In the embodiment of FIG. 8, a plurality of conductive features 126 are formed in the first metallization layer 124' above the region where the transistor 122 has been formed in the substrate 100, and additional conductive features 126 are formed therein. The substrate 100 does not contain any other areas of the transistor 122 above it.

9A to 9F illustrate a method of forming an adhesion semiconductor, which is as described above with reference to FIGS. 6A to 6F, but using the configuration including the first metallization layer 124' shown in FIG. 8, instead of FIG. The structure of the display. The process of the method of Figures 9A through 9F is generally the same as that described above with respect to Figures 6A through 6F, and thus the details already described above are not repeated below.

Referring to FIG. 9A, a plurality of inter-wafer via junctions 130 may be formed and extend through the first metallization layer 124 ' and the layer of semiconductor material 104 to the layer of electrically insulating material 105. In such methods, the layer of electrically insulating material 105 can be used as an etch stop in an etch process for forming a plurality of vias or vias that will eventually be one or more conductive. The material is filled to form the inter-wafer via junctions 130.

As shown in FIG. 9B, after the inter-wafer via bonds 130 are formed through the first metallization layer 124 ' and the layer of semiconductor material 104, a carrier substrate 140 can be selectively temporarily adhered to the first One of the metallization layers 124 ' exposes the major surface 128. After the carrier substrate 140 is adhered to the first metallization layer 124 ' , the substrate 106 of the substrate 100 and the layer of electrically insulating material 105 can be removed from the structure, leaving the layer of semiconductor material 104 to form a pattern. The structure shown in 9C.

It should be noted that the semiconductor structure presented in FIG. 9C can also be fabricated in another manner by mounting the semiconductor structure of FIG. 8 on a carrier substrate and by grinding and polishing one or more of the layers. The semiconductor material 104 and the layer of electrically insulating material 105 are removed. Subsequent processes may define the inter-wafer via junctions 130 that pass through the semiconductor layer 104 and into the first metallization layer 124'.

Referring to FIG. 9D, a second metallization layer 154 may be formed on a second side of the layer of semiconductor material 104, the second side being the layer of semiconductor material 104 having the first metallization layer 124 ' formed thereon. The opposite side of the first side. With respect to the angles of Figures 9A through 9C, the angle of Figure 9D is inverted because the configuration may be reversed to facilitate the formation of the second metallization layer 154. The second metallization layer 154 is similar to the first metallization layer 124 ' and also includes a plurality of conductive features 156 as previously described.

Figure 9E shows that the semiconductor construction is again inverted such that the second metallization layer 154 is at the bottom of the semiconductor construction (from the perspective of Figure 9E). The carrier substrate 140 can be removed as shown in Figure 9E. However, the region of the first metallization layer 124 ' that covers the layer of semiconductor material 104 but does not include any of the transistors 122 may be removed without the prior art embodiments. At this stage of the process, one or more processed semiconductor structures 120 have been formed in situ on and in the layer of semiconductor material 104 remaining in the portion of the substrate 100.

At this stage of the process, the processed semiconductor structure of Figure 9E can be diced into dies (and the carrier can be removed). In addition, the die can be a known good (KGD) that has been electrically tested and mounted on a package using bump technology. Next, additional dies (made with similar or different functionality or using similar or different techniques) can be stacked on top of the interposer of Figure 9E using microbumping techniques, in the active devices (ie active regions) And above the non-active device (ie, the inactive area).

Thus, in particular, referring to FIG. 9F, an additional one or more processed semiconductor structures, such as the processed semiconductor structure 160A, the processed semiconductor structure 160B, and a processed semiconductor structure 160C, may be The exposed major surface of the first metallization layer 124 ' is electrically coupled to the exposed end faces of the inter-wafer via junction 130 to form the bonded semiconductor construction shown in FIG. 9F. The additional processed semiconductor construction 160C can include any of the types of processed semiconductor constructions described above in connection with the additional processed semiconductor structures 160A and 160B. After being configured in this manner, the electrical path can be provided to the processed semiconductor structures 120 through the first metallization layer 124 ′ , the inter-wafer via junctions 130 , and the second metallization layer 154 . Between 160A, 160B, 160C, the electrical paths can be used to transfer power and/or electronic signals between the processed semiconductor structures.

As also shown in FIG. 9F, the conductive features 156 of the second metallization layer 154 can be structurally and electrically coupled to another higher level configuration, such as another substrate 170, as described above. . The electrical path may also be provided to the processed semiconductor structures 120 via the first metallization layer 124 ′ , the inter-wafer via junctions 130 , and the second metallization layer 154 to the conductive features of the additional substrate 170 . Between 160A, 160B, 160C, such additional electrical paths may also be used to transfer electrical and/or electronic signals between the processed semiconductor structures.

10A through 10F illustrate a method of forming an adhesion semiconductor, as described above with reference to FIGS. 7A through 7F, but using the configuration of the first metallization layer 124 ' shown in FIG. 8, instead of FIG. The structure of the display. The processes of the methods of Figures 10A through 10F are generally the same as those described above with respect to Figures 6A through 6F and 7A through 7F, and thus the details already described above are not repeated below.

Referring to FIG. 10A, a plurality of inter-wafer via junctions 130 may be formed and extend through the first metallization layer 124 ' , the layer of semiconductor material 104, and the layer of electrically insulating material 105 to the substrate 106. In such methods, the substrate 106 can be used as an etch stop in an etch process for forming a plurality of vias or vias that will eventually be filled with one or more conductive materials. The inter-wafer via junctions 130 are formed.

As shown in FIG. 10B, after the inter-wafer via junction 130 is formed through the first metallization layer 124 ' , the layer of semiconductor material 104, and the layer of electrically insulating material 105, a carrier substrate 140 can be selectively selected. Temporarily adhered to one of the first metallization layers 124 ' to expose the major surface 128. After the carrier substrate 140 is adhered to the first metallization layer 124 ' , the substrate 106 of the substrate 100 can be removed from the structure, leaving the layer of semiconductor material 104 and the layer of electrically insulating material 105 to form a pattern. The structure shown in 10C.

It should be noted that the semiconductor structure presented in FIG. 10C can also be fabricated in another manner by mounting the semiconductor structure of FIG. 8 on a carrier substrate and by grinding and polishing one or more of the layers. The semiconductor material 104 is removed. Subsequent processes may define the inter-wafer via junctions 130 that pass through the layer of electrically insulating material 105 and the semiconductor layer 104 and into the first metallization layer 124'.

Referring to FIG. 10D, a second metallization layer 154 may be formed on a second side of the layer of semiconductor material 104, the second side being the layer of semiconductor material 104 having the first metallization layer 124 ' formed thereon. The opposite side of the first side. In other words, the second metallization layer 154 can be formed on one side of the layer of electrically insulating material 105 opposite the layer of semiconductor material 104. With respect to the angles of Figures 10A through 10C, the angle of Figure 10D is inverted because the configuration may be reversed to facilitate the formation of the second metallization layer 154. The second metallization layer 154 is similar to the first metallization layer 124 ' and also includes a plurality of conductive features 156 as previously described.

Figure 10E shows that the semiconductor construction is again inverted such that the second metallization layer 154 is at the bottom of the semiconductor construction (from the perspective of Figure 10E). As shown in Figure 10E, the carrier substrate 140 can be removed. However, the region of the first metallization layer 124 ' that covers the layer of semiconductor material 104 but does not include any of the transistors 122 may not necessarily be removed as in the prior embodiments described with reference to Figures 6A through 6F and 7A through 7F. At this stage of the process, one or more processed semiconductor structures 120 have been formed in situ on and in the layer of semiconductor material 104 remaining in the portion of the substrate 100.

At this stage of the process, the processed semiconductor structure of Figure 10E can be diced into dies. In addition, the die can be a known good (KGD) that has been electrically tested and mounted on a package using bump technology. Next, additional dies (made with similar or different functionality or using similar or different techniques) can be stacked on top of the interposer of Figure 10E using microbumping techniques, in the active devices (ie active regions) And above the non-active device (ie, the inactive area).

Thus, in particular, referring to FIG. 10F, an additional one or more processed semiconductor structures, such as the processed semiconductor structure 160A, the processed semiconductor structure 160B, and the processed semiconductor structure 160C, may be The exposed major surface of the first metallization layer 124 ' is electrically coupled to the exposed end faces of the inter-wafer via junction 130 to form the bonded semiconductor structure shown in FIG. 10F. Thus, the electrical path can be provided to the processed semiconductor structures 120, 160A, 160B, 160C through the first metallization layer 124 ' , the inter-wafer via junctions 130, and the second metallization layer 154. The electrical paths can be used to transfer electrical and/or electronic signals between the processed semiconductor structures.

As also shown in FIG. 10F, the electrically conductive member 156 of the second metallization layer 154 can be structurally and electrically coupled to another higher level configuration, such as another substrate 170, as described above. . The electrical path may also be provided to the processed semiconductor structures via the first metallization layer 124 ′ , the inter-wafer via junctions 130 , and the second metallization layer 154 to the conductive features of the additional substrate 170 . Between 120, 160A, 160B, 160C, such additional electrical paths may also be used to transfer electrical and/or electronic signals between the processed semiconductor structures.

In the above embodiments, the additional conductive features (such as conductive pads) of the processed semiconductor structures 160A, 160B, 160C utilize the conductive microbumps or microspheres 162 to be structurally and electrically coupled. The through-wafer vias 130 and 130' are connected to the wafers. Similarly, the conductive features 156 of the second metallization layer 154 are structurally and electrically coupled to the conductive features of the additional substrate 170 using conductive solder bumps or solder balls 172. In additional embodiments of the present invention, the additional conductive features of the processed semiconductor structures 160A, 160B, 160C may be metal-to-metal direct adhesion processes, structurally and electrically coupled to the inter-wafer via connections. 130. Likewise, the conductive features 156 of the second metallization layer 154 can be structurally and electrically coupled to the conductive features of the additional substrate 170 using a metal-to-metal direct adhesion process. It should be noted that the direct adhesion method has a reduced bonding pitch as compared to the microbump technique described in this specification and can be applied to additional embodiments of the present invention. This reduced joint spacing allows for a higher input/output (I/O) density between the adhesive device configurations.

For example, Figure 11 presents an embodiment of an adhesive semiconductor construction similar to that of Figure 10F, but with a metal-to-metal direct adhesion process in Figure 11 to add additional processed semiconductor structures 160A, 160B, 160C. A conductive member is adhered to the inter-wafer via junctions 130 and the conductive features 156 of the second metallization layer 154 are adhered to the conductive features of the additional substrate 170. These direct adhesion processes can also be used to form an adherent semiconductor construction as shown in Figures 6F, 7F and 9F.

In some embodiments of the invention, the metal-to-metal direct adhesion processes can be performed at temperatures below about 400 ° C, or even below about 350 ° C, to avoid processing the processed semiconductor structures 120. Any of the device configurations of 160A, 160B, 160C cause thermal damage. In some embodiments, the adhesion processes may include an ultra-low temperature direct adhesion process, and may also include a surface assisted direct adhesion process, such as those previously defined in this specification.

As another example, FIG. 12 presents an embodiment of an adhesive semiconductor construction similar to that of FIG. 7F, but using an oxide-to-oxide direct adhesion process in FIG. 12 to add additional processed semiconductor structures 160A, 160B. Adhered to the layer of electrically insulating material 105. As in FIG. 11, a metal-to-metal direct adhesion process can be used to adhere the conductive features 156 of the second metallization layer 154 to the conductive features of the additional substrate 170. A method similar to that described above with reference to Figures 7A through 7F but with minor modifications may be used to form the bonded semiconductor construction of Figure 12. For example, to form the bonded semiconductor construction of Figure 12, portions of the first metallization layer 124 can be removed as previously described with reference to Figure 7E. However, the processes can also be used to remove portions of the layer of semiconductor material 104 in such regions to expose the layer of electrically insulating material 105 (which can be formed to include an oxide). Then, the additional processed semiconductor structures 160A, 160B can be directly adhered to the layer of electrical insulating material 105 in one process of direct oxide-to-oxide adhesion. In addition, at least the inter-wafer via junctions 130 to be coupled to the additional processed semiconductor structures 160A, 160B may be formed in addition to the processed semiconductor structures 160A, 160B in an oxide pair. After one of the oxide direct adhesion processes adheres to the layer of electrically insulating material 105, and before the second metallization layer 154 is formed. Forming the inter-wafer via junctions 130 after the direct adhesion process can be improved between the inter-wafer via junctions 130 and the additional conductive features of the additional processed semiconductor structures 160A, 160B coupled thereto The quality of the electrical connection.

In some embodiments of the invention, the oxide-to-oxide direct adhesion process can be performed at temperatures below about 400 ° C, or even below about 350 ° C, to avoid processing the processed semiconductor structures. Any device configuration in 120, 160A, 160B causes thermal damage. In some embodiments, the adhesion processes may include an ultra-low temperature direct adhesion process, and may also include a surface assisted direct adhesion process, such as those previously defined in this specification.

A similar oxide to oxide direct adhesion process can also be used to form the bonded semiconductor construction as shown in Figures 6F, 9F and 10F.

Embodiments of the present invention can be used to provide a direct, continuous electrical path between a plurality of processed semiconductor structures carried by at least a portion of a SeOI type substrate, the electrical paths only passing through the same type of SeOI At least a portion of the substrate carries conductive features (eg, conductive pads, traces, and vias) without passing through another higher level substrate attached to at least a portion of the SeOI type substrate, such as The extra substrate 170, any part of it. These electrical paths are shorter than previously known fabrics and can improve signal speed and/or power efficiency.

Exemplary embodiments of additional non-limiting properties of the invention are recited below:

Embodiment 1 : A method of forming a semiconductor device, the method comprising: providing a substrate comprising a layer of semiconductor material on a layer of electrically insulating material; the substrate being opposite to the layer of electrically insulating material Forming a first metallization layer comprising one of a plurality of conductive members; forming a plurality of inter-wafer via connections to at least partially pass through the substrate, and forming the inter-wafer through Passing through at least one of the wafers through the metallization layer and the layer of semiconductor material; one of the layers of semiconductor material opposite the first side of the layer of semiconductor material on the substrate a second metallization layer comprising a plurality of electrically conductive members; and a first processed semiconductor structure carried by the substrate on a first side of the layer of semiconductor material and carried by the substrate to the layer of semiconductor A second processed semiconductor structure between the first side of the material provides an electrical path through the first metallization layer, the substrate, and the second metallization layer.

Embodiment 2: The method of Embodiment 1, wherein providing the substrate comprises selecting the substrate to comprise a semiconductor-on-insulator (SeOI) substrate.

Embodiment 3. The method of Embodiment 2 wherein the substrate is selected to comprise a semiconductor-on-insulator (SeOI) substrate comprising selecting the substrate to comprise a silicon-on-insulator (SOI) substrate.

The method of any one of embodiments 1 to 3, wherein the layer of semiconductor material has an average total thickness of about 1 micron or less, and wherein the layer of electrically insulating material comprises a layer of oxide material, the layer The oxide material has an average total thickness of about 300 nm or less.

The method of any one of embodiments 1 to 4, wherein forming at least one of the inter-wafer via bonds is formed through the metallization layer and the layer of semiconductor material The method includes forming a through-wafer via interconnect between the inter-wafer via bonds to pass through the layer of electrically insulating material.

The method of any one of embodiments 1 to 5, further comprising at least one of the first processed semiconductor structure and the second processed semiconductor structure on the first side of the layer of semiconductor material Adhered to the substrate.

Embodiment 7: The method of Embodiment 6, wherein at least one of the first processed semiconductor construction and the second processed semiconductor construction is adhered to the substrate on a first side of the layer of semiconductor material to be included in the metal pair In one of the processes of direct metal adhesion, at least one of the first processed semiconductor construction and the second processed semiconductor construction is directly adhered to the substrate at a temperature or temperatures less than about 400 °C.

The method of any one of embodiments 1 to 7, further comprising at least one of the first processed semiconductor structure and the second processed semiconductor structure on the first side of the layer of semiconductor material It is formed on the substrate in situ .

The method of any one of embodiments 1 to 8, wherein providing an electrical path further comprises structuring the electrical path through the at least one electrically conductive member of the first metallization layer, through the metallization And at least one inter-wafer via connection between the layer and the semiconductor material of the layer of semiconductor material, at least one conductive component of the second metallization layer, and at least one other of the inter-wafer via connections Inter-wafer connection.

The method of any one of embodiments 1 to 9, further comprising structurally and electrically joining the at least one electrically conductive member of the second metallization layer to one of the electrically conductive members of the other substrate.

The method of any one of embodiments 1 to 10, further comprising: consisting of an electronic signal processor device, an electronic memory device, an electromagnetic radiation emitter device, and an electromagnetic radiation receiver device The first processed semiconductor structure and the second processed semiconductor structure are each selected in the set.

Embodiment 12: The method of Embodiment 11, further comprising: selecting the first processed semiconductor structure to include an electronic signal processor device; and selecting the second processed semiconductor structure to include an electronic memory device, At least one of a light emitting diode, a laser diode, and a solar cell.

Embodiment 13: A semiconductor construction comprising: a substrate comprising a layer of semiconductor material; a first metallization layer on the substrate, the first surface of the layer of semiconductor material; the substrate a second metallization layer on a second side of one of the layers of semiconductor material opposite the first side of the layer of semiconductor material; a plurality of inter-wafer interconnects that at least partially pass through the first metallization layer And a layer of semiconductor material of the substrate; a first processed semiconductor structure carried by the substrate on a first side of the layer of semiconductor material; and a second processed semiconductor structure carried by the substrate a first side of the semiconductor material; wherein the electrical path passes from the first processed semiconductor structure through one of the first metallization layer conductive members, and the inter-wafer transparent connections are interconnected between the first wafers And electrically connecting one of the conductive members of the second metallization layer and the second wafer between the inter-wafer vias to the second processed semiconductor structure.

Embodiment 14: The semiconductor construction of Embodiment 13, wherein the substrate comprises a semiconductor-on-insulator (SeOI) substrate.

Embodiment 15: The semiconductor construction of Embodiment 14, wherein the semiconductor-on-insulator (SeOI) substrate comprises a silicon-on-insulator (SOI) substrate.

Embodiment 16: The semiconductor construction of Embodiment 14 or 15, wherein the layer of semiconductor material has an average total thickness of about 1 micron or less.

The semiconductor construction of any one of embodiments 14 to 16, wherein at least one of the inter-wafer via bonds is at least partially passed through a layer of electrically insulating material of the SeOI substrate.

The semiconductor construction of any one of embodiments 13 to 17, wherein at least one of the first processed semiconductor construction and the second processed semiconductor construction is adhered to the first side of the layer of semiconductor material to The substrate.

The semiconductor structure of embodiment 18, wherein at least one of the first processed semiconductor structure and the second processed semiconductor structure is directly adhered to the inter-wafer via junctions A wafer is connected through the gap.

The semiconductor construction of any one of embodiments 13 to 19, wherein the electrical path extends continuously between the first processed semiconductor construction and the second processed semiconductor construction, through the substrate, the a first metallization layer, and a second metallization layer.

The semiconductor construction of any one of embodiments 13 to 20, wherein the at least one electrically conductive component of the second metallization layer is electrically coupled to one of the electrically conductive components of the other substrate.

The semiconductor construction of any one of embodiments 13 to 21, wherein each of the first processed semiconductor structure and the second processed semiconductor structure comprises an electronic signal processor device, an electronic memory One of a device, an electromagnetic radiation emitter device, and an electromagnetic radiation receiver device.

Embodiment 23: The semiconductor construction of embodiment 22, wherein: the first processed semiconductor structure comprises an electronic signal processor device; and the second processed semiconductor structure comprises an electronic memory device, a light emitting diode, At least one of a laser diode and a solar cell.

The above described exemplary embodiments of the invention do not limit the scope of the invention. These examples are merely examples of embodiments of the invention, which are defined by the scope of the appended claims and their legal equivalents. Any equivalent embodiments are within the scope of the invention. For those skilled in the art to which the invention pertains, various modifications of the present disclosure, such as a substitute for the useful combinations of the elements, will become apparent from the description of the specification. . Such modifications are also intended to fall within the scope of the appended claims. The headings used in the present specification are provided for clarity and ease of understanding, and such titles do not limit the scope of the following claims.

100, 170. . . Substrate

104. . . semiconductors

105. . . Electrical insulation material

106. . . Base

107, 128. . . Main surface

110. . . Part of semiconductor materials

112. . . Ion implantation plane

120, 160A, 160B. . . Processed semiconductor construction

122. . . Transistor

124. . . First metallization layer

125. . . Dielectric material

126, 156. . . Conductive component

130. . . Transparent link

140. . . Carrier substrate

154. . . Second metallization layer

156’. . . Through hole

162. . . Microbump or microsphere

172. . . Bump or solder ball

Embodiments of the present invention can be more fully understood by reference to the following detailed description and appended claims.

1 is a simplified cross-sectional view of a semiconductor-on-insulator (SeOI) substrate that can be employed in embodiments of the method of the present invention;

Figure 2 is a simplified cross-sectional view showing a method that can be used to fabricate the SeOI substrate of Figure 1;

3 is a simplified top plan view of the SeOI substrate of FIG. 1 with an outline of a plurality of processed semiconductor structures on the substrate;

4 is a simplified cross-sectional view schematically showing a plurality of transistors formed in and on a layer of semiconductor material of the SeOI substrate of FIG. 1;

5 is a simplified cross-sectional view showing a first metallization layer formed over the plurality of transistors and a first side of the layer of semiconductor material of the SeOI substrate of FIG. 1;

6A through 6F are diagrams for presenting embodiments of the method of the present invention, which may be used to form a configuration comprising two or more processed semiconductor structures carried by the substrate of Figure 5, The method can be used to electrically interconnect at least two of the processed semiconductor structures;

FIG. 6A illustrates the fabrication of a through-wafer via connection between the wafers through the first metallization layer and the layer of semiconductor material of the SeOI substrate illustrated in FIG. 5;

Figure 6B is shown on the opposite side of the first metallization layer and the SeOI substrate, a carrier substrate is adhered to the first metallization layer;

Figure 6C shows that a portion of the SeOI substrate is removed to provide a see-through connection between the wafers through the substrate on a side opposite the carrier substrate;

6D is a side of the layer of semiconductor material of the SeOI substrate opposite to the first metallization layer, a second metallization layer is formed on the layer of semiconductor material;

Figure 6E shows the carrier substrate and other portions of the configuration shown in Figure 6D removed;

Figure 6F is presented on the first side of the layer of semiconductor material of the SeOI substrate, the additional processed semiconductor structure being adhered to and electrically coupled to the structure of Figure 6E, the figure being further presented in the layer of the SeOI substrate On the second side of the semiconductor material, the semiconductor structure is adhered and electrically coupled to another substrate;

Figures 7A through 7F are similar to Figures 6A through 6F and are used to present additional embodiments of the method of the present invention, which may be used to form a configuration comprising two or more of the substrates carried by Figure 5 The semiconductor construction has been processed, and the method can be used to electrically connect at least two of the processed semiconductor structures, wherein one layer of the SeOI substrate electrical insulation material is not removed during processing;

8 is similar to FIG. 5, showing a first metallization layer formed on the first surface of the semiconductor material above the transistor and the SeOI substrate of FIG. 1, including a SeOI substrate having no crystal formed thereon. region;

9A through 9F are similar to Figs. 6A through 6F for presenting additional embodiments of the method of the present invention, which may be used to form a configuration comprising two or more of the configurations carried by the configuration of Fig. 8. Processing semiconductor structures, and the methods can be used to electrically connect at least two of the processed semiconductor structures, wherein one layer of the SeOI substrate electrical insulation material is removed during processing;

Figures 10A through 10F are similar to Figures 9A through 9F and are used to present additional embodiments of the method of the present invention, which may be used to form a configuration comprising two or more of the configurations carried by the configuration of Figure 8. Processing semiconductor structures, and the methods can be used to electrically connect at least two of the processed semiconductor structures, wherein one layer of the SeOI substrate electrical insulation material is not removed during processing;

11 is a simplified cross-sectional view of a processed semiconductor structure similar to that presented in FIG. 10F, but showing a plurality of processed semiconductor structures directly attached to a first side of the SeOI substrate. a metallization layer, and another substrate directly adhered to a second metallization layer on the second side of the SeOI substrate;

Figure 12 is a simplified cross-sectional view of a processed semiconductor structure similar to that presented in Figure 7F, but showing a plurality of processed semiconductor structures directly attached to the first side of the SeOI substrate, and A substrate is directly adhered to a metallization layer on the second side of the SeOI substrate.

100, 170. . . Substrate

104. . . semiconductors

105. . . Electrical insulation material

106. . . Base

Claims (18)

A method of forming a semiconductor device, comprising: providing a substrate comprising a layer of semiconductor material on a layer of electrically insulating material; and one of the layers of semiconductor material opposite the layer of electrically insulating material on the substrate Forming, by the first surface, a first metallization layer comprising a plurality of conductive members; forming a plurality of inter-wafer via connections to at least partially pass through the substrate, and forming at least one of the inter-wafer via connections The circular space is transparently connected to pass through the metallization layer and the layer of semiconductor material; and the second surface of the layer of semiconductor material opposite to the first surface of the layer of semiconductor material is formed on the substrate to comprise a plurality of a second metallization layer of a conductive member; and a first processed semiconductor structure carried by the substrate on a first side of the layer of semiconductor material and carried by the substrate on a first side of the layer of semiconductor material A second processed semiconductor structure provides an electrical path through the first metallization layer, the substrate, and the second metallization layer. The method of claim 1, wherein forming at least one of the inter-wafer via bonds through the metallization layer and the layer of semiconductor material further comprises forming the inter-wafer At least one inter-wafer via joint in the through-connection is passed through the layer of electrically insulating material. The method of claim 1, further comprising adhering at least one of the first processed semiconductor structure and the second processed semiconductor structure to the substrate on a first side of the layer of semiconductor material. The method of claim 3, wherein at least one of the first processed semiconductor structure and the second processed semiconductor structure is adhered to the substrate on the first side of the layer of semiconductor material to be included in the metal to metal In one of the direct adhesion processes, at least one of the first processed semiconductor construction and the second processed semiconductor construction is directly adhered to the substrate at a temperature or temperatures less than about 400 °C. The method of claim 1, further comprising forming at least one of the first processed semiconductor structure and the second processed semiconductor structure in situ on the first side of the layer of semiconductor material on. The method of claim 1, wherein providing an electrical path further comprises structuring the electrical path through the at least one electrically conductive member of the first metallization layer, through the metallization layer, and the layer of semiconductor material The at least one inter-wafer via connection between the wafers, the at least one conductive member of the second metallization layer, and the at least one other of the inter-wafer via connections are transparently connected. The method of claim 1, further comprising structurally and electrically joining the at least one electrically conductive member of the second metallization layer to one of the electrically conductive members of the other substrate. The method of claim 1, further comprising selecting from the group consisting of an electronic signal processor device, an electronic memory device, an electromagnetic radiation transmitter device, and an electromagnetic radiation receiver device. The first processed semiconductor structure and the second processed semiconductor structure. The method of claim 8, further comprising selecting the first processed semiconductor structure to include an electronic signal processor device; and selecting the second processed semiconductor structure to include an electronic memory device, a light emitting At least one of a diode, a laser diode, and a solar cell. A semiconductor construction comprising: a substrate comprising a layer of semiconductor material; a first metallization layer on the substrate on a first side of the layer of semiconductor material; and a second metal on the substrate a layer on a second side of one of the layers of semiconductor material opposite the first side of the layer of semiconductor material; a plurality of inter-wafer interconnects that at least partially pass through the first metallization layer and the substrate a layer of semiconductor material; a first processed semiconductor structure carried by the substrate on a first side of the layer of semiconductor material; and a second processed semiconductor structure carried by the substrate on the layer of semiconductor material One of the electrical paths from the first processed semiconductor structure through one of the first metallization layer conductive members, the inter-wafer via connections, the first inter-wafer via connection, the second A conductive member of one of the metallization layers and one of the inter-wafer via connections are electrically connected to the second wafer and extend to the second processed semiconductor structure. The semiconductor construction of claim 10, wherein the substrate comprises a semiconductor-on-insulator (SeOI) substrate. The semiconductor structure of claim 11, wherein at least one of the inter-wafer via bonds is at least partially passed through a layer of electrically insulating material of the SeOI substrate. The semiconductor construction of claim 10, wherein at least one of the first processed semiconductor construction and the second processed semiconductor construction is adhered to the substrate on a first side of the layer of semiconductor material. The semiconductor structure of claim 13, wherein at least one of the first processed semiconductor structure and the second processed semiconductor structure is directly adhered to at least one of the inter-wafer via bonds Inter-wafer connection. The semiconductor structure of claim 10, wherein the electrical path extends continuously between the first processed semiconductor structure and the second processed semiconductor structure, through the substrate, the first metallization layer, and The second metallization layer. A semiconductor construction according to claim 10, wherein at least one of the electrically conductive members of the second metallization layer is electrically coupled to one of the electrically conductive members of the other substrate. The semiconductor structure of claim 10, wherein each of the first processed semiconductor structure and the second processed semiconductor structure comprises an electronic signal processor device, an electronic memory device, and an electromagnetic radiation emitter. A device, and one of an electromagnetic radiation receiver device. The semiconductor structure of claim 17, wherein: the first processed semiconductor structure comprises an electronic signal processor device; and the second processed semiconductor structure comprises an electronic memory device, a light emitting diode, and a lightning At least one of a diode and a solar cell.