FR2979167A1 - Forming bonded semiconductor structure, comprises e.g. forming through wafer interconnects through thin layer of material of first substrate structure, bonding processed semiconductor structure and electrically coupling conductive feature - Google Patents

Abstract

Forming bonded semiconductor structure (180), comprises: (a) providing first substrate structure (120) comprising thin layer of material on thick substrate body (104); (b) forming through wafer interconnects (112) through thin layer; (c) bonding processed semiconductor structure over thin layer and electrically coupling conductive feature of processed structure; (d) bonding second substrate structure (182) over processed structure; (e) removing substrate body and leaving thin layer; and (f) electrically coupling through wafer interconnect to conductive feature of another structure. Forming a bonded semiconductor structure (180), comprises: (a) providing a first substrate structure (120) comprising a relatively thin layer of material on a relatively thick substrate body (104); (b) forming many through wafer interconnects (112) through the thin layer of material of the first substrate structure; (c) bonding at least one processed semiconductor structure over the thin layer of material of the first substrate structure on side opposite the relatively thick substrate body and electrically coupling at least one conductive feature of the processed semiconductor structure with at least one through wafer interconnect of the many through wafer interconnects; (d) bonding a second substrate structure (182) over the processed semiconductor structure on side opposite the first substrate structure; (e) removing the thick substrate body of the first substrate structure and leaving the thin layer of material of the first substrate structure bonded to the processed semiconductor structure; and (f) electrically coupling at least one through wafer interconnect of the through wafer interconnects to a conductive feature of another structure. An independent claim is also included for an intermediate structure formed during fabrication of a bonded semiconductor structure, comprising: a first substrate structure comprising many through wafer interconnects extending through the thin layer of material, and a thick substrate body temporarily bonded to the layer of material; many processed semiconductor structures electrically coupled to the through wafer interconnects; and the second substrate structure temporarily bonded over the processed semiconductor structures on a side opposite the first substrate structure.

Description

Technical Field The present invention relates to methods of forming bonded semiconductor structures using three-dimensional (3D) integration techniques, and linked semiconductor structures formed by these methods. Background Three-dimensional (3D) integration of two or more semiconductor structures can bring a number of benefits in microelectronic applications. For example, three-dimensional integration of microelectronic components can result in improved electrical performance and power consumption while reducing the area of the device footprint. See, for example, P. Garrou, et al., "The Handbook of 3D Integration," Wiley-VCH (2008). The three-dimensional integration of semiconductor structures can be achieved by connecting a semiconductor chip to one or more additional semiconductor chips (i.e., chip chip (D2D)), a semiconductor chip having one or more semiconductor wafers (i.e., semiconductor wafer chip (D2W)), as well as a semiconductor wafer with one or more additional semiconductor wafers (i.e. semiconductor wafer (W2W)), or a combination thereof.

The bonding techniques used for bonding a semiconductor structure to another semiconductor structure can be classified in different ways, the first being that an intermediate material layer is provided between the two semiconductor structures to bond them to each other. the other, and the second being that the link interface allows electrons (i.e., an electric current) to pass through the interface. "Direct binding methods" are processes in which a solid-to-solid solid chemical bond is established between two semiconductor structures to bond to each other without using intermediate bonding material between the two semiconductor structures. to link them to each other. Direct metal-to-metal bonding methods have been developed for bonding a metal material on a surface of a first semiconductor structure to a metal material on a surface of a second semiconductor structure.

Metal-to-metal direct bonding methods can also be classified according to the temperature range in which each is performed. For example, some metal-to-metal direct bonding processes are performed at relatively high temperatures, resulting in at least partial melting of the metallic material at the bonding interface. These direct bonding processes may be undesirable for use in bonding treated semiconductor structures that include one or more device structures, since relatively high temperatures may adversely affect previously formed device structures. Thermocompression bonding methods are direct bonding methods in which pressure is applied between the bonding surfaces at high temperatures between 200 degrees Celsius (200 degrees C) and about 500 degrees Celsius (500 degrees Celsius). and often between about three hundred degrees Celsius (300 ° C) and about four hundred degrees Celsius (400 ° C). Additional direct link methods have been developed that can be performed at temperatures of 200 degrees Celsius (200 degrees Celsius) or less. These direct bonding processes performed at temperatures of 200 degrees Celsius (200 degrees Celsius) or less are referred to herein as "ultra-low temperature" direct bonding processes. Ultra-low temperature direct bonding processes can be carried out by carefully removing surface impurities and surface compounds (eg, native oxides), and increasing the area of close contact between the two surfaces. atomic scale. The close contact area between the two surfaces is generally achieved by polishing the bonding surfaces to reduce surface roughness to values near the atomic scale, applying pressure between the bonding surfaces, thereby This results in plastic deformation, or both polishing the bonding surfaces and applying pressure to achieve this plastic deformation. Some ultra low temperature direct bonding methods can be implemented without applying pressure between the bonding surfaces at the bonding interface, while pressure can be applied between the bonding surfaces at the bonding interface. link interface in other ultra-low temperature direct-link methods to obtain an appropriate link resistance at the link interface. Ultra-low temperature direct bonding processes in which pressure is applied between the bonding surfaces are often referred to in the art as "power assisted bonding" or "BSA" processes. Thus, as used herein, the terms "surface assisted bonding" and "SAB" refer to and include any direct bonding process in which a first material is directly bonded to a second material by placing the first material abutting against the second material and applying pressure between the bonding surfaces at the bonding interface at a temperature of two hundred degrees Celsius (200 ° C) or less. Silicon (Si) and glass substrates are generally perceived as basic substrates on which semiconductor devices can be fabricated to achieve high bandwidth performance, and for use in heterogeneous three-dimensional integration of first level. The interposers are generally planar structures that include layers of material, which are interposed between two or more different chips and / or semiconductor wafers in three-dimensional integration processes. The interposers are used in intermediate processing steps during a three-dimensional integrated circuit (3D-IC) integration. The main objectives for silicon interposers are the greatest need for high density package chip interconnects, thermal expansion coefficient (CTE) matching (for example, Si on Si), and greater scalability. implantation of passive devices (eg, resistors, inductors, etc.) in the interposer. For example, the interposers may incorporate vias through the substrate (TSV), as well as decoupling capacitors and voltage regulators. In addition, very small form factors can be obtained on a silicon interposition device. Generally, the silicon interposers are thinned after the formation of vias crossing the substrate (TSV) and redistribution layers (RDL) in and on the silicon interposers. These thinning processes often involve waste of expensive silicon. In addition, the interposers are usually thinned while the TSVs and RDL layers are filled with copper. A mechanical stress may develop in the interposing device after the manufacture of the TSV and RDL layers, and after the thinning of the interposition device. This constraint may cause the interposition device to buckle and may result in fracture or other mechanical damage to the interposition device. A veiled interposing device may also veil the fully tested chip (KGD) which can be mounted thereto, thereby significantly affecting the productivity of devices which can be implemented on or over the device. interposition. Brief summary This summary is provided to introduce a selection of concepts in a simplified form. These concepts are described in more detail in the detailed description of exemplary embodiments of the invention below. This summary is not intended to identify key features or essential characteristics of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

In some embodiments, the present disclosure includes three-dimensional integration techniques that utilize a recoverable substrate, and can provide solutions for overcoming the productivity-limiting challenges commonly encountered due to constraint development in the interposer devices. In addition, some embodiments may involve direct bonding techniques to enable low-temperature and low-pressure positioning and bonding of structures in three-dimensional integration processes. In some embodiments, the present invention includes methods of forming bonded semiconductor structures. According to these methods, a first substrate structure may be provided which includes a relatively thin layer of material on a relatively thick substrate body. A plurality of interconnects passing through the semiconductor wafer may be formed through the relatively thin layer of material of the first substrate structure. At least one treated semiconductor structure may be bonded to the relatively thin layer of material of the first substrate structure on one side thereof opposite the relatively thick substrate body, and at least one conductive characteristic of the at least one structure The treated semiconductor may be electrically coupled to at least one interconnection traversing the semiconductor wafer of the plurality of interconnects through the semiconductor wafer. A second substrate structure may be bonded to the at least one semiconductor structure processed on one side thereof opposite the first substrate structure. The relatively thick substrate body of the first substrate structure can be removed, leaving the relatively thin layer of material of the first substrate structure bonded to the at least one processed semiconductor structure. At least one interconnection traversing the semiconductor wafer of the plurality of interconnects through the semiconductor wafer may be electrically coupled to a conductive characteristic of another structure. In further embodiments, the present invention comprises linked semiconductor structures formed by methods as presented herein. For example, one embodiment of a linked semiconductor structure of the present invention may include a first substrate structure comprising a plurality of interconnects passing through the semiconductor wafer and extending through a relatively thin layer of material, and a relatively thick substrate body temporarily bonded to the layer of material. A plurality of processed semiconductor structures may be electrically coupled to the plurality of interconnects passing through the semiconductor wafer, and a second substrate structure may be temporarily bonded to the plurality of semiconductor structures processed on one side thereof. opposite to the first substrate structure. Brief Description of the Drawings Although the description ends with claims particularly showing and distinctly claiming what are considered embodiments of the invention, the advantages of the embodiments of the invention may be more readily established from describing certain exemplary embodiments of the invention when read in conjunction with the accompanying drawings, in which: FIGS. 1A-1L are simplified cross-sectional views of semiconductor structures and show formation of a structure bound semiconductor according to exemplary embodiments of the invention; Figs. 2A-2C are simplified cross-sectional views of semiconductor structures and are used to describe additional embodiments of linked semiconductor structure forming methods of the invention; and Figs. 3A-3D are simplified cross-sectional views of semiconductor structures and are used to further describe other embodiments of linked semiconductor structure forming methods of the invention.

Detailed Description The illustrations presented here are not considered actual views of a particular semiconductor structure, device, system, or process, but are merely idealized representations that are used to describe embodiments of the invention. The titles used herein should not be construed as limiting the scope of the embodiments of the invention as defined by the following claims and their legal equivalents. The concepts described in any specific title are generally applicable in other sections in the entire description.

As used herein, the term "semiconductor structure" refers to and includes any structure that is used for the formation of a semiconductor device. Semiconductor structures include, for example, chips and semiconductor wafers (for example, support substrates and device substrates), as well as composite assemblies or structures that include two chips and / or semiconductor wafers. or more integrated three-dimensionally to each other. Semiconductor structures also include fully-manufactured semiconductor devices, as well as intermediate structures formed during the fabrication of semiconductor devices.

As used herein, the term "treated semiconductor structure" means and includes any semiconductor structure that includes one or more at least partially formed device structures. The semi-conductive structures treated are a subset of semiconductor structures, and all conductive semiconductor structures. As used herein, the term "treated structure is bound semi-semiconductor structures" means and includes any structure that comprises two or more semiconductor structures that are attached to each other. The linked semiconductor structures are a subset of semiconductor structures, and all related semiconductor structures are semiconductor structures. In addition, the bonded semiconductor structures that include one or more processed semiconductor structures are also treated semiconductor structures.

As used herein, the term "device structure" means and includes any portion of a treated semiconductor structure, i.e., includes or defines at least a portion of a component active or passive component of a semiconductor device to be formed on or in the semiconductor structure. For example, the device structures comprise active and passive integrated circuit components, such as transistors, transducers, capacitors, resistors, conductive lines, conductive vias, and conductive pads. As used herein, the term "semiconductor wafer interconnect" or "TWI" means and includes any conductive through hole extending through at least a portion of a first semiconductor structure that is used for performing a structural and / or electrical interconnection between the first semiconductor structure and a second semiconductor structure through an interface between the first semiconductor structure and the second semiconductor structure. Interconnections passing through the semiconductor wafer are also known in the art by other expressions, such as "vias through silicon", "vias through the substrate", "vias" interconnection through the semiconductor wafer ", or abbreviations of these expressions, such as" TSV "or" TWV ". The TWIs generally extend through a semiconductor structure in a direction generally perpendicular to the generally flat major surfaces of the semiconductor structure (i.e., in a direction parallel to the "Z" axis ). According to some embodiments of the invention, the recoverable substrate structures are temporarily bonded to semiconductor structures and used in the formation of bonded semiconductor structures. The recoverable substrate structures are removed from the semiconductor structures at different points in the process of forming the bonded semiconductor structures. Recoverable substrate structures can provide support for interposers throughout the process stages. In addition, a separable interface between them may be designed to control the aspect ratio of the TSV and the thickness of the final interposing device (i.e., a thinner interposer device). results in a lower aspect ratio of TSV). Figs. 1A to 1C illustrate the fabrication of a substrate structure 120 (Fig. 1C) that may be used in some embodiments of the invention. With reference to FIG. 1A, a substrate structure 100 is provided which comprises a relatively thin layer of material 102 on a relatively thick substrate body 104. In some embodiments, the substrate structure 100 may comprise a substrate having the scale of the semiconductor wafer having an average diameter of several hundred millimeters or more. By way of example and not limitation, the relatively thin layer of material 102 may have an average thickness of about two hundred microns (200 μm) or less, about one hundred microns (100 μm) or less, or even about about fifty microns (50 μm) or less. The relatively thick substrate body 104 may have an average thickness, for example, between about three hundred microns (μm) and 750 microns or more. The relatively thin layer of material 102 may comprise a semiconductor material such as, for example, silicon or germanium. Such a semiconductor material may be a polycrystalline material or at least substantially composed of a monocrystalline material, and may be doped or undoped. In further embodiments, the relatively thin layer of material 102 may comprise a ceramic, such as an oxide (eg, silicon oxide (SiO 2), aluminum oxide (Al 2 O 3), etc. .), a nitride (for example, silicon nitride (Si3N4), boron nitride (BN), etc.), or an oxynitride (for example, silicon oxynitride (SION)).

The relatively thick substrate body 104 may have a composition different from that of the relatively thin layer of material 102, but may itself comprise a semiconductor material or a ceramic as mentioned in connection with the thin layer of material 102. In In further embodiments, the relatively thick substrate body 104 may comprise a metal or metal alloy. In some embodiments, the relatively thin layer of material 102 may be temporarily attached to the relatively thick substrate body 104 using temporary bonding techniques such as those disclosed in US Patent Application No. 12/837326. , which was filed on July 15, 2010 in the name of Sadaka and others. The relatively thick substrate body 104 may comprise a recoverable and reusable portion of the substrate structure 100, as discussed in more detail below. Referring to FIG. 1B, a plurality of interconnects passing through the semiconductor wafer 112 may be formed through the relatively thin layer of material 102 to form the substrate structure 110 of FIG. 1B. Various processes for forming the interconnects passing through the semiconductor wafer 112 are known in the art and can be used in embodiments of the present invention. As a non-limiting example, a mask mask layer may be provided on the exposed major surface of the thin layer of material 102. The drawn mask layer may include apertures extending therethrough at the locations at which it is desired to form the interconnects passing through the semiconductor wafer 112 through the thin layer of material 102. An etching process (e.g., an isotropic wet chemical etching process or anisotropic dry reactive ion etching process) can then be used. for etching through holes through the thin layer of material 102. Another example may include laser drilling the exposed major surface of the thin material layer 102 to form through holes.

After forming the through holes, the drawn mask layer may be removed, and the through holes may be filled with one or more metals or alloys of conductive metals (eg, copper or a copper alloy), or polycrystalline silicon, to form the interconnections passing through the semiconductor wafer 112. For example, one or more of a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process , an electroless chemical deposition process and an electrolytic deposition process may be used to provide the conductive material in the through holes and form the interconnections passing through the semiconductor wafer 112. After forming the plurality of interconnects passing through the semiconductor wafer 112 through the relatively thin layer of material 102, one or more redistribution layers (RDL) 122 may be formed on the a thin layer of material 102 on one side thereof opposite the relatively thick substrate body 104 to form the substrate structure 120 shown in Figure 1C. As known in the art, redistribution layers may be used to redistribute the locations of electrical characteristics of a first device or structure so as to receive a pattern of conductive characteristics on another device or structure to be coupled to it. this. In other words, a redistribution layer may have a first pattern of conductive characteristics on a first side of the redistribution layer and a second pattern of different conductive characteristics on a second opposite side of the redistribution layer. As shown in Fig. 1C, the redistribution layer 122 may include a plurality of conductive features 124 that are disposed in and surrounded by a dielectric material 126. Conductive features 124 may include one or more conductive pads, laterally extending conductive lines or tracks, and vertically extending conductive vias. Further, the redistribution layer 122 may comprise a plurality of layers formed sequentially on each other, each layer comprising conductive characteristics 124 and the dielectric material 126, and the conductive characteristics 124 of a layer may be in physical contact with each other. direct electrical connection with the conductive characteristics 124 in the adjacent layers, so that the conductive characteristics 124 of the redistribution layer 122 extend continuously through the dielectric material 126 from one side of the redistribution layer 122 to the opposite side of the redistribution layer 122. On the side of the redistribution layer 122 adjacent the relatively thin layer of material 102 and the interconnections passing through the semiconductor wafer 112, the conductive characteristics 124 of the redistribution layer 122 may be arranged in a pattern that is complementary to a pattern in l equel the interconnections passing through the semiconductor wafer 112 are arranged, so that the interconnections passing through the semiconductor wafer 112 are in direct physical and electrical contact with the corresponding conductive characteristics 124 of the redistribution layer 122. The pattern of the conductive characteristics 124 of the redistribution layer 122 may be redistributed through the thickness of the redistribution layer 122 from one side thereof to the other, as described above. The redistribution layer 122 may provide the ability to form a personalized routing pattern. For example, custom redistribution layers may be formed into a pattern that is a mirror image of the metallization layer pattern on a treated semiconductor structure or structures that will be subsequently bonded to the surface of the relatively thin layer of material. The redistribution layer 122 may also provide "fan-in" and / or "fan-out" capabilities. For example, with fan-in redistribution layers, the device structure (e.g., chip device) limits the available area for contacts and passive device structures, in addition to other limitations due to proximity effects of device structures. With fan-out redistribution layers, fan-in limitations can be eliminated, which provides routing flexibility using standard CMOS back-end processing. Passive devices formed in these redistribution layers can utilize the availability of thick metals and low k dielectrics. Therefore, they may have improved operating characteristics compared to passive devices fabricated on the device structure (for example, a chip device). With reference to FIG. 1D, after forming the redistribution layer 122, at least one treated semiconductor structure 132A may be bonded to the relatively thin layer of material 102 of the substrate structure 120 on one side of the substrate. opposite to the relatively thick substrate body 104 to form a structure 130. For example, said at least one treated semiconductor structure 132A may be directly bonded to the redistribution layer 122, as shown in FIG. 1D. In some embodiments, a plurality of treated semiconductor structures 132A, 132B, 132C may be bonded to the redistribution layer 122 on the relatively thin layer of material 102 of the substrate structure 120 on one side thereof opposite the relatively thick substrate body 104, as shown in Figure 1D. The plurality of treated semiconductor structures 132A, 132B, 132C may be disposed laterally next to each other along a common plane oriented parallel to a major surface of the first substrate structure 120, as shown in FIG. 1D. . In other words, each of the plurality of treated semiconductor structures 132A, 132B, 132C can occupy a different area on the substrate structure 120, and can be positioned so that a plane can be drawn parallel to a major surface of the first structure substrate 120 which passes through each of the treated semiconductor structures 132A, 132B, 132C. Said one or more treated semiconductor structures 132A, 132B, 132C may comprise, for example, semiconductor chips (made from silicon or other semiconductor materials), and may include one or more of electronic signal processors , memory devices, microelectromechanical systems (MEMS), and optoelectronic devices (e.g., light-emitting diodes, lasers, photodiodes, solar cells, etc.). To bond the treated semiconductor structures 132A, 132B, 132C to the substrate structure 120, the conductive characteristics 134 of the treated semiconductor structures 132A, 132B, 132C can be electrically coupled to the conductive characteristics 124 of the redistribution layer 122. and the interconnects passing through the semiconductor wafer 112 extending through the relatively thin layer of material 102. The bonding process used to bond the treated semiconductor structures 132A, 132B, 132C to the substrate structure 120 may be performed at a temperature or temperatures of about 400 ° C or less. In some embodiments, the treated semiconductor structures 132A, 132B, 132C may be bonded to the substrate structure 120 using a direct thermocompression bonding process performed at a temperature or temperatures of about 400 ° C or less. In further embodiments, the treated semiconductor structures 132A, 132B, 132C may be bonded to the substrate structure 120 using an ultra low temperature direct bonding process performed at a temperature or temperatures of about 200 ° C. or less. In some cases, the bonding process can be performed at about room temperature. Performing the bonding process at these lower temperatures avoids inadvertent damage to the device structures in the treated semiconductor structures 132A, 132B, 132C. In addition, the linking process may include a surface-assisted bonding process in certain embodiments. The direct bonding process may include a direct oxide-to-oxide bonding process (eg silicon dioxide to silicon dioxide) and / or a direct metal-to-metal bonding process (eg, copper to copper).

In some embodiments, additional processed semiconductor structures may be stacked on the treated semiconductor structures 132A, 132B, 132C and electrically and physically coupled thereto using one or more three-dimensional (3D) integration processes. . Examples of these processes are described below with reference to Figs. 1E to 1H. Referring to FIG. 1E, after bonding the treated semiconductor structures 132A, 132B, 132C to the substrate structure 120, a low-stress dielectric material 138 may be deposited on the treated semiconductor structures 132A, 132B, 132C and around them to form the structure 140 of Figure 1E. The dielectric material 138 may comprise, for example, a polymeric material or an oxide (eg, silicon oxide), and may be deposited using, for example, a centrifugation process or a chemical vapor deposition process ( CVD) or a Physical Vapor Deposition (PVD) process. The dielectric material 138 may be conformably deposited on the structure 130 of FIG. 1D so that an exposed major surface 139 of the dielectric material 138 includes peaks and valleys. The peaks may be located on the treated semiconductor structures 132A, 132B, 132C, and the depressions may be located in the regions between the treated semiconductor structures 132A, 132B, 132C, as shown in Figure 1E.

Referring to Fig. 1F, the exposed major surface 139 of the dielectric material 138 may be flattened, and a portion of the dielectric material 138 may be removed to expose the treated semiconductor structures 132A, 132B, 132C through the dielectric material 138 and forming the structure 150 shown in Figure 1F. For example, a chemical etching process (wet or dry), a mechanical polishing process, or a chemical mechanical polishing (CMP) process may be used to flatten the main surface 139 of the dielectric material 138, removing some of the material dielectric 138, and exposing the treated semiconductor structures 132A, 132B, 132C through the dielectric material 138. In some embodiments, the treated semiconductor structures 132A, 132B, 132C may comprise processed semiconductor structures of different heights. In such a case, the equalization of the dielectric material 138 can be performed to expose the treated semiconductor structure with the greatest height, followed by a combination of chip thinning and dielectric polishing to smooth the structure 150.

As shown in FIG. 1G, a further plurality of interconnects passing through the semiconductor wafer 162 may be formed at least partially through the treated semiconductor structures 132A, 132B, 132C to form the structure 160. The interconnections traversing the semiconductor wafer Additional conductive members 162 may be formed through the treated semiconductor structures 132A, 132B, 132C from exposed major surfaces thereof to conductive characteristics 134 in treated semiconductor structures 132A, 132B, 132C. Interconnections passing through the semiconductor wafer 162 may be formed as previously described in connection with the formation of the interconnects passing through the semiconductor wafer 112. However, the processes may be limited to temperatures of about 400 ° C or less to avoid to damage the device structures in the treated semiconductor structures 132A, 132B, 132C.

Referring to FIG. 1H, after forming the additional interconnections through the semiconductor wafer 162, the processes described above in connection with FIGS. 1D-1G can be used to realize the treated semiconductor structures 132D, 132E, 132F vertically on the treated semiconductor structures 132A, 132B, 132C and form the bonded semiconductor structure 170 shown in FIG. 1H. As an example, a treated semiconductor structure 132D can be bonded directly to the treated semiconductor structure 132A, a treated semiconductor structure 132E can be directly bonded to the treated semiconductor structure 132B, and a semiconductor structure treated 132F can be directly related to the 132C treated semiconductor structure. These bonding processes may be limited to temperatures of about 400 ° C or less to avoid damage to device structures in treated semiconductor structures 132A-132F, and may include a direct bond process without thermocompression or Ultra low temperature direct bonding process. In addition, in some embodiments, the forward link processes may include surface-assisted linkage processes.

In this configuration, the treated semiconductor structures 132D, 132E, 132F are respectively arranged vertically on the treated semiconductor structures 132A, 132B, 132C along lines oriented perpendicular to the major surfaces of the first substrate structure 120. For example, the Treated semiconductor structure 132A and treated semiconductor structure 132D are disposed vertically on each other along a common line oriented perpendicular to the major surfaces of the first substrate structure 120. In other words, the treated semiconductor structure 132A and the treated semiconductor structure 132D are arranged such that a common line may be drawn perpendicular to the major surfaces of the first substrate structure 120 through each of the treated semiconductor structure 132A and the treated semiconductor structure 132D.

After bonding the treated semiconductor structures 132D, 132E, 132F to the treated semiconductor structures 132A, 132B, 132C, additional interconnections through the semiconductor wafer 172 may be formed at least partially through the 132D treated semiconductor structures, 132E, 132F. The additional interconnections through the semiconductor wafer 172 may be formed through the treated semiconductor structures 132D, 132E, 132F from the exposed major surfaces thereof to the interconnects passing through the semiconductor wafer 162 or to other conductive characteristics of the treated semiconductor structures 132A, 132B, 132C. The interconnections passing through the semiconductor wafer 172 may be formed as previously described in connection with the formation of the interconnects passing through the semiconductor wafer 112. However, the processes may be limited to temperatures of about 400 ° C or less to avoid 5 to damage the device structures in the treated semiconductor structures 132A to 132F. The processes described above in connection with FIGS. 1D-1G may be repeated one or more times as desired to vertically integrate any number of additional layers of semiconductor structures processed on the treated semiconductor structures 132A to 132F in a three-dimensional (3D) integration process. Referring to FIG. 1I, a second substrate structure 182 may be bonded on the treated semiconductor structures 132A-132F on one side thereof opposite the first substrate structure 120 to form the semiconductor structure. Connected conductor 180 shown in FIG. The second substrate structure 182 may have an at least substantially homogeneous composition, or it may comprise a multilayered structure comprising layers of materials having different compositions. As nonlimiting examples, the second substrate structure 182 may comprise a semiconductor material such as, for example, silicon or germanium. Such a semiconductor material may be a polycrystalline material or at least substantially composed of a monocrystalline material, and may be doped or undoped. In further embodiments, the second substrate structure 182 may comprise a ceramic, such as an oxide (eg, silicon oxide (SiO 2), aluminum oxide (Al 2 O 3), etc. .) a nitride (for example, silicon nitride (Si3N4), boron nitride (BN), etc.), or an oxynitride (for example, silicon oxynitride (SiON)). The second substrate structure 182 may also include a metal or a metal alloy in some embodiments. The second substrate structure 182 may have an average thickness, for example, between about 1.5 micron (μm) and several centimeters.

In some embodiments, the second substrate structure 182 may be temporarily attached to the semiconductor structure 170 of Figure 1H using techniques such as those described in the aforementioned US Patent Application No. 12/837326 filed July 15, 2010 on behalf of Sadaka and others. The second substrate structure 182 may be directly bonded to the exposed surfaces of one or more dielectric materials 174 of the treated semiconductor structures 132D to 132F, and the interconnects passing through the semiconductor wafer 172 of the treated semiconductor structures 132D to 132F. Referring to Fig. 1J, after the temporary bonding of the second substrate structure 182 to the semiconductor structure 170 (Fig. 1H), the relatively thick substrate body 104 of the first substrate structure 120 can be separated or otherwise removed, leaving the relatively thin layer of material 102 and the interconnects passing through the semiconductor wafer 112 extending therethrough connected to the redistribution layer 122 and treated semiconductor structures 132A-132F. For example, the relatively thick substrate body 104 may be separated from the relatively thin layer of material 102 and recovered in a manner that does not cause significant or irreparable damage to the relatively thick substrate body 104. Optionally, a conductive boss 192 may be provided on the exposed end of each of the interconnects passing through the semiconductor wafer 112 to form the bonded semiconductor structure 190 of Figure 1J. The conductive bosses 192 may comprise a conductive metal or a metal alloy, such as a refoldable solder alloy, and may be used to facilitate a structural and electrical coupling of the interconnects passing through the semiconductor wafer 112 of the semiconductor structure. related to conductive characteristics of another structure 202, which may be, or include, a higher level substrate or device. For example, as shown in Fig. 1K, the bonded semiconductor structure 190 of Fig. 1J may be structurally and electrically coupled to the structure 202. For example, the structure 202 may comprise another processed semiconductor structure or a card printed circuit board. As shown in FIG. 1J, the structure 202 may comprise a plurality of conductive characteristics 204 and a surrounding dielectric material 206. Conductive characteristics 204 may include bond pads, for example. Conductive bosses 192 may be aligned with and abut against conductive characteristics 204. The conductive bosses 192 may be heated to cause the material of the conductive bosses 192 to melt again, after which the material may be cooled and solidified, thereby forming a structural and electrical connection between the interconnects passing through the semiconductor wafer 112 and the conductive characteristics 204 of the structure 202. With reference to FIG. 1L, after the structural and electrical coupling of the interconnections traversing the semiconductor wafer 112 and the conductive characteristics 204 of the structure 202, the second substrate structure 182 (FIG. 1K) can be removed to form the bonded semiconductor structure 210 shown in FIG. 1L.

After removing, from each of the relatively thick substrate body 104 of the first substrate structure 120 and the second substrate structure 182, the relatively thick substrate body 104 and / or the second substrate structure 182 can be recovered and reused. For example, the relatively thick substrate body 104 and / or the second substrate structure 182 may be reused one or more times in methods of forming bonded semiconductor structures (e.g., a bonded semiconductor structure similar to the linked semiconductor structure 210 of Figure 1L) as previously described herein. The bonded semiconductor structure 210 of Figure 1L may further be treated as needed or desired to make the bonded semiconductor structure 210 suitable for its intended use. As a non-limiting example, a protective coating or encapsulating material may be provided on at least a portion of the bonded semiconductor structure 210, and / or a protective bonding material may be provided between the structure 202 and the layer of material 102 between and around the conductive bosses 192.

In some embodiments of the invention, one or more of the substrate structures that are temporarily bonded to and ultimately removed from the semiconductor structures during the bonded semiconductor structure forming processes as described herein may include a semiconductor on insulator substrate (SeOI), such as a silicon on insulator (SOI) substrate. For example, Figure 2A illustrates an example of a semiconductor on insulator substrate 300 that may be used in embodiments of the invention. The semiconductor-on-insulator substrate 300 comprises a layer of semiconductor material 302 disposed on a dielectric insulator layer 303, which may be disposed on a relatively thick substrate body 304. In these substrate structures, the Insulator 303 is often referred to as a "buried" layer, such as a "buried oxide" layer.

The semiconductor material layer 302 and the insulator layer 303 may be relatively thin compared to the relatively thicker substrate body 304. By way of example and not limitation, the layer of semiconductor material 302 may have a relatively thin layer 303. average thickness of about ten microns (10 pirt) or less, about one hundred nanometers (100 nm) or less, or even about ten nanometers (10 nm) or less. Insulator layer 303 may have an average thickness of about one micron (1 μm) or less, about two hundred nanometers (200 nm) or less, or even about ten nanometers (10 nm) or less. The relatively thick substrate body 304 may have an average thickness, for example, between about seven hundred and fifty microns (μm) and several centimeters.

The layer of semiconductor material 302 may comprise a semiconductor material such as, for example, silicon or germanium. Such a semiconductor material may be a polycrystalline material or at least substantially composed of a monocrystalline material, and may be doped or undoped. The insulator layer 303 may comprise a ceramic, such as an oxide (for example, silicon oxide (SiO 2), aluminum oxide (Al 2 O 3), etc.), a nitride (for example, silicon nitride (Si3N4), boron nitride (BN), etc.), or oxynitride (for example, silicon oxynitride (SiON)). The relatively thick substrate body 304 may have a composition different from that of the semiconductor material layer 302 and / or the insulation layer 303, but may itself comprise a semiconductor material or a ceramic such as mentioned in connection with the semiconductor material layer 302 and the insulator layer 303. In additional embodiments, the relatively thick substrate body 304 may comprise a metal or alloy of metals, although silicon or another material selected to present a corresponding ETC may be desirable. Referring to FIG. 2B, a plurality of interconnects passing through the semiconductor wafer 312 may be formed through the layer of semiconductor material 302, as discussed previously in connection with the interconnects 30 passing through the semiconductor wafer. 112 with reference to Fig. 1B, to form the substrate structure 310 shown in Fig. 2B. After forming the interconnects passing through the semiconductor wafer 312 through the semiconductor material layer 302, the substrate structure 310 can be processed as previously described with reference to Figures 1C-11 to form the bonded semiconductor structure 380 shown in FIG. Figure 2C. The bonded semiconductor structure 380 is substantially similar to the bonded semiconductor structure 180 of Figure 11, but includes the substrate structure 310 of Figure 2B, with a redistribution layer 122 thereon substituted for the first structure of substrate 120.

After forming the bonded semiconductor structure 380 of Fig. 2C, the insulator layer 303 and the substrate body 304 can be removed from the bonded semiconductor structure 380, as previously described. The substrate body 304 may be recovered and reused, as previously described herein. After removing the insulator layer 303 and the substrate body 304, the resulting bonded semiconductor structure can be processed as previously described with reference to Figs. 1J-1L.

As mentioned above, in connection with FIG. 1K, in some embodiments, the additional structure 202 to which the bonded semiconductor structure 190 of FIG. 1J may be attached may comprise another processed semiconductor structure. An example of such a method is described below with reference to Figs. 3A to 3D. Figure 3A illustrates a bonded semiconductor structure 400 that can be formed from the bonded semiconductor structure 180 by removing the substrate body 104 from the first substrate structure 120 thereof, as previously described herein in connection with the FIGS. 11 and 1J, but without providing the conductive bosses 192 (FIG. 1J) on the interconnections passing through the semiconductor wafer 112. With reference to FIG. 3B, an additional treated semiconductor structure 412 can be directly linked to the layer of material 102, to the interconnections passing through the semiconductor wafer 112, or both to the layer of material 102 and to the interconnections passing through the semiconductor wafer 112.

By way of example and not limitation, the further treated semiconductor structure 412 may comprise a semiconductor chip, and may include one or more of an electronic signal processor, a memory device and a optoelectronic device (e.g., a light-emitting diode, a laser, a photodiode, a solar cell, etc.). The direct bonding process used to bond the additional treated semiconductor structure 412 to the material layer 102 and / or interconnections through the semiconductor wafer 112 may be performed at a temperature or temperatures of about 400 ° C or less. In some embodiments, the bonding process may comprise a direct thermocompression bonding process performed at a temperature or temperatures of about 400 ° C or less. In additional embodiments, the bonding process may comprise an ultra low temperature direct bonding process performed at a temperature or temperatures of about 200 ° C or less. In some cases, the bonding process can be performed at about room temperature. In addition, the linking process may include a surface-assisted bonding process in some embodiments. The direct bonding process may include a direct oxide-to-oxide bonding process (eg silicon dioxide to silicon dioxide) and / or a direct metal-to-metal bonding process (eg, copper to copper). As shown in FIG. 3B, the additional interconnections through the semiconductor wafer 414 may be formed through the additional treated semiconductor structure 412. The additional cross-connects through the semiconductor wafer 414 may be formed through the treated semiconductor structure 412 before or after the direct bonding of the additional treated semiconductor structure 412 to the material layer 102 and / or the interconnections traversing the semiconductor-I12. At least a portion of the interconnects traversing the semiconductor wafer 414 may extend to the interconnects traversing the semiconductor wafer 112 in the material layer 102 and may be structurally and electrically coupled thereto. Optionally, a conductive boss 416 may be provided on the exposed end of each of the interconnects passing through the semiconductor wafer 414 to form the bonded semiconductor structure 410 of Figure 3B, as previously described in connection with the conductive bosses. 192 with reference to Figure 1J. Referring to Fig. 3C, the bonded semiconductor structure 410 of Fig. 3B may be structurally and electrically coupled to a structure 422. For example, the structure 422 may comprise another processed semiconductor structure or a circuit board. printed circuit board. As shown in FIG. 3C, the structure 422 may comprise a plurality of conductive features 424 and surrounding dielectric material 426. Conductive features 424 may include bond pads, for example. Conductive bosses 416 may be aligned with and abut against conductive features 424. The conductive bosses 416 may be heated to cause the material of the conductive bosses 416 to melt again, after which the material may be cooled and solidified, thereby forming a structural and electrical connection between the interconnects passing through the semiconductor wafer 414 and the conductive characteristics 424 of the structure 422.

Referring to FIG. 3D, after the structural and electrical coupling of the interconnects passing through the semiconductor wafer 414 and conductive characteristics 424 of the structure 422, the second substrate structure 182 (FIG. 3C) can be removed to form the structure linked semiconductor 430 shown in FIG. 3D. For example, a mechanical division process, an etching process, or a combination of these processes may be used to remove the second substrate structure 182 to form the bonded semiconductor structure 430. After removing semiconductor structures each of the relatively thick substrate body 104 of the first substrate structure 120 and the second substrate structure 182, the relatively thick substrate body 104 and / or the second substrate structure 182 may be recovered and reused, as discussed. previously here. The bonded semiconductor structure 430 of FIG. 3 may further be treated as desired or desired to make the bonded semiconductor structure 430 suitable for its intended use. As a non-limiting example, a protective coating or encapsulating material may be provided on at least a portion of the bonded semiconductor structure 430, and / or a protective bonding material may be provided between the bonding structure 422 and the treated semiconductor structure 412 between and around the conductive bosses 416.

According to the methods described above, by maintaining the second substrate structure 182 bonded to the treated semiconductor structures 132A to 132F until the bonded semiconductor structures 200, 420 have been bonded to the additional structures 202, 422, buckling, cracking and other damage that may occur in the related semiconductor structures due, for example, to differences in the coefficients of thermal expansion of the various materials and devices thereof, can be avoided or reduced. Additional non-limiting exemplary embodiments of the invention are described below. Embodiment 1: A method of forming a bonded semiconductor structure, comprising: providing a first substrate structure comprising a relatively thin layer of material on a relatively thick substrate body; forming a plurality of interconnects passing through the semiconductor wafer through the relatively thin layer of material of the first substrate structure; bonding at least one treated semiconductor structure to the relatively thin layer of material of the first substrate structure on a side thereof opposite to the relatively thick substrate body and electrically coupling at least one conductive characteristic of the at least one semiconductor structure treated at least one interconnection crossing the 0 semiconductor wafer of the plurality of interconnections passing through the semiconductor wafer; bonding a second substrate structure to said at least one semiconductor structure treated on one side thereof opposite the first substrate structure; removing the relatively thick substrate body from the first substrate structure and leaving the relatively thin layer of material of the first substrate structure bonded to said at least one processed semiconductor structure; and electrically coupling at least one interconnection traversing the semiconductor wafer of the plurality of interconnects passing through the semiconductor wafer to a conductive characteristic of another structure. Embodiment 2: The method according to Embodiment 1, further comprising removing the second substrate structure after the electrical coupling of the at least one interconnection traversing the semiconductor wafer of the plurality of interconnects traversing the semi wafer. conductive to the conductive characteristic of said other structure. Embodiment 3: The method according to Embodiment 1 or Embodiment 2, wherein the provision of the first substrate structure further comprises temporarily bonding the relatively thin layer of material to the relatively thick substrate body. and wherein removing the relatively thick substrate body from the first substrate structure and allowing the relatively thin layer of material of the first substrate structure bonded to the at least one processed semiconductor structure to separate the body relatively thick substrate of the relatively thin layer of material.

Embodiment 4: The method according to any one of embodiments 1 to 3, further comprising forming at least one redistribution layer on the relatively thin layer of material of the first substrate structure on the side thereof opposite to the relatively thick substrate body before bonding said at least one treated semiconductor structure to the relatively thin layer of material of the first substrate structure, and wherein the bonding of said at least one semiconductor structure treated to the relatively thin layer of material of the first substrate structure is to bond said at least one treated semiconductor structure to the redistribution layer. Embodiment 5: The method according to any one of embodiments 1 to 4, wherein the bonding of said at least one treated semiconductor structure to the relatively thin layer of material of the first substrate structure is to bond said minus a semiconductor structure treated on the relatively thin layer of material of the first substrate structure at a temperature or temperatures below about 400 ° C. Embodiment 6: The method according to any one of embodiments 1 to 5, wherein the bonding of said at least one treated semiconductor structure to the relatively thin layer of material of the first substrate structure is to bond said at least one semiconductor structure treated on the relatively thin layer of material of the first substrate structure using an ultra low temperature direct bonding process. Embodiment 7: The method according to any one of embodiments 1 to 6, wherein the bonding of said at least one treated semiconductor structure to the relatively thin layer of material of the first substrate structure is to bond a plurality of semiconductor structures processed on the relatively thin layer of material 10 of the first substrate structure. Embodiment 8: The method according to embodiment 7, wherein at least some of the plurality of treated semiconductor structures are disposed laterally next to each other along a common plane. oriented parallel to a major surface of the first substrate structure. Embodiment 9: The method according to Embodiment 8, wherein at least some of the plurality of processed semiconductor structures are arranged vertically on each other along a common oriented line. perpendicular to a major surface of the first substrate structure. Embodiment 10: The method according to embodiment 7, wherein at least some of the plurality of processed semiconductor structures are arranged vertically on each other along a common oriented line. perpendicular to a major surface of the first substrate structure. Embodiment 11: The method of any one of embodiments 1 to 10, further comprising selecting said other structure to include another processed semiconductor structure. Embodiment 12: The method of any one of embodiments 1 to 11, further comprising selecting said other structure to include a printed circuit board. Embodiment 13: The method of any one of embodiments 1 to 12, further comprising selecting the first substrate structure to include a semiconductor on insulator substrate (SeOI). Embodiment 14: The method of embodiment 13, further comprising selecting the first substrate structure to include a silicon on insulator (SOI) substrate. Embodiment 15: The method according to any one of embodiments 1 to 14, further comprising forming a further plurality of interconnects passing through the semiconductor wafer through said at least one semiconductor structure treated after bonding. said at least one semiconductor structure treated on the relatively thin layer of material of the first substrate structure. Embodiment 16: The method of any one of embodiments 1 to 15, further comprising reusing at least one of the second substrate structure and the relatively thick substrate body of the first substrate structure in a method of forming a bonded semiconductor structure. Embodiment 17: An intermediate structure formed during manufacture of a bonded semiconductor structure, comprising: a first substrate structure, comprising: a plurality of interconnects passing through the semiconductor wafer extending through a relatively thin layer material; and a relatively thick substrate body temporarily bonded to the layer of material; a plurality of processed semiconductor structures electrically coupled to the plurality of interconnects passing through the semiconductor wafer; and a second substrate structure temporarily bonded to the plurality of semiconductor structures processed on one side thereof opposite the first substrate structure. Embodiment 18: The intermediate structure according to Embodiment 17, wherein the first substrate structure comprises a semiconductor on insulator substrate (SeOI). Embodiment 19: The intermediate structure according to Embodiment 17 or Embodiment 18, wherein the relatively thin layer of material has an average thickness of about one hundred nanometers (100 nm) or less. Embodiment 20: The intermediate structure according to any one of embodiments 17 to 19, wherein at least some of the plurality of treated semiconductor structures are disposed laterally next to one another along a common plane oriented parallel to a major surface of the first substrate structure.

Embodiment 21: The intermediate structure according to any one of embodiments 17 to 20, wherein at least some of the plurality of processed semiconductor structures are disposed vertically on top of each other along a common line oriented perpendicular to a major surface of the first substrate structure. The exemplary embodiments of the invention described above do not limit the scope of the invention, since these embodiments are merely exemplary embodiments of the invention, which is defined by the present invention. scope of the attached claims and their legal equivalents. All equivalent embodiments are intended to be included within the scope of the present invention. Indeed, various variations of the invention, in addition to those shown and described herein, such as other useful combinations of the elements described, will become apparent to those skilled in the art from the description. In other words, one or more features of an exemplary embodiment described herein may be combined with one or more features of another exemplary embodiment described herein to provide additional embodiments of the invention. These variants and embodiments are also intended to fall within the scope of the appended claims.

Claims (21)

REVENDICATIONS1. A method of forming a bonded semiconductor structure, comprising: providing a first substrate structure (100, 300) comprising a relatively thin layer of material (102, 302) on a relatively thick substrate body (104, 304); forming a plurality of interconnects passing through the semiconductor wafer (112, 312) through the relatively thin layer of material (102, 302) of the first substrate structure (100, 300); bonding at least one treated semiconductor structure (132) to the relatively thin layer of material (102, 302) of the first substrate structure (100, 300) on a side thereof opposite to the substrate body relatively thick (104, 304) and electrically coupling at least one conductive characteristic (134) of said at least one treated semiconductor structure (132) to at least one interconnection traversing the semiconductor wafer (112, 312) of the a plurality of interconnects passing through the semiconductor wafer (112, 312); bonding a second substrate structure (182) to said at least one treated semiconductor structure (132) on one side thereof opposite the first substrate structure (100, 300); removing the relatively thick substrate body (104, 304) from the first substrate structure (100, 300) and leaving the relatively thin layer of material (102, 302) of the first substrate structure (100, 300) bound to said at least one treated semiconductor structure (132); and electrically coupling at least one interconnection 35 passing through the semiconductor wafer (112, 312) of the plurality of interconnects passing through the semiconductor wafer (112, 312) to a conductive characteristic (204, 414) of another structure (202, 422). The method of claim 1, further comprising removing the second substrate structure (182) after the electrical coupling of said at least one interconnection traversing the semiconductor wafer (112, 312) of the plurality of interconnects passing through the semiconductor wafer (112, 312) to the conductive characteristic (204, 414) of said other structure (202, 422). The method of claim 1, wherein providing the first substrate structure (100, 300) further comprises temporarily bonding the relatively thin layer of material (102, 302) to the relatively thick substrate body (104). , 304), and wherein removing the relatively thick substrate body (104, 304) from the first substrate structure (100, 300) and leaving the relatively thin layer of material (102, 302) of the first substrate structure (100, 300) bonded to said at least one treated semiconductor structure (132) comprises separating the relatively thick substrate body (104, 304) from the relatively thin layer of material (102, 302) . The method of claim 1, further comprising forming at least one redistribution layer (122) on the relatively thin layer of material (102, 302) of the first substrate structure (100, 300) on the side of that opposed to the relatively thick substrate body (104, 304) prior to bonding said at least one treated semiconductor structure (132) to the relatively thin layer of material (102, 302) of the first substrate structure (100, 300), and wherein the bonding of said at least one treated semiconductor structure (132) to the relatively thin layer of material (102, 302) of the first substrate structure (100, 300) comprises bonding said at least one treated semiconductor structure (132) at the redistribution layer (122). The method of claim 1, wherein bonding said at least one treated semiconductor structure (132) to the relatively thin layer of material (102, 302) of the first substrate structure (100, 300) comprises bonding said at least one treated semiconductor structure (132) to the relatively thin layer of material (102, 302) of the first substrate structure (100, 300) at a temperature or temperatures below about 400 ° vs. The method of claim 1, wherein bonding said at least one treated semi-conductive structure (132) to the relatively thin layer of material (102, 302) of the first substrate structure (100, 300) comprises bonding of said at least one treated semiconductor structure (132) on the relatively thin layer of material (102, 302) of the first substrate structure (100, 300) using an ultra low temperature direct bonding process. The method of claim 1, wherein bonding said at least one treated semiconductor structure (132) to the relatively thin layer of material (102, 302) of the first substrate structure (100, 300) comprises bonding a plurality of processed semiconductor structures (132A, 132B, 132C, 132D, 132E, 132F) to the relatively thin layer of material (102, 302) of the first substrate structure (100, 300). The method of claim 7, wherein at least some of the plurality of processed semiconductor structures (132A, 132B, 132C, 132D, 132E, 132F) are arranged laterally next to one another along a common plane oriented parallel to a major surface of the first substrate structure (100, 300). The method of claim 8, wherein at least some of the plurality of processed semiconductor structures (132A, 132B, 132C, 132D, 132E, 132F) are disposed vertically on top of each other. along a common line oriented perpendicular to a major surface of the first substrate structure (100, 300). The method of claim 7, wherein at least some of the plurality of processed semiconductor structures (132A, 132B, 132C, 132D, 132E, 132F) are arranged vertically on each of the plurality of processed semiconductor structures (132). others along a common line oriented perpendicular to a major surface of the first substrate structure (100, 300). The method of claim 1, further comprising selecting said other structure (202, 422) to include another processed semiconductor structure. The method of claim 1, further comprising selecting said other structure (202, 422) to include a printed circuit board. The method of claim 1, further comprising selecting the first substrate structure (100,300) to include a semiconductor on insulator substrate (SeOI). The method of claim 13, further comprising selecting the first substrate structure (100, 300) to include a silicon on insulator (SOI) substrate. The method of claim 1, further comprising forming a further plurality of interconnects passing through the semiconductor wafer (162, 172) through said at least one treated semiconductor structure (132) after bonding said at least one a treated semiconductor structure (132) on the relatively thin layer of material (102, 302) of the first substrate structure (100, 300). The method of claim 1, further comprising reusing at least one of the second substrate structure (182) and the relatively thick substrate body (104,304) of the substrate first structure (100,300). ) in a method of forming a bonded semiconductor structure. 17. An intermediate structure formed during the manufacture of a bonded semiconductor structure, comprising: a first substrate structure (100, 300), comprising: a plurality of interconnects passing through the semiconductor wafer (112, 312) and extending through a relatively thin layer of material (102, 302); and a relatively thick substrate body (104, 304) temporarily bonded to the material layer (102, 302); A plurality of processed semiconductor structures (132) electrically coupled to the plurality of interconnects passing through the semiconductor wafer (112, 312); and a second substrate structure (182) temporarily bonded to the plurality of processed semiconductor structures (132) on one side thereof opposite the first substrate structure (100, 300). 18. An intermediate structure according to claim 17, wherein the first substrate structure (100,300) comprises a semiconductor on insulator substrate (SeOI). 19. An intermediate structure according to claim 17, wherein the relatively thin layer of material (102, 302) has an average thickness of about ten nanometers (10 nm) or less. 20. An intermediate structure according to claim 17, wherein at least some of the treated semiconductor structures (132) of the plurality of processed semiconductor structures (132) are disposed laterally next to one another along a common plane. oriented parallel to a major surface of the first substrate structure (100, 300). An intermediate structure according to claim 20, wherein at least some of the plurality of processed semiconductor structures (132) are disposed vertically on each other along a common oriented line. perpendicular to a major surface of the first substrate structure (100, 300).