TWI326987B - Efficient design to implement ldpc (low density parity check) decoder - Google Patents

Description

1326987 IX. Invention Description: [Technical field of invention] The number and the secret of the communication are more ships. This judgment involves communication system communication. [Prior Art] The data communication system has been continuously developed for many years. Recently caused a major concern: the main package of the main offer code (turbQ eGde). Another communication system that uses Low Density Parity Check (LDPC) codes is also a topic of interest. The communication secrets of these classes can all achieve a lower bit error rate for the real axis (then. This field is lang_ and the main direction is to continue to work hard to reduce the error platform within the track purity (en: 〇r floor). The ideal goal is To reach the Sha_n's limit in the communication channel, the Shannon limit can be regarded as the (four) data rate in the communication channel, with a specific signal-to-noise ratio (10)), which can realize error-free transmission through the communication channel. In other words, for a given _ drunk and coding rate, the Shannon limit is the theoretical limit of channel capacity. Cong coded shirts and squares. For example, interactive soft decoding of (10)c = can be implemented in a financial manner, including reliability-based propagation (BeUef prc division (10), Bp) shoulder-same method, sum product (Sum_Pr〇duct, sp) algorithm, and (MeSSage-Passing, Mp ) Deductive, a) ~ law, MP is sometimes called the sum / confidence transmission group minus. Although Jing Jing Cong has made a lot of efforts and efforts, no matter which special way of interactive decoding algorithm is used by the brothers (as listed above), the communication is set to complete this decoding. The execution " space. For example, the calculation, data management, and processing of a variety of relatively complex and digital bits must be performed to complete the LDPC code of the coded signal, which has been shown to provide excellent decoding performance, at some extremes. For example, S (four) Na 嶋 财 财 ^ ^ ^ ^ ^ ^ ^ ^ Although this example uses an irregular knife of one million in length, it still proves that the application of the C code in the Lions is very promising. ΜImplementation, when decoding the received signal, in the process of calculation, the solution is based on the logarithmic domain of e), sometimes it is simple _ ζ number field. The pulse decoder belongs to this category. Converting some multiplications into additions, dividing into subtractions, and completely eliminating the exponent by operations in the logarithmic domain

performance. The calculation of the month's deduction without affecting the BER natural logarithmic domain comparison _ includes calculating the sum of the exponents as follows: In(ea+eb+ec+...) Complexity calculated using the Jacobian formula UaeQbian f as shown below Sex: L clerk reduction _ count ^ (a»b) = tn (e · + e ') a max (ajb) + ln (l + eM) & species is often referred to as max wood calculation or _ Operation. It should be noted that the above calculation only gives the calculation of two variables ^ b. When calculating = lack of sum, this calculation can be repeated. For example, to calculate ΐη(Α~), you can perform the following two max* operations: - max*(ab)=ln(e* +eb)*max(atb)+]n([+eM|j= χ _ (a,b,C)=ma^e)= + W)=maxM+14+e1 Although there has been a great development in the LDPC code environment, the large amount of processing and calculation necessary to perform decoding is extremely cumbersome. The calculation index and Guan provided by the agency explained the potential complexity and the heavy calculations required when c. • the implementation of such signals. Sometimes, the handling of 'requirements is so cumbersome that the design budget m (four) unified H prohibits this _ execution. There are already some non-optimal methods to handle the heavy calculations required. For example, when the lamp base max* operation is performed, 'some decodings are completely removed from the Wei correction factor', M), and the max(a'b) result is used, which can be a single instruction in the digital signal processor (10) p). Implemented inside. However, this inevitably degrades the performance of the decoder and makes the calculations inaccurate. Most systems that seek to improve the impulses either cut corners in terms of computational accuracy, or can't reduce the complexity of the calculations to adjust their integrals. A factor that hinders the implementation of LDpc codes 疋 inherently different complexity and the amount of storage required associated with it. In Lai County, the towel is done like max^t, and it is necessary to provide a more effective solution. LDPC coded signals are being used in many new applications. One such application area is digital video broadcasting. The Digital Video Broadcasting Organization (DVB) is an industry leadership consortium that includes more than 2, 6 broadcasters, manufacturers, network operations, software development companies, management groups and other entities in more than 35 countries. A globally harmonized standard for digital transmission of digital contempt and data services. Information about DVB can be obtained from the following Internet addresses: . "http: //www.dvb.org/,, , DVB-S2 (ie DVB-Satellite Version 2) draft Standards are also available through this Internet address. The DVB_S2 draft standard can be downloaded in Adobe PDF format from the following Internet address: "http://www.dvb. 〇rg/docuraents//en302307. vl. 1.1. Draft, pdf 1326987 Therefore the full content of the 'DVB-S2 draft standard, namely, draft ETSi EN 302 307 VI.1.1 (2004-06), digital video broadcasting (DVB); second-generation training frame structure, broadcast communication. Channel coding and modulation systems, interactive services, message collection and other broadband satellite applications" (Draft ETSI ΕΝ 302 307 VI. 1.1 (2004-06), Digital Video Broadcasting (DVB); Second generation framing structure, channel Coding and modulation systems for Broadcasting, Interactive Services, News Gathering and other broadband satel 1 ite applicat〇ns) 'herein reference is made in its entirety and constitutes a part of the present disclosure. Lu also, standard "ETSI EN 302 307 VI. 1.1 (2005 -03), Digital Video Broadcasting (DVB); second-generation training frame structure 'broadcast channel coding and modulation system, interactive services, message collection and other broadband satellite applications, at 2()() 5 years It was officially approved in March (European Electric and Letter Standards Association). The entire text of this application is hereby incorporated by reference in its entirety in its entirety in its entirety in its entirety herein in its entirety in its entirety Information on the signals used in systems that comply with DVB-S2 is described in detail in this DVB-compliant standard. The _ along the standard mainly focuses on the description of the transmission system and its sub-systems, including mode adaptation, flow adaptation, FEC, coding (including extra-brain coding and intra-hop coding), and mapping to the cluster (c〇). Nstellati〇n), physical layer training and baseband shaping and quadrature modulation. DVB-S2 is an advanced, version of DVB-S (the first standard proposed by digital video broadcasting organizations). DVB-S2 attempts to provide higher efficiency than brain_s. Negotiation 昼 Execution*, the same modulation: QPSK (Quadrature Phase Shift Keying), 8 PSK (Phase Shift Keying), 16th Position (Asymmetric Phase Shift Keying), and 32 APSK. In general, the QPSK and 8 PSK modulation types are used in the near-saturated nonlinear satellite transponder propagation applications; the 16ApsK and 32 sinking modulation types are primarily intended for professional applications requiring translinear transponders. In addition, DVB-S2 uses a powerful forward error correction (FEC) system based on bch (Boss-Johri-Hochwinheim) outer coding combined with LDPC intra-coding. The result is that performance is sometimes only 7 dB from the Shannon limit. The choice of the fec parameter depends on the system requirements. Using VCM (Variable Coding and Modulation) and Response (Adaptation Coding and Modulation), the coding rate can be dynamically changed based on a training frame. The call to the receiving device, including the plurality of arithmetic parameters that the decoder must follow to perform the face-and-forward operation, is clearly listed by the operational parameters in the transport system description. However, as long as the decoder complies with these operational parameters specified in the DVB-S2 standard, the implementation method is allowed to have a larger selection of posts. The Wei-Taiwan's Wei-Terminal Orbital Generation has been widely published in the 臓(8) standard, and the method of receiving such a signal tiger (in the communication channel (4)) is widely open to the public. Obviously, the key design constraint for this type of receiving device is to provide the adaptability of the DVB-S2 signal while providing high performance while occupying only a small area of the product and having a relatively low complexity. Another application area for using LDPC coded signals is the various communication systems and applications that are regulated and managed by the 1st (Electronic and Electronic Engineers Association). For example, Cong coding • The use of signals is very important in the IEEE P802. 3an (10GBASE-T) task group. The post of the P802·3an (10GBASE-T) task force was created and engaged in the development and standardization of the copper wire 1 billion bit Ethernet standard. The copper wire 1Q billion bit Ethernet standard according to the dirty 3 CSMA / The CD Ethernet protocol is implemented by a twisted pair cable. Carrier Sense Multiple Access/Collision Detection (CSMA/CD) is a protocol for carrier transmission access in an Ethernet network.臓 9 1326987 802. 3an (10GBASE-T) is the new standard for lOGbps Ethernet operating on 4 twisted pairs. More public information about IEEE P802.3an (10GBASE-T) is available from the following Internet: Road Address: < "http://www.ieee802.org/3/an". High in this application The data rate is relatively close to the worst case theoretical maximum rate of a 100 meter cable. Achieving lOGbps operation requires close capacity to implement error correction code. The potential constraints associated with using regular link codes can hinder their use in the application. Typical coding and modulation of LDPC coded signals is performed by generating a signed signal, each symbol having a common coding rate and being mapped to a monotonic change (e.g., a single singular constellation shape having therein) Single mapping of each cluster point). In other words, all symbols of this Lj)pc coded modulation signal have the same code rate and the same modulation (the same cluster shape, the cluster point has a single mapping). Typically, this prior art design is implemented to maximize hardware and processing efficiency for generating LDPC coded signals with all symbols within a single code rate and a single modulation. Ren Biao, in some recent LDPC communication systems, the design of LDPC encoders has been seeking to provide the ability to generate multiple-sided LDPC code reduction. The communication system makes the coding rate and modulation type of all symbols in any given LDPC block the same. In other words, the entire block has a specific type of programming and modulation. However, the 'encoder can be used to generate different LDPC blocks, such that the first ld - 2 code rate and the fine - modulating type, the second LD pe block has the second gamma rate ·, and the second tune associated with it Variable type. The decoder used to solve the stone horse must be able to touch the various types of 1 10 1326987 blocks it receives. At present, the prior art Cong decoder design requires a relatively large surface area and has a relatively high complexity. Therefore, in the current miscellaneous surgery, it is necessary to provide a pulse decoding state that can provide high performance and only has small area and low complexity. [Invention] The technology to be solved by the present invention lies in The above-mentioned deficiencies of the prior art: = (low-density parity check) coded signal solution and a coded description: = - aspects of the (four) decoding _ coded signal decoder, metric generator, for: = corresponding The first-z, q (in-phase, quadrature) value of the symbol-symbol of the S-coded signal, the first-order multi-bit metric is generated, and the second _ corresponding to the second symbol of the LWC-encoded signal is received. And two sets of a plurality of bit metrics; τ generating a metric memory for: storing the first set of plural red metrics and the second supporting 埠 memory core + radiance, a plurality of n (4) The yield generation n receives the plurality of bits w degrees of the second cylinder, and as described in the first-group Wei-yuan metric; and, supports the management of the double-click memory, thereby

Simultaneously, the second group of plural bits is rotated by the second plurality of bits, and the second plurality of bits/school H 1326987 are continuously received. The first group of plurality of bit metrics, the second group are continuously received. a plurality of bit metrics and the third plurality of bit metrics; • performing bit node processing, including updating a plurality of edge messages of the plurality of bit nodes _, and verifying node processing, including updating and plural a plurality of side messages associated with the check node; message transfer memory for:

And storing, after processing by the bit node, the plurality of side messages associated with the plurality of bit nodes; I in the plurality of bit/check processors After processing by the check node, storing the plurality of side messages associated with the plurality of check nodes; a barrel shifter for: reading the plurality of bits read from the message transfer memory a plurality of side messages associated with the meta-node are used to perform shifting; and the shifted plurality of side messages associated with the plurality of bit nodes are provided to the plurality of bit/check processors for subsequent verification Node processing; performing shifting elements on the plurality of side messages associated with the plurality of check nodes read from the message transfer memory; and correlating the shifted check nodes with the plurality of check nodes A plurality of side messages are provided to the plurality of bit/check processors for subsequent bit node processing. 'Preferably' said decoder further comprising: 'an output processor for use in said plurality of bit/check processors corresponding to a plurality of recently updated plurality of side messages associated with said plurality of bit nodes A soft output is received, and then a hard decision is made 12 丄 326 987 to generate a bit best estimate of at least one of the first symbol and the second symbol of the LDPC encoded signal. Advantageously, said decoder further comprises: a syndrome calculation function block for said plurality of bits/check processing corresponding to a plurality of side messages associated with said most recently associated plurality of bit nodes A soft round is received in the device, and it is determined whether each of the plurality of syndromes of the LDPC code used to generate the LDPC coded signal is equal to zero. Preferably, the ration memory, the plurality of bit/check processors, and the message transmission form a first macroblock including a plurality of macroblocks; Each of the plurality of macroblocks further includes a corresponding metric memory, a corresponding plurality of bit/check processors, and a corresponding message transfer memory. Each of the corresponding message transfer memory communication connections in each of the macro blocks of the plurality of macroblocks is described. The above-mentioned hidden system is a soldier-type storage structure, including two separate measurement memories. Preferably said said metric memory is a virtual double 埠 metric memory. Preferably, the plurality of side messages associated with the plurality of bit nodes are stored in the message transfer memory in a symbol value format; and the plurality of check nodes __ complex 姊 以 以 2 2 The format is stored in the messaging memory. 13 1326987 Preferably, the plurality of side messages associated with the plurality of bit nodes comprise a first plurality of side messages corresponding to the information bits and a second plurality of side messages corresponding to the parity bits; A first set of fine-edge messages of the information bits and a second set of multiple side messages of the corresponding parity bits are stored in the message transfer memory. Preferably, the check node processing includes mi_ (min_dQUble_star) processing and min**- (min-double-star-minus) processing. Preferably, the check node processing includes a minit (min_d〇uMe_dagger) process and a mint, (min-dagger-minus) process. Preferably, the LDPC coded signal is a variable code rate signal; the first symbol of the LDPC coded signal has a first code rate; and the second symbol of the LDPC coded signal has a second code rate. Preferably, the LDPC coded signal is a variable modulation signal; the first symbol of the LDPC coded signal has a first modulation, including a first cluster shape and a corresponding first mapping; The second symbol of the LDPC encoded signal has a second modulation comprising a second cluster shape and a corresponding second mapping. Preferably, the decoder decodes the LDPC coded signal, and the LDPC coded signal complies with the DVB-S2 (Digital Video Broadcasting project_SatelliteVersi〇n 2) standard and the recommended procedure provided by the IEEE P8〇2.3an (10GBASE-T) task group. 14 !326987 At least one. *. According to an aspect of the invention, a decoder for decoding an LDPC, an encoded signal is provided, the decoder comprising: a plurality of bit/check processors for: receiving a plurality of bit metrics;侃Node New' includes a plurality of side messages 'and a checksum point 4' of the more frequent semaphore __ including updating a plurality of edge call messages associated with the plurality of check nodes; message transfer memory for: After the plurality of bits are processed by the bit node in the verification process H, storing the plurality of side messages related to the plurality of bit nodes; Gu said Wei Chunyuan/News _ 峨龇 节 减 减And storing the plurality of side messages associated with the plurality of check nodes; the barrel shifter is configured to: _ read the complex number associated with the plurality of 侃 nodes read from the message transfer memory The side message is subjected to a shifting element; the shifted and complex stripe_phase_plural number of side counties are supplied to the plurality of bit/check processing H for subsequent check node processing; The plurality of reads from the message transfer memory Performing a plurality of edge messages related to the node to perform a shifting element; providing the shifted plurality of check nodes with the plurality of check nodes to the plurality of bit cells/checking the subsequent bit nodes of the riding deal with. Preferably, the decoder further comprises: a ridge generator, receiving a plurality of symbols corresponding to the LDPC coded signal

Phase, 丄, 1 w U°J parent) value' and generate a plurality of bit metrics therefrom. Preferably, the decoder further comprises: a round-out processor for processing the plurality of bits/check processing from a plurality of edge counts corresponding to the most recently updated plurality of bit nodes The S towel is fine-grained, and then a hard decision is made to describe the LDPG code minus the best estimate of the bit-to-J and the second symbol in the second symbol.

Preferably the decoder further comprises: a positive sub-computation function block for the plurality of bits/check processing corresponding to a plurality of side messages associated with the most recently updated plurality of bit nodes A soft round is received in the device, and it is determined whether each of the plurality of syndromes of the (3) code used to generate the LDPC coded signal is equal to zero. Advantageously, said decoder further comprises a metric memory, said plurality of metrics being stored and subsequently outputting said plurality of metrics to said plurality of bits/authentication processing The metric memory, the plurality of bit/check processors, and the message transfer memory form a first macroblock including a plurality of macroblocks; each of the plurality of macroblocks The macroblock further includes a corresponding metric memory, a corresponding plurality of bit/voucher processors, and corresponding message transfer memory; each of the barrel shifter and the plurality of macroblock commands Each corresponding messaging memory communication connection within the macroblock. 16 1326987 Preferably, the metric memory is a soldier-type storage structure, including two metric memory. $ • Preferably, the metric memory is a virtual double 埠 metric memory. Preferably, the plurality of side messages associated with the plurality of bit nodes are stored in the message transfer memory in a symbol value manner; the plurality of side messages associated with the plurality of the right node are supplemented by 2 The number format stores φ in the message transfer memory. Preferably, the plurality of side messages associated with the plurality of bit nodes include a plurality of side messages corresponding to the information bits and a second plurality of side messages corresponding to the parity bits; - the corresponding information A first plurality of side messages of the bit and a second plurality of side messages of the corresponding parity are stored in the message transfer memory. Preferably, the checkpoint processing includes min** (min-double_star) processing φ and min**- (min-double-star-minus) processing. Preferably, the checkpoint processing includes mintt (inin_double_dagger) processing and mint. (min-dagger-minus) processing. Preferably, the LDPC coded signal is a variable code rate signal; the first symbol of the LDPC coded signal has a first code rate; and the second symbol of the LDPC coded signal has a second code rate. Preferably, the LDPC coded signal is a variable modulation signal; the first symbol of the LDPC coded signal has a first modulation, including a first cluster shape and a corresponding first map (m- The second symbol of the LDPC-compiled signal has a second modulation, including a second cluster shape and a corresponding second mapping. Preferably, the decoding g decodes the coffee coded signal, and the pulse coded signal complies with at least one of the recommended procedures provided by the DVB-S2 (Digital Video Broadcasting Project-Satellite Version 2) standard and the _P802. 3an (10) B wins T) task group. One. According to an aspect of the present invention, a method for decoding a coffee coded signal is provided, the method comprising: a first I, Q (in-phase, quadrature) value, a second I, Q value and generating a first Receiving a first symbol corresponding to the LDPC coded signal and generating a first plurality of bit metrics therefrom;

Receiving a second plurality of bit metrics corresponding to the second symbol of the LDPC coded signal; ^ said [the group of plural metrics and the second group of plural metrics; ^ Shuang Yiji, Shu Weiqing: Nian Peiyuan Measure The time is rounded out of the first set of multiple bit metrics; - the heart is thin, the bottom touches (four) · Xie while the second set of multiple bit metrics; continuously receives the first set of plural a bitwise degree, the second set of a plurality of bit i degrees, and the third set of a plurality of bit metrics; • The I stub includes a bit node processing 'update and a plurality of bit sections __ A plurality of edge elimination I and weight check node processing, including updating a plurality of edges associated with a plurality of check nodes, and a '乂over bit TL section, after shouting, storing a plurality of edges of the meta-node and the complex number of her meta-nodes a message; after processing by the check node, storing the plurality of 1-edge messages associated with the plurality of check nodes; shifting the plurality of rhymes associated with the plurality of bit nodes to a suitable configuration Performing subsequent check node processing; the plurality of edges associated with the plurality of check nodes Shift information element to the appropriate configuration for subsequent bit node processing. Preferably, the method further comprises: receiving a wheel A of the plurality of side messages associated with the plurality of bit nodes corresponding to the updated update, and then making a hard decision 'to generate the LDpc stone horse signal number A bit-best estimate of at least one of a symbol and a second symbol. Advantageously, the method further comprises: - receiving a soft output corresponding to the most recently updated plurality of side messages associated with said plurality of bit nodes; - determining a plurality of corrections of the LDPC code used to generate the LDPC coded signal Whether each of the children is equal to zero. Preferably, the plurality of side messages associated with the plurality of bit nodes are stored in a symbol value format as described in 19^326987; the plurality of side messages associated with the plurality of button nodes are stored in a 2's complement format. Preferably, the complex and the meta-section __wei side message includes a first group of multiple side messages of the information bits and a second group of complex brain side counts: the method further includes And storing, in each storage device, each of the second plurality of side messages of the first side and the parity of the corresponding t-segment. Preferably, the check node processing includes min forest (. ubiquitous) processing and min**- (min-double-star-minus) processing. Preferably, the check node processing includes mintt (min_dQuble_daggei〇& and mint-(min-dagger-minus) processing. Preferably, the LDPC coded signal is a variable code rate signal; the LDPC coded signal The first symbol has a first coding rate; the second symbol of the LDPC coded signal has a second coding rate. Preferably, the LDPC coded signal is a variable modulation signal; the first symbol of the LDPC coded signal has The first-modulation includes a first cluster shape and a corresponding first mapping; 20 丄 the second symbol of the LDPG encoding dance u has a second symmetry, including a second cluster shape and corresponding The second mapping. Preferably, the 'the gamma transcode LDpc coder signal, the DM-coded DVB-S2 (Digital Video Broadcasting Project-Satellite Version 2) h and IEEE P8 〇 2.3an ( At least one of the recommended procedures provided by the 10GBASE-T) task group. [Embodiment] The present invention provides a decoding method and a method for the LDPG. Sex decodable and Wang Li has generated a compliance signal from the standard (ie, pay-S_nte Version 2). In addition, the decoding method and the capture decoding and processing proposed by the present invention have been born (four) from the task of Cong·U0GBASE-T) The signals provided by the group for draft standards and recommended procedures. In general, the decoding method and functionality proposed by the present invention can be applied to various devices that perform processing of LDPC coded signals and/or other types of coded signals. Sometimes, these devices can perform the transmission of the Cong code base _ ( The encoding method can also be used to receive processing (including decoding) of the LDPC encoded signal. In other cases, these devices can only perform the receiving processing (including decoding) of the LDPC encoded signal. Moreover, the decoding method of the present invention can be applied to have Modulation of variable modulation and/or variable coding rate • Signaling. For example, 'Wangyang ticketing explicitly describes VQf (variable editing and tuning (5) and by generating various LDPC signals conforming to DVB-S2 standard) Hall (adaptive coding and modulation) method. Generally, the coding rate and modulation of the signal are performed on a training-by-train basis. The decommissioning method and functional performance proposed by the present invention == The code rate and/or modulation is based on a frequently changing signal of the training frame. In addition, the present transmission block 2 and Yang_ can process and decode the signals based on the symbols m. For example, - A block can be considered as - in the training box - 'In some cases, a training box includes a plurality of blocks. The decoding method and functionality proposed by a single method also apply to all the symbols in the second or Decoding of a single modulated _ signal. For example, 'for all of them, the encoding rate and the common modulation (cluster and mapping) of the signal are all described (and in the following description of the mosquitoes) Decoding can be used to decode such LDPC coded signals. = and Figure 2 are respectively a (10) and a measurement of the communication system according to various embodiments of the present invention. As shown in Figure 1, the communication system (10) includes a communication channel (10) that will The communication at one end of the communication is fine (including the transmitter with the encoder 114 and the receiver 116 as the decoder m) and the other 2 device 120 at the other end of the communication channel (10) (including the transmission with the encoder 128) Please communicate with the decoder with the decoder 122. In some embodiments, the communication devices ιι and (10) both include - a developed n or - receivers. The communication channel (10) can pass several different classes The medium in which to implement (for example, The satellite communication of the satellite dish 132 and (9) is referred to as 'the paste tower 144 and/or the local antenna 152 and 】 54 line line channel (10) 'wired communication channel (10)' and / or use electricity - light ((10) Interface lion, first-electric (Ο/E) interface 164 optical fiber communication channel (10). In addition, more than one medium can be connected together to form communication channel 199. 22, in the communication system 200 shown in FIG. At the transmitting end of communication channel 299, the information: bit is provided to transmitter 297, which can perform this information using an encoder and symbol mapping pirate 20G (which can be considered as different functional blocks 222 and 224, respectively). The code of bit 201 is thus generated to generate a discrete value modulation symbol sequence 2〇3, which is then supplied to the transmit driver 230. The transmit driver 230 uses the DAC (digital analog converter) 232 to generate a succession signal. Then, by transmitting the chopper 234, a wave 2G5 is transmitted after the wave is sufficiently adapted to the communication channel 299. The I reception at communication channel 299, such as continuous time reception signal 206, is provided to the muscle (analog front end) 26〇, and the ship fine includes receive wave 262 (generating filtered continuous time reception signal 2〇7) and ADC (analog digital converter) ) 264 (Generate Discrete Time Receive Signal 208). The metric generator 270 calculates the symbol metric 209 'decode ϋ 280 using the symbol metric 209 to make a best estimate of the discrete value modulation symbol and the information bits encoded therein. The decoder in the foregoing embodiments has various features of the present invention. In addition, some of the following figures and associated descriptions will introduce other and specific embodiments that support the devices, systems, functionality, and/or methods of the present invention (the description of some embodiments is more detailed). The type of signal processed in accordance with the present invention is an LDPC coded signal. The LDPC code is briefly described before giving a more detailed introduction. FIG. 3 is a schematic diagram of an LDPC code bipartite graph 300. In the prior art, the LDpc bipartite graph is also known as the Tanner graph. The LDPC code is treated as a code having a binary parity check matrix such that almost all elements of the matrix (4) have zero values (e.g., the parity check matrix is sparse). For example, H = (hu) (four) is regarded as the parity check matrix of the LDpc code whose block length is N. 23 1326987 The number of 1s in the i-th column of the parity check matrix is represented as dv(i), and the number of 1's in the j-th row of the parity check matrix is represented as dc(j). If for all i, dv(i) = 丄, the LDPC code for which there is j ′ dc( j) = de ′ is called a regular LDPC code, otherwise it is called an irregular LDPC code. For an introduction to LDPC codes, please refer to the following two references: [1] R. Gallager » Low-Dentisy Parity-Check Codes >

Cambridge, MA: MIT Press, 1963 [2] M. Luby, M. Mitzenmacher, A. Shokrollahi, D. Spielman, and V. Stemann, “Practical loss-resilient codes”, 1997 Regular LDPC codes can be represented as bipartite graphs 3〇0, the left node of the parity check matrix is a code bit variable (or “variable node” (or “bit node”) 31〇 in the bit decoding method for decoding the LDPC coded signal), and the right node is The check equation (or "check node" 320^ is defined by a binary map of the LDPC code defined by Η, which can be defined by N variable nodes (for example, n-bit nodes) and one check node. N variable nodes Each variable node of Tick_ has an exact dv(1) edge (such as a side-by-side) connecting a bit node such as a postal and two or a plurality of check nodes (within M check nodes). The contact node V1 312 and the check node cj322. The number of edges (as shown by mirror 4) is called the degree of the variable node i. Similarly, each of the M check nodes, _ There are money,) one side (as shown by 幽), connect the node. = complex ^ variable node ( The number of edges is read as the degree of _ · point J. The edge between the variable node V1 (or bit node bi) 312 and the check node _ 24 1326987 • can be defined as e=( U), but, on the other hand, assume that the edge e = (i, D, _ node of the _ side, can be expressed as e = (v (e), c (e)) (or e = (b (e), c(e))). Assume that the variable node % * (or bit 70 node bi) ' can be defined as a set of edges emitted from node Vi (or bit node bi) as Ev(i)={e|v (e) = i} (or ^ 〇) = {64 (6 > 1}). Assuming that the check node 给出 is given, the -group edge transmitted from the node Cj can be defined as Ec (J>{e|c( e) = j}. Next, the result of the export is |Ev(i)b dv (or |Eb(i)|=db) and |EC( j)|=dc. -Generally, any available bipartite graph representation The code is characterized by a graphic code. It should be noted that the irregular LDPC code can also be represented by a bipartite graph. However, the degree of each group of nodes in the irregular code can be selected according to some distributions. Two different variable nodes of irregular LDpc code, Vil and Vi2, 丨Ev(5)丨 is not equal to |Ev (i〇 is also the relationship for two checkpoints. Unpaid LDPG code The concept was first introduced in the above cited quotation (2) • In general, through the illustration of the LDPC code, the parameters of the LDPC code can be defined by the degree of distribution, such as M. Luby et al. in the above reference file [2]. As mentioned above, there is also a description of the following references: []TJ Richardson and RL Urbanke, "The capacity of low-density parity-check code under message-passing decoding ' IEEE Trans. Inform. Theory,V〇I 47, pp. 599-618, .Feb. 2001 This distribution can be described as follows: Ai indicates the number of edges emitted from the i degree variable node, and Pi represents the number of edges emitted from the i degree check, ie, point. Then the degree of divergence (Λ, p) is defined as follows: 25 1326987, where Mv and Me respectively represent the variable node and the check section (6): Office 1 P〇f) = Art

The maximum degree of Μ and W points. Although the plural embodiments described herein employ a regular LDPC code, it is noted that the features of the present invention are applicable to both regular LDPC codes and irregular LDpc codes. The LLR (Log-Like Similar Value Ratio) decoding method of the LDPC code can be roughly described as follows: When the work is actually transmitted, the probability that the actual bit value in the received vector is equal to 丨 is calculated. Similarly, when 〇 is actually transmitted, 'the probability that the received vector_bit actual value is equal to Q is calculated. These probabilities are obtained by the odd matrix of the LDPG code, which is used to verify the parity of the (4) vector. The LLR is the logarithm of the ratio of the two probabilities calculated. The LLR mapping transmission communication channel produces a non-sounding degree to the vector (10) bit. The LLR decoding of the LDPC code can be mathematically expressed as follows: First, the LDPC code' and the received vector within the transmitted signal (4). , "The form of the heart is ((来:"; (景;> 'The measure of the channel can be defined as the more = round I (four) called .. winter i. Then the measure of (10) that "(1) can refer to the base is Note to e, the "In" natural logarithm described in each mathematical expression. p{y, =^yt) Κν, =ι| is) For each variable node Vi' its LLR information value can be defined as follows: 'The ratio of these values can be replaced by the following equation because the variable node vi is located in the LDPC codeword: 26 1326987 ln p(v, =0,v//r =〇b)_ ln/^(v, =〇,ν /ζ/^〇μ 7(v( = i,v/frr^y ~ (.y)4(1) pool = i,vfr^ where Ev(i) is a group defined as described above starting from Vi When performing the BP (reliability propagation) decoding method described above, the contribution of ιη ρ(ν, = ο'ν;; ' = 〇卜) p{vi = l}vhjT = 〇|^) uses the following relationship Alternative: f \ P ZVv(e)=0l· Lcheck(Uj) = ——ip Σνν(〇=l\y

\e^EcuHu)} y

LcheckCl, j) is the foreign (Εχτ) information of the check node & associated with the edge (丨, j). Further, it is noted that all the edges transmitted from the check node Cj are indicated, except for the side transmitted from the check node Gj to the Wei node Vi. The foreign value is calculated to assist in generating the best estimate of the actual information bit value within the received vector. Also in the method, the foreign information of the variable node Vi associated with the edge (i, j) can be defined as follows: ❿ Figure 4 is a schematic diagram of an LDPC decoding function using a bit metric of 4 根据 according to one embodiment of the present invention. In order to decode the (3)^ encoded signal having the m_bit signal sequence, the functionality shown in the figure can be used. After receiving the I, Q (in-phase, quadrature) value 4〇1 of the signal at the symbol node, the m_bit symbol metric generator counts the corresponding symbol metric 41 at the symbol node, and these symbol metrics 411 It is then passed to the symbol node calculator function block, which uses the received symbols 1 degree 4U to calculate the bit metric 421 corresponding to these symbols. Then, according to the LDPC code bipartite graph, the bitwise metric 421 is passed to the bit node connected to the symbol node, and the code 27 1326987 signal is generated by the LDPC code bipartite graph, and the LDpc code bipartite graph is used to solve the problem. Then at the bit point, the bit node bit node processor calculates the phase soft information of the bit. Then, according to the iterative ambiguous processing 45(), the bit node bit node processor, 430 receives the edge message Medgec 441 ' associated with the check node from the check point processor 440 and uses; k symbol 筇The calculator function block 42 receives the bit metric 421 and updates the edge elimination 4 Medgeb 431 associated with the bit node. These edge nodes Medgeb 431 associated with the bit nodes are passed to the check node processor 44 after the update. At the check node, the check node processor then receives the edge message Medgeb 431 (from the bit node processor 43A) associated with the bit node described above and updates them accordingly, thereby generating the edge associated with the check node The next updated version of the message is shown in function block 442. The updated edge message Medgec 441 associated with the check node is then passed back to the bit node (eg, back to the bit node bit node processor 430) where the bit metric 421 and the bit are used. The current iteration value of the node-related edge message _eb431 is used to calculate the soft output of the bit, which is in the function block: out. Thereafter, use the soft output of the just calculated bit (such as soft output 435) and the previous value of the edge message Medgeb431 with bit 4 o'clock (from the previous iteration, the thorn, : node position sample coffee! i tender input ^ _ _ 韵 妳 - 1 - Operation is shown in the function please. According to the J code bipartite graph used to decode and generate the decoded signal, iterative decoding processing · between the bit node and the check node (ie bit, (10) point Between the 4-point processor 450 and the check node processor 44〇) - the iterative solution processing step of the second-order node-bit node processor 430 and the check-node processor is repeated (4) a predetermined number of iterations ( For example, in time, the basin η is 28 1326987 optional) ° Alternatively, these iterative decoding processing steps can be repeated - until the syndromes of the coffee code are all equal to zero. The soft output 435 is in each decoding iteration process The intermediate bit node node processor 430 is generated. In the embodiment shown in FIG. 4, the soft output 435 can be provided to the hard limiter 460' that makes the hard decision and the hard decision information can be provided to the syndrome calculation. The calibrator to determine the code is that God is equal to zero. The positivity is not equal to the tree, and the _ iterative decoding process 450, as appropriate, updates and passes the edge message between the bit node bit node processor and the check node process _. For example, the edge message wrist 43 associated with the bit node ^ is passed from the bit node processor couch to the check node processor. Similarly, the edge message Medgec 441 associated with the check node is passed from the check node processor to the bit node bit node processor 430. In the embodiment, the softener output and the syndrome calculation performed by the syndrome calculator 470 are executed during the transcoding iteration process of the county. After all the steps of the iterative solution processing 450 are performed, the bit-based soft output output bit is the most A good estimate (e.g., bit estimate 471). In the implementation_method shown in Figure 4, the bit metric value calculated by the symbol node calculator function block 42 is a fixed value and is updated when the bit node value is updated. [Fig. 5] is a schematic diagram of an LDPC decoding operation using a bit. Measure 500 in accordance with another embodiment of the present invention (when performing a iterative iteration). This embodiment shows decoding performed when performing a predetermined number of times. Stack How to perform the iterative decoding process shown in Figure 4, such as η times. If the decoding iteration number is known first, as in the embodiment of the dare number decoding iteration, as in the case of a predetermined number of decoding iterations, the bit The node bit node processor side can use the bit metric 421 itself (instead of updating the corresponding edge message associated with the bit node Medgeb43 in the soft wheel out of the previous embodiment 29 1326987) - processing in addition to the last - Execution is performed in all decoding iterations except for the next iteration (for example, from iteration to 〇. But 疋 'in the last-times iterations ten-bit node node damage calculation soft round, 435. Then soft output 435 is provided to the hard limiter, in the hard limiter _ anger out of the hard decision. This embodiment does not require calculation of the syndrome since only a predetermined number of decoding iterations are performed. Often, when implementing LDpc decoding functionality in actual communication equipment and hardware, the key consideration in design is how to implement hard bribery calculations with the utmost precision, while at the same time having the highest possible accuracy. Similarly, this Cong decoding functional hardware can be implemented in the <number field. The hardware implementation can sometimes be simplified, simplifying the multiplication process to add =, and the division process is simplified to subtraction. In general, the difficulty in performing the calculations necessary to implement the pulse decoding process is that it is necessary to verify the calculation of the scales. For example, a calculation performed within a check node processor (or a bit check processor that performs check node processing) typically requires determining a minimum (or maximum) value from the set of possible values. # When performing these calculations in the actual hardware that performs calculations in the = number field, the minimum (or maximum) value is usually determined at the expense of some accuracy loss. That is, some log correction factors are not used in the calculations, thus resulting in a loss of accuracy. Even in the logarithmic domain, some prior art decoding methods only select the minimum value (or maximum value) from a certain number of possible values without using any logarithmic correction factor. Thus, when operating in the logarithmic domain, from - Groups can be selected - when the minimum value (or maximum value) is selected in the energy value, some inaccuracies are inevitably introduced. Several calculations described above will be introduced in conjunction with the operation of the input value Y and the input value "y". The value can be regarded as a different side message associated with the bit node '(4)妳. For example, 30 1326987 The input value "X" can be regarded as the first side message related to the bit node, the substance (1), and the rounding "y" can be regarded as the bit. The second node message Medgeb(2) associated with the metanode, or vice versa, is processed by the check node of the edge message Medgeb of the bit node lake. Various possible embodiments are given here to generate corresponding checksum nodes. Related: The Medger Cross-Inventor has developed a variety of different methods for performing these calculations, which can still perform high-precision while performing check node processing. These calculations include _* , & ♦ min*-processing, min** processing, min forest-processing. In addition, each of the above processing methods has a corresponding maximum correlation function: min* processing, min*_ processing, min** processing, processing In addition, other processing methods can be used, including min, processing, mint processing, mint processing, and mintt processing. Several calculations described above will be introduced in conjunction with the operation of the input value "χ" and the input value "y". Min* processing and min*-processing: °^take 0^): min(x,y) · ln(i+cxp(-(x-yj)〉 min,(x,y) « min(x,y ) _ ln(l*«p(-|xy|)) zero max* processing and max*-processing: : _x(x,y) + ln(l+exp(-|x-yj)) maxMx,y) = niax(x,y) + 1η(1-βχρ(.|χ.γ〇) min forest treatment and min forest-treatment: min**(xy) = minix^y) - te(l+exp(-| Xy〇) + ln(l+exp(-(x+y))) min**.(x,y) * nunix.y) - ln(l-«P(-lx-yl)) + ln<l -exp(-(x+y))) max forest processing and max yarn-processing: max**(x,y) = max(x,y) +ln(l+e^(-|xy|)) - Ln(l+exp(-{x+y))) msx***(*»y)555 max(x,y) + ln(l-exp(-|xy〇) - ln(l+«p(- (x+y))) min' processing 31 丄 / min' ('less) =|mm* 0, less) min* (ά 〇 0 Other ^Mms. = mn*(x>y)>〇L 〇Other ^-^y) = h^-^y) ^n*^y) > 0 L 0 Others in the __ job _ Na and deal with. Off; tt processing, coffee processing some of the additional functionality of the class. For example, if the amount of land is small, the value of the value is compared with the value of i. The number of symbols is used to calculate the minimum value in the bamboo processing. This symbolic value format makes it possible to find a minimum value by multiplying a plurality of value sheets. This month provides a fast and efficient hardware implementation that performs the above calculations. It can be processed by the access node when the decoding PC is a code signal. In addition, the various structures below will explain how the various calculations described above are performed during the decoding process and where. ώ 6 13⁄4 , v 图 〇 (4) a force: money (four) which c saki ship mad (four) (four) schematic diagram of the example. In the LDPC decoding function 6 shown in Fig. 6, the I, 卩 (in-phase, quadrature) values of the received symbols are supplied to the metric generator 6 〇 3 (i.e., the ship 6 〇 3 shown in the figure). . These I and Q values can be regarded as the listening function blocks from a common gamma. The annihilation function. The block performs preliminary processing on the continuous time signals received from the communication channel. For example, the pre-processing can include frequency conversion, receive filtering, digital sampling, gain adjustment, and/or equalization. These j, 32 1326987 Q values correspond to discrete time signals generated in continuous time signals. The day metric generator 603 calculates a bit metric corresponding to at least one symbol to be decoded. The grading generator 603 performs a symbol metric calculation and converts it into a bit metric. In some of the above embodiments, this separation is performed using two separate Wei blocks: first, the slot metric is calculated from the received I, Q values, and the metric is calculated from the symbol metric. _ Then the bit metric is provided from the metric generator 6 〇 3 to the battalion storage structure (Fig. PPMS 605). The soldier storage structure 6〇5 includes two separate measurement memories _ • and 607 (the hall 6〇6 and the legs 6〇7 as shown). The equivalence generator 6〇3 is providing the bit metric of the corresponding-or-group symbol to the metric memory of the soldier storage structure. • _ when the bit metric provided earlier is measured from the metric storage of the soldier storage structure 605. The body 606 'Jit! ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ The first set of bit metrics corresponds to the decrement of each symbol of the first symbol train (10), the second set of bit metrics corresponding to the second symbol hard _ each Wei metric. _ The rear position of the 70-degree military is transferred from the soldier storage structure 6〇5 and is provided to a set of center check processing H61G (Bcp(10) as shown). - The group/check processor (10) includes a plurality of bit/check processors such as Bcp 611, ..., and Bcp 612. It is to be noted that, according to the present invention, a single set of processing blocks, i.e., bit/verification processors, performs both check bit processing and 'checkpoint node processing'. That is to say, when the T-Ape coded signal is used, the bit node processing and check node processing can be performed using the exact same hardware in the multiple bit/check processor (10). This can be done by using a barrel shifter (BS 615 as shown) in conjunction with the information transfer memory (4) (circle as shown) 33 1326987 ::1: Now. It should be noted that 'by using an efficient addressing scheme (more details === transfer memory 620 can store two types of edges with a plurality of byte sections' bits, and Xiao Ziyi (1) corresponds to the poor news (2) Corresponding to the parity check, and using the important difference between the two shapes and the prior art, the Tongyou has the technology to store the MW's storage structure/equipment to store the two types of non-type and plural bits. The ρ point is associated with the edge. However, the single memory 640 in the present invention can store the side messages of both faces. It is said that when a plurality of bits/check processors are performing bit_processing (ie, the associated side message Medgeb), and these updated bits and bits are already written to the message transfer memory 62, Next, the barrel shifter = 5 ensures that the side messages are read from the messaging memory in a specific and controlled manner so that they are used in the next iteration of the check node processing ( That is, the edge message related to the node is updated (Medgec). The track shift element_615 controls the reading of the message from the message transfer memory (4) to the check node, so that the (four) (four) information transfer memory _ is properly read out so that the same complex number The bit/verification service (10) is used in the subsequent check node processing (i.e., after updating the side message memory 620 associated with the check node, the _hard body of the bit/receive processing H(10) is executed. _Processing and Bit Nodes - Handling Both. This solution to the execution of ·, _峨 is actually reduced in size, and complexity. 615 can also be placed in another connection path between the complex number 34, the number of interrogation processors (10) and the message transfer memory. This embodiment. Bamboo,,,,,,,,,,,,,,,,,,,,,,,, Where is the location, the multiple digits/check processor (10), the bucket I shift 7 benefit 615, and the message transfer memory (4) can be operated in cooperation to execute the edge of the 聪崎收胄_low_目关~e geb to generate the defensive element Soft output. Then the soft output and hard decision corresponding to the decoded bit will be decoded. Generated after generation or when all syndromes are equal to zero, the supply to the face (static random access memory) _ (as shown by 5_0). These hard decisions stored in 3_660 are based on the initial reception of the decoded signal. ^, (4) The best estimate of the decoding ^. Before the last solution iteration or before all the syndromes are equal to zero, the coded bit is extracted to the _. The soft round of the decoded bit is provided to a group function block that cooperatively performs a correction+check by using a parity of an LDPC-matrix that originally generates an LDPC coded signal to read that the decoded bit is a part of a valid code word of the money. The output is then transferred from SRAM 660, which is passed through another barrel shifter called BS 662) and sent to syndrome calculation function block 664 (SYNCALC 664 as shown). If the syndrome passes (ie, the syndrome is calculated for the syndrome, all inputs are equal to zero), the controller 65 is informed ((10) 65〇 as shown) the iterative solution f, , , . bundle. More details of the 650 is in Further, the controller 650 can be implemented to provide a control signal 652 according to the selection #LDpc code 651. For example, the LDPC decoding functionality can be used to decode a plurality of LDpc encoded signals, including DVB-S2-compliant encoded signals. Examples of __ signals include 35 1326987 with VCM (variable coding and modulation) and ACM (adaptive coding and modulation) functionality. The coding rate (and modulation type) of the ldpc coded signal can be based on The training frame changes dynamically. That is, the 'say' first training frame uses the first coding rate and the first modulation type coding, and the second training frame uses the second coding rate and the second modulation type coding. Based on the selected LDPC code 651, the controller 650 provides the & appropriate decoding control signal 652 to other functional blocks within the LDPC ambiguity function 6 这 which ensures that the received I and q values are within the metric generator 603. Calculate the appropriate bit length. In addition, according to the decoding control signal 652, the plurality of bit/check processor 61〇, the bucket/shifting element 615, and the message transfer memory 62〇 can also generate signals according to the transmitting end of the communication channel. The LDPC decoding of the received signal is performed cooperatively, wherein the communication channel provides a continuous time signal, and the I, q values are ultimately extracted from the continuous time signal and provided to the LDPC decoding function 600 for subsequent decoding. The decode control signal 652 notifies the specific bit type/attribute to the plurality of bit/check processor 610, the barrel shifter 615, and the message transfer memory 62 to use the appropriate parity when decoding the received signal. Check matrix. The decode control signal detachment indicates that the bucket shifter 615 pairs the edge message Medgeb associated with the bit/meta-segment (and the side message Medgec associated with the check node - depending on when; j. LDPC decoding functionality _) Perform an appropriate level of shifting. Since the barrel shifter 615 performs the appropriate shift of the two side messages, the edge message Medgeb associated with the bit point (and the edge message MedgeO associated with the check node are stored in the message transfer memory in a manner The body 62 wipes, so that they can 'retrieve from it' in order to reduce the S/School turn, _ perform iterative decoding process - the follow-up step bribe makes the mind pay attention to, After the processing of the plurality of bits/check processing (4) 〇_check node, the next bit byte 36 丄: before the Z processing step, the barrel shifter 615 must not perform shifting on it. After the bit (10) can be dazzled (ie, multiple bits / check processor

Both 1 70-node processing and check node processing. For example, when decoding a set of X ΓΓ 'if the execution of the outline (four) is followed by N, the initial shift is performed to make the shifted bits back to their initial hypothesis before the bit node processing has a specific set of The _coded signal will be C-decoded. The amount of shift performed by the toilet-shaped shift thief 615 can be implemented in a _ (read-only memory) device to provide very fast calculation and processing when decoding the actual signal. . The shift value stored in j_ may be selected based on the connectivity of the edge between the bit node and the check node in the bipartite graph that produces the Cong coded 峨. The use of the controller 650 ensures that the LDPC decoding functionality _ can decode various coffee 2 code signals, and the signals complying with the D job are among them. However, the _decoding power 600 can also be used to perform decoding of other Cong coded signals. In addition, the function provided by the controller is used to perform the decoding of the _coded signal which is frequently changed on a block-by-block basis by performing the coding rate and/or (including the fresh set shape and mapping). For example, a block can be considered as a symbol group within the training box. In some cases, a training box • can include multiple blocks. Compliance with DVB-S2 signals - all symbols in a training frame have a common coding rate and modulation (including cluster shape and mapping), and the coding rate and / or modulation is based only on the training box . As described above, the plurality of bit/check processors 61 includes a set of bit/check processors such as BCP 611, ..., and BCP 612. In a number of bits / check processor _ in the real 37 1326987 how many galax / she is in the face of the choice. The village roots check the number of fines to choose how many bits/checking processors to use, including the decoded bits, the number of bits, the number of bits, the number of bits, the number of bits, the number of bits, the amount of memory The throughput speed is .· and the required area is _ total area. Selecting the bit/check processing (4)_real_multiple bits/check processing 1§ will result in more parallel class processing. It is also noted that several examples of macroblocks 699 can be implemented (as shown in Figure 9) to support parallel processing of the ingress. In this case, the macroblock_ includes a soldier storage structure 605, a plurality of bit/check processors (10), and a message transfer memory (10). Other examples of macroblocks are used in other embodiments that will be described below to support more efficient implementations and consume a smaller total area. In general, the total number of macroblocks selected should be such that the total area of the equipment is as small as possible. Regarding the macroblock 699, it is also desirable that the barrel shifter 615 need not be implemented therein. In this embodiment, the barrel shifter is actually implemented outside of macroblock 699 to serve a plurality of macroblocks. However, the barrel shifter 615 can also be implemented within the macroblock without the scope and substance (as will be described in other embodiments below). However, it is better to say that it is better to place the barrel shifter on the outside of the macroblock _ Lu, because this will not delay or slow down the messaging memory (10) (which can be implemented using the memory) Access time. When the barrel shifter 615 is located outside the macroblock 6', it is necessary to use the pipeline register (pipeline registe〇 to ensure access synchronization to/from the message transfer memory 620. -' and 'each of the LDPC decoding functionality' The function block implementation (by using the bucket shifter 615, in conjunction with the messaging memory 62 (four) single function block), allows the messaging memory 620 to use a single port of storage; this inevitably occupies 38 1326987 devices than the dual port storage It has less area and consumes less energy than a dual-port storage device.: As described above, 'using pulse decoding functionality _ can decode various types of LDPC encoding minus. The town will provide - bit and word width A specific example, and the number of bit/check processors in a plurality of bit/check processors (10) to show their relationship in a particular case. The Q values provided to the metric generator 603 are each It is 7 bits. The metrics generated by the metric generator 603 using the 7-bit I and Q values are each 6 bits. Therefore, each of the two separate metric memory coffees and 6 〇 7 is operated with 6 bits. Value; this The length of the DVB-S2 block is 64,800 bits. When designing a structure that can decode DVB-S2 signals, the bit metric output from the metric generator 63〇 needs to have 360x6 bits; that is, there are The same value, • each value is 6. The bit metric can be supplied to the parallel configuration of the 36 〇 unique bit / 'check processor. More specifically, the multiple bits / check processing $ _ includes chat 6 ι U 1 bit check processor), ..., and BCP 612 (sixth bit / check processor). The side message output from the 360 individual bit/check processors is a 6-bit value. Thus, the total output of the 360 individual bit/check processors is a fine-grained bit; each bit/check processor outputs a 6-bit side message. Similarly, the edge message of the appropriate shifting element within bucket indexer 615 is also every 6 bits. Therefore, the Qing Shift ride output also has a hill, - the position. Similarly, when decoding the signal following 眺S2, the message transfer memory will be 792x360x6 bits. So there are 360 unmixes output from __. It is also noted that the bit values in the above description are just one possible embodiment of the implementation/decoding functionality. According to the present invention, different amounts of money are used for the respective values in the above embodiments, and it is also possible to implement a unique embodiment. 39 1326987 The mid-vein of the embodiment shown in Figure 7; the decoding functionality is exactly the same as the assignment function _ in Figure 6 except that virtual 埠 埠 记忆 memory is used? 〇5 (face 7〇5 as shown in Fig.) replaces the soldier's wrong structure. The virtual double 埠 metric memory 705 ' can support dual special storage management, even if it is a 單埠 storage device. By making it off? The virtual double 蟑 metric memory 705 replaces the soldier storage structure 〇5 (including the double 埠 storage structure) in FIG. 6 and the LDpc decoding functional paste can significantly save space. In the embodiment shown in Fig. 7, the value of the DVB-S2 compliant virtual double 埠 metric memory 7 〇 5 operation (10) χ 36 〇χ 6 bits is processed similarly to the description in Fig. 6. In the LDPC decoding function 800 of the embodiment shown in FIG. 8, the 丨, Q input, metric generator 803 (such as MG 803 as shown), the controller 850, and the corresponding control based on the selected LDPC code 851 The signal 852 is very similar to the LDpc decoding functionality shown in FIG. However, compared to macroblock 699 in Figure 6, LDPC decoding functionality 8 includes a slightly modified macroblock 899 (MB 899 as shown). Macroblock 899 can be copied a certain number of times to assist in providing 11% more efficient than the previous embodiment. (;: Decoding functionality. Macroblock 899 includes all the functionality that can be replicated to achieve more parallelism. Processing Structure In the embodiment shown in Fig. 8, the barrel shifter 815 is included inside the macro block 8. The barrel shifter 815 in this embodiment and the barrel shifter 615 in the foregoing embodiment. Or the 移位-shaped shifter 715 is different in that the barrel shifter 815 in this embodiment only serves the components within the actual macro block 899 in which it resides. Instead, the barrel shifter 615 or bucket The shape shifters 715 each serve the ^26987 32 of the macro block 699 and the macro block 799 in the respective embodiments. Thus the barrel shifter 815 has no pick-up shifter 6丨5 or barrel shift The difference between the position of the shifter 815 and the barrel shifter 615 or the barrel shifter 715 & is appropriately shifted by the subsequent check node processing or bit node in the _0 Also, since the position of the ♦ indexer 815 is different from the barrel shifter 615 or the barrel shifter 715: The shifting element removes and bribes 86〇 for reconfiguration to be compatible with this sequence of processing. A macroblock example that can decode the compliant-S2峨 design including 18 solutions is provided to the 1 degree generator 8〇3 The I>Q value is 7 bits each. The metric measure generated by the metric generator using the 7-bit I and Q values is a value of 6 bits each. However, each block of the macro block 899 in Fig. 8 The implementation is different from the macroblock 6卯 in Figure 6. The soldier storage structure 8G5 (PPMS 8G5 as shown) includes the measurement memory 8〇6 spear 807 (as shown in Figure 805 and MM 807). Operates on 180x120 bits. These 120 bits are each implemented as 20x6 bits; that is, there are 2 separate values, each value is 6 bits. The bit metric output from the ping pong storage structure 805 also has 12〇. The bits (i.e., each 20x6 bits). These bit metrics provided to the plurality of bit/verify processors 810 can be provided to 2 separate bits/checks of the parallel configuration located within each macroblock. More specifically, the plurality of bit/check processors 810 include BCP 811 (1st bit/check processor) '...' and BCP 812 (No. 20 bits/check processor. From these 20 separate bit/check processors 810, the appropriate side messages are output in 120 bits (ie, 20 x 6 bits per 41 1326987). Each of the 2 individual bit/check processors in each macroblock has a total of 120 bits of output (ie, fine bits). The complex bits are corrected by the processor. 20 bits/bit processing Each of the outputs outputs a 6-bit side message. Similarly, the side message after the appropriate shift in the barrel shifter 815 is also 12 bits (i.e., 2 〇χ 6 bits). Therefore, the barrel shifter 815 also has an output of 12 ( (ie, 2 〇 young). Similarly, the decoding conforms to the DVB-S2 message, and the message transmission key needs to transmit a value of 792 χΐ 2 。. Thus, the decoded bits of 12 bits (ie, the drain bits) are output from SARM_. It is to be noted that the barrel shifter 815 can be implemented inside or outside of any macro block _. If the barrel shifter 815 is implemented outside the macroblock_, a single bucket shift can calculate the side message value of the x6 bit, that is, when the #barrel shifter 815 is implemented inside the macroblock 899' Then there will be 18 separate barrel shifters (i.e., one of each macroblock 899) that computes the edge message value of 120 bits (i.e., 2 〇χ 6 bits). It is also noted that the number of macroblocks 899 can be selected such that the total area of the LDpc decoding functionality 800 is as small as possible. For example, to decode a signal that complies with dvb_s2, the number of macros < blocks multiplied by the number of complexes per check block 'checksum ^ _ bit / check processor should equal . For example, a parallel processor can be selected to support the decoding required to decode DVB-S2-compliant signals. In order to support higher output, more parallel processors are needed. - In the LDPC decoding functionality of the embodiment shown in FIG. 9, I, q input, quantity and degree generator 903 (MG 903 as shown), controller 95, and corresponding selection based on selection The control signal 952 of the LDPC code 951 is very similar to the y) PC decoding functionality shown in Figure 7 of 42 1326987. However, it is the same as that contained in Figure 7. Compared to the 799, the LDPC decoding functionality is 9 〇〇. It includes the modified macroblock _ (as shown in the figure (4)). • In the embodiment shown in Figure 9, the 彡狡a _ bucket tree position 915 is included in the macroblock _. The barrel shifter 915 in this embodiment is in the +wb embodiment. The barrel shifter 615 is different from the barrel shifter 715 in that it is the same as the barrel shifter 915 in the embodiment, serving the actual _99 _ Mail. Instead, the bucket 615 or barrel shifter 715 each serves all of the examples of the macroblocks and python blocks 799 in their respective embodiments. Thus the barrel shifter 915 is not as complicated as the barrel shifter positive or the bucket = shifter 715. ^ The position of the barrel shifter 915 is different from the barrel shifter 615 or the barrel shifter 715 'Must be careful to ensure that the edge message is properly shifted for multiple bits/check processing H 91〇_Subsequent check node processing or bit node processing. Also, since the position of the barrel shift ϋ 915 is different from the barrel shifter 615 or the barrel shifter 715, the barrel shifter 962 and subsequent reconfiguration are required to be compatible with this different zero. Order processing. Similar to the embodiment of Figure 8, macroblock 999 in Figure 9 can be copied a predetermined number of times to assist in providing LDPC decoding functionality that is more efficient than previous embodiments. Macroblock 999 includes - all functions that can be copied to achieve a more parallel processing structure. A design that can decode DVB-S2 compliant signals includes 18 separate macroblock examples. The I and Q values supplied to the metric generator 903 are each 7 bits. The metric measure generated by the metric generator 9 〇 3 using the 7-bit I and Q values is a value of 6 bits each. However, the implementation of each block of macroblock 999 in Figure 9 is the same as macroblock 799 in Figure 7 not 43 1326987. The virtual double 埠 metric memory 905 (PDPMM 905 as shown) operates on 180x120 bits. These 120 bits are each implemented with 2〇X6 bits; that is, there are 2 unique values, each with 6 bits. The bit metric output from the virtual double metric memory 905 also has 120 bits (ie, each is 20x6 bits). These bit metrics provided to a plurality of bit/verify processors 91A are provided to 2 separate bit/check processors in parallel configuration within the parent macroblock. More specifically, the plurality of bit/check processors 910 include BCP 911 (1st bit/check processor) '..., and BCP 912 (20th bit/check processor). From these two single-bit/check processors 910, the appropriate side messages are output in 12-bit units (i.e., each is 20x6 bits). Thus, 2 individual bit/check processors within each macroblock 999 have a total of 120 bits of output (i.e., 2 〇χ 6 bits). Each of the 20 bits/check processors of the plurality of bits/check processors outputs a 6-bit side message. Similarly, the side message after the appropriate shifting element in the barrel shifter 915 is also 120 bits (i.e., 2 〇χ 6 bits). Therefore, the barrel shifter 915 also has a total of 120 bits (i.e., 20 x 6 bits) of output. Similarly, when decoding a signal conforming to DVB-S2, the message transfer memory 92 does not need to transmit the value of the 792 χ 12 () lu bit. Thus, 120 bits (i.e., 2 〇χ 6 bits) of decoded bits are output from the SARM 960. As with the other embodiments, it is noted that the barrel shifter 915 can be implemented inside or outside of any macro block 999. If the barrel shifter 915 is implemented outside of the macroblock 999, a single barrel shifter can compute a side message value of 360x6 bits. However, when the bucket shifter 915 is implemented inside block 999, then there will be 18 separate bucket shifts (ie, one of each macroblock 999), which operates 120 bits (ie, Side message value of 20x6 bits). :326987. It is also noted that the number of macroblocks 999 can be selected such that the total area of the LDpc gamma function 900 is as small as possible. For example, in order to decode a DVB-S2-compliant signal, the number of macroblocks multiplied by the number of bits per macroblock 999/the number of bits/check processors in the check processor should be equal to 360. For example, 360 parallel processors can be selected to support the output required to decode DVB-S2-compliant signals. To support higher output, more parallel processors are needed. It should also be noted here that the controllers in the various embodiments described above provide synchronization information for each of the other unblocking function blocks. More specifically, this includes generating timing signals for each corresponding metric generator, metric memory, complex bit/check processor, barrel shifter, and messaging memory. These timing signals are provided to each of these functional blocks, regardless of how these functional blocks are implemented in a particular embodiment. If necessary, these timing signals can be appropriately modified to suit the implementation of a given function block. For example, depending on whether the barrel shifter is implemented inside or outside the macroblock, the timing signal needs to be processed differently. Recklessly, as described above, each of the different LDpc decoding functions in the various embodiments can process and decode different types of LDpc encoded signals, including LDPC encoded signals generated using different parity check matrices, and have different The coding rate and/or modulation type, and will be based on training boxes or even block-by-block LDPC coded signals. For example, a block can be thought of as a group of symbols within a training box. In some cases, a training box may include a plurality of blocks. The controller in each of the above embodiments may also use π programming and optional parameters for each LDPC code. These programmable and selectable parameters include the bit node and check node degrees for each LDpc = submap. In addition, these programmable and selectable parameters include information transfer and bucket shifter selection parameters. Parity ΓΙ' Pair: The information bit node provides a check cut for the bit. Similarly, for 'Y', a checksum is provided for the bit cut. By doing this, you can mix the two... in the same depository device (for example, the same Na Na). This is possible because the bits +q of any 2ΓΓ node are tolerable because they are +ι or the value of the sentence is not meta: _ is not used in __) the bit of the parity bit node 'f The order of the multiplexed _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ For example, the _ hingling process engine will process the engraved information bit nodes (e.g., node 〇 to node 359) corresponding to the check nodes (i.e., G, q, 2q, deductions). For the even parity bit node', the lion processing engine will process a bit node (eg, η, kiss, ^ 'ring' . . . ). These parity bits correspond to 36 校验 check nodes (for example, m m+q rings ' ra+3q ’ . . . ). By doing so, all _ side messages are stored in the _ location of the storage device and can be used during check node processing and bit node processing. If you don't do this, you need two separate storage devices. (1) The solid storage device stores the edge corresponding to the signal bit 7〇_; and the other storage device stores the edge message corresponding to the parity bit). The adaptability of such compatible LDpC coded signals allows the LDPC decoding functionality in the various embodiments described above to be interpreted as a wake-up, coded signal: FIG. 10A, in accordance with an embodiment of the present invention The schematic diagram of the functional generator is shown in Figure 7. The SF generator (the MG shown in the figure) receives the I and Q values of the 46 1326987 related symbols for which the metric will be calculated. The ϊ and Q components are separately separated and provided to the I processing channel and the Q processing channel in the symbol metric calculator function block (SMC as shown). More specifically, the received I component (Rxj as shown) is provided to the processing channel, and the received Q component (RX-Q as shown) is provided to the Q processing channel. Along these respective processing channels, the difference between the shop and its number (associated with the appropriate modulation used to generate the miscellaneous symbols) is determined. More specifically, in the 丨 processing channel, the ί coefficient (LC〇efj as shown) is subtracted from the received I component (i.e., Rx_I). Similarly, in the Q processing channel, the coefficient of subtraction is subtracted from the received q component (ie, Rx_Q) (Q-Coefjh as shown in the figure then squares each generated difference (ie, it is self-contained with itself) Multiply. Then add the resulting squared differences and use the variance factor (represented by VF, which is equal to 1/(2σ2), where 4 standard deviation noise coefficients). Then the symbol metric is calculated. The function block output symbol metric (synunetric(i) as shown) 'The symbol metric is then provided to the bit metric calculator function block. After providing these symbol metrics to the bit metric calculator function block, Calculate the bit metric of the bit of interest for each period. As shown in the figure, calculate the bit 兀罝 of the bit ^. First, use all generated symbol metrics whose bit value m is 〇 to perform coffee processing. It is also possible to first perform, min* processing using all generated symbol metrics of the bit value ^ j. Once the results of each processing are determined, the difference between them is determined next. Use direct _ The method of calculating the bit metric using symbol metrics in the prior art does not use min processing or _ processing. This is an important difference from the prior art method, which also makes the performance better than the prior art. Improvements 47 1326987 The calculations performed by the metric generator can be expressed in mathematical formulas. The calculation of the symbol metrics synunetric(i) is performed as follows: sMtncCi)=l/(2^)x [(^ί^ΐ^ί^+( Κχ_〇_ρ_006ί〇2]; The operation-counting occurs in the symbol metric calculator function block shown in the figure. Then, the bit metric of the specific bit m is calculated as follows: bit_metCbit m)=mmall sym_nietric( i) with bit m=0]-min*[all syin_metric(i) with bit m=l] This - occurs in the calculated bit metric metric bit t-degree calculator function block (10)). Stomach It should also be noted that the calculation of the 'bit metric metric metric calculator' can also be performed using only the min processing as opposed to the min* processing. The various decoding embodiments described herein are suitable for decoding various different types of LDPC coded signals, including LDPC coded signals whose modulation and/or coding rate is based on a block-by-block variation. The LDPC coded signal includes four graphs below the Peng coded signal that complies with the currency standard. The following figures show the use of different coefficients. These coefficients are used for different modulations (ie, each one includes a group of townships). The appropriate metric is calculated for the associated symbol with the corresponding modulation of the mapping of its domain set points. 11 is a diagram showing a QPSK (Quadrature Phase Shift Keying) cluster u〇〇- and its corresponding binary map and QPSIU^, numbers employed therein, in accordance with one embodiment of the present invention. Each cluster point is appropriately labeled. For example, the cluster points on the QPSK cluster map are labeled as follows: 48 0 cluster point 1, 1 cluster point 01, 2 cluster point 10, 3 cluster point 11. In the figure, the mark of his cluster point can be executed similarly to i, and can be shown in the figure. Each of these cluster points can be represented by a coefficient, from T

The I and Q axes of the Vittor extend. Since the cluster shape is symmetric about the origin of the Bu Q: the actor - two coefficients to represent all the cluster points in the graph. Because of this symmetry, this is the same value' but the opposite sign. Thus, a user who is in a QPSK-shaped cluster can only see two different green values. More specifically, the Cartesian coordinates of each point in the cluster can be described as follows: 0 cluster point 00 today Cartesian coordinates (PJ, PJ), 1 cluster point 01 + Cartesian coordinates (PJ, P_3), 2 Cluster point 10+ Cartesian coordinates (p_3, P_1), 3 cluster points 12-> Cartesian coordinates (p_3, P_3). Figure 12 is a diagram of an 8 psK (phase shift keying) cluster η 卯 and its corresponding binary map and the 8 级 coefficients used therein, in accordance with one embodiment of the present invention. Each point in this cluster can also be represented by a coefficient extending from the 丨 and Q origins along the I and Q axes of the 2D map. The 8 PSK cluster shape also uses 4 cluster points, but the locations of the 4 cluster points with respect to the I and Q origins are smaller than those in the QpSK cluster shape in the above figure. It can be seen that, as in the QPSK modulation of the previous embodiment, some of the same coefficients can be used to interpret the cluster points within the 8 PSK modulation. All of the clusters in the 8 PSK shape are described. Only four different coefficient values are needed for each point. More specifically, the Cartesian coordinates of each point in the cluster can be described as follows: 0 cluster point 000 > Cartesian coordinates (P - 1, P_1), 1 cluster point 001 today Cartesian coordinates (PJJ, p_〇), 2 cluster point 010-> Cartesian coordinates (〇, p_2), 3 cluster points 011 + Cartesian coordinates (p_3, p-3), 4 cluster points 1〇〇"> Cartesian coordinates (〇, p_ 〇), 5 cluster points + Cartesian coordinates (pj, P_3), 6 cluster points 11 〇 + Cartesian coordinates (ρ_3, ρ_ι), 7 cluster points 111 Descartes coordinates (〇, p - 2). Figure 13 is a schematic illustration of a 16 QAM cluster 1300 and its corresponding ten', carry map and its 四(iv) 16(10) filaments in accordance with the present invention. Similar to the embodiment described above, each point in the cluster can also be represented by a coefficient, which is torn from 1.峨16 (10) __ All the cans in the set? (4) The group of coffee-shaped groups is more specific 'The group is fine. Each can be described as follows: 〇 Cluster point (9) Descartes coordinates (QJ, Q_l) , 1 cluster point ~ 1~> Cartesian coordinates (Q-Bu Q-2), 2 cluster points _) + Cartesian coordinates (〇, Q), 3 cluster points 0011·> Cartesian coordinates ( Q—〇Q—〇), 4 clusters (four) whistle phase coordinates (q_3, qj), 50 1326987 5 cluster points 0101 + Cartesian coordinates (Q-2, Q-〇, 6 cluster points 0110+ Descartes coordinates (q_3 , q—0), 7 cluster point 0111·> Cartesian coordinates (Q_2, q_0). 8 cluster point 1〇〇〇~> Cartesian coordinates (q_3, q_3), 9 cluster point 1001 Descartes coordinates ( Q_2,q_3), A cluster point 1010 Descartes coordinates (q_3, q_2), B cluster point 1011 + Cartesian coordinates (q_2, q_2), C cluster point 1100; Cartesian coordinates (qj, q_3), D cluster point Cartesian coordinates (q_〇, q_3), E cluster point 111〇·> Cartesian coordinates (Qj, q_2), F cluster point Cartesian coordinates (q_〇, q-2). Figure 14 is in accordance with the present invention. 16 APSK cluster of one embodiment 14〇 〇 and its corresponding hexadecimal mapping and a schematic diagram of the 16 APSK coefficients used therein. Similar to the above embodiment, each point in the cluster can also be represented by a coefficient, from !, L origin. The 丨, Q axis extension of the graph. More specifically, the stagnation coordinates of each point in the cluster can be described as follows: 〇 Cluster point 0000 + Cartesian coordinates (A 5 , Α _5) 1 Cluster point 0001 Descartes coordinates (A 5, Α_7) 2 cluster point 0010~> Cartesian coordinates (a 7 'A-5) 3 cluster point 0011 + Descartes coordinates (a 7 , A-7) 4 cluster points 〇 1〇〇~> Descartes Coordinates (a 1 , A_0) 5 cluster points 〇1〇1·> Cartesian coordinates (a 1 Ά_2) 51 1326987 6 cluster points 0110 + Cartesian coordinates (A_3, A_0), 7 cluster points 0111 + Cartesian coordinates ( A_3, A-2) · 8 cluster points 1000_> Cartesian coordinates (A_0, A_1), '9 cluster points 1〇〇1>> Cartesian coordinates (A_〇, a-3), A cluster point 1010 + Cartesian coordinates (A_2, Aj), B cluster points 1011~> Cartesian coordinates (A-2, A_3), C cluster points 11〇〇«> Cartesian coordinates (a", A-4), D Cluster point 110 1_> Cartesian coordinates (A_4, A-6), φ E cluster point 1110 + Cartesian coordinates (A_6, A-4), F cluster point 0111 + Cartesian coordinates (A_6, A-6). It should also be noted that each of these modulations (QPSK, 8 PSK, 16 QAM, and 16 * APSK) can also be used in the DVB-S2 standard. Figure 15 is a schematic illustration of a modulation coefficient table in accordance with one embodiment of the present invention. This shows how to choose the appropriate coefficients based on the modulation used to calculate the relevant metrics. It can be seen from the table that 'different values' are selected for the coefficients for each modulation. Thus there can be as many as 麝 coefficients (eg 'for 16 APSK modulations'), 4 coefficients (for 8 or Μ _ 调

For example, when calculating a metric that is related to any modulation with QPSK 11 as long as it is selected, modulation is used for the calculation of the metric. When modulating a symbol-dependent metric, select 52 1326987 and C 〇 (the values of 3 are p-i and p-3. Similarly, when modulating the symbol-related metric, c〇efJ), c〇 eU, (4) ^ coffee, can be selected as P〇, Pl, p2^p3 oe ~ values w _ Μ and P-3 for the other modulation types described by the table, taking into account the cluster shape and corresponding scale __ change The mapping can be chosen in a similar way (for example, C〇ef-〇 to c〇ef-7). By using this method, the value can be selected based on the desired modulation. Thus, a single metric generator can be used to perform the Newton calculation for a variety of aspects. The following county _ bribe _ volume; several embodiments of the structure. 16 , 17 , and 18 are schematic diagrams showing the structure of the metric generation in accordance with several embodiments of the present invention. °, as shown in Figure 16, the 1 degree generator structure 16〇〇, its functionality can be divided into the symbol metric calculator function block (SMC as shown) and the bit metric bit metric calculator function ^ MC) shown. The symbol metric calculator function block calculates a plurality of symbol metrics (such as the synunetHes), and calculates the metrics for the thief bribes to calculate a plurality of metrics (bit metrics as shown). The metric generator structure 1600 can; hardware, perform the above-described fresh calculations, and have the ability to be compatible with different code rates and/or modulations. According to the variable coding rate functionality of the present invention, in order to support multiple coding rates and/or modulations, a plurality of I and Q coefficients are used, the 丨 value of the received symbol (with 丨) and a plurality of I coefficients (eg, The "differences between LCoef-O, ... and I_Coef-7) shown in the figure are all calculated simultaneously. Similarly, the q-value (Rx_Q) of the received symbol and the complex Q-factor (Q as shown) The "difference" between -Coef - Ο, ... and Q - Coef_7) is calculated simultaneously. 53 1326987 The accuracy of these values is 9 bits in some embodiments. It should be noted that these "differences, They are all calculated by using the symmetry of the above cluster, in which only addition is performed, and no subtraction is performed, thereby saving hardware. Then squash each of these nucleus (generated by performing addition and coefficient selection based on the symmetry of the lion-like symmetry). In some embodiments these square values have an accuracy of 18 bits. These squared values are then rounded. Thus, in some embodiments the precision of some values is rounded to 9 bits. These rounded values are then passed to the corresponding registers (rEg as shown). After being placed in its corresponding register for a predetermined period of time (eg, one clock cycle), when a predetermined number of significant bits are selected from the total number of remaining bits, the round-out of each register is transferred to the corresponding saturated function block. (SAT as shown). ·, Μ-yO of each saturated function block. In some embodiments the values of these values are 7 bits. The t output is then secreted to the squared output multiplexer (10), or the squared output is shown in SO MUX). The Deng group selects the value from the squared output MUX. This choice is governed by the modulation and/or coding rate provided by a controller (as shown in Figure N). The operation of certain functional blocks that control hop decoding functionality is controlled according to the decoded coffee coded axis rate and/or modulation as described in other embodiments above. Ingenuity change · In the square output MUX by using the controller to mention. Appropriate item material distribution φ miv 丄 fine shot selection, pay output output output, and is selected and added version of the year (four) heart, as shown in the figure S (As shown by U〇〇ut, with item 54 丄-Q Q_Coef) 2 ' is added as shown by Sq_q 〇 (10) in the figure. From the square wheel out • The 1 related round of the output shows the I-axis distance'. The ί component of the received signal is matched with the lion! The coefficient ^ is on. ;, ϋ «The Q-related output of the output in the square output 指示 indicates the 〇-axis distance, which is separated from the predetermined q-factor of the cluster point corresponding to the appropriate cluster based on the appropriate coding rate and/or modulation. , ', select the added value obtained by adding the appropriate output from the square wheel, and then the register (shown as REG in the figure)' and stay in the register for a predetermined time (for example, - one clock cycle) ). The variance factor is scaled for each value corresponding to the weave: center (5) 2) and at the end of the five-person period, the ideal sufficiency value is obtained. The standard deviation of the standard value of the signal received by σ疋. Then, the symbol metric calculator function block (shown in Figure XI - Patience) is generated from the symbol metric calculator function block and is provided to the red metric bit. The bit metrics of the Brix calculator are calculated in the corresponding bits (as shown in IntjetAs in the figure). For each element (6) of the rib, the base 7 code rate and/or modulation (determined and controlled by the signal provided by the controller, as shown in the figure), the bit metric metric calculator function block For all W symbol metrics (ie, ^ _ gamma. Also _, the bit function block is :: mother!: all the symbol metrics with a median value of 1 in the meta-position are executed _. Similarly, the bit reading money The operator Wei block rides the W degree (ie, the machine 1C value) to perform the rain* process. That is, the bit metric calculator function block performs the min* process for 55 1326987 degrees, thereby generating the corresponding bit. The difference between the two separate min* processing results, as measured by bitjnetrics in the figure, is determined by the total value of each symbol in each bit position of the meta-symbol. The (10) real-cut towel, the measurement unit of the bit measure can perform direct min processing (without logarithmic correction factor). In this case, the difference between the two separate direct min processing results can be determined, thereby Generate the corresponding bit metric (as shown by bit_metrics in the figure.) As shown by the other possible metric generator structures, there are many other possible square wire implementation metrics that produce H-functions without departing from the scope and spirit of the present invention. Each of these different metric structures can support variables. Coding 钵//modulation signal. In the metric generator structure plane, the variance signal is scaled for the output signal of the squared input 。. Optionally, the signal factor scaling can be performed at an earlier stage in the process. In some cases This method provides a better and more efficient implementation. As shown in Figure 7F, the latitude generator structure is deleted, and the operation of the symbol metric calculator function block (as shown by SMC in the Lutu) is the same as in the previous embodiment. The metric generator has different structural planes. The bit twip bit 1 _ 4 controller function block (shown in the figure) is similar to the straightness generator structure 1600 of the previous embodiment. The metric generator of the previous embodiment The structure 16 is similar to the 'TM degree generator structure 1700 receiving a coded 'rate and/or modulation control signal from a controller (shown as c〇N in the figure) to control the different function blocks of the metric generator structure. 'Operation. Similar to the embodiment of the above-described metric generator structure 1_, in order to support multiple octave rates 56 1326987 and/or modulate '$ degrees, the H structure (10) uses a plurality of Q coefficients. The I value of the received signal (Rx - The difference between I) and the complex I coefficients (as shown in Lad.. and LCod-7) is calculated simultaneously. Similarly, the 卩 value of the received signal ((4)) and the complex Q coefficients (such as The difference between Q-c〇efJ), ... and Q_c〇ef_7 in the figure is calculated simultaneously. In the implementation of the financial, the accuracy of these values is 9 digits. It is important to note that all of these "differences" can be calculated by using the symmetry of the above cluster, in which only addition can be performed without subtraction, thus saving hardware. ',,,: After each such difference" (generated by performing the addition and the coefficients selected appropriately based on the cluster shape), the values are passed to the corresponding registers as shown in the figure. Medium_shows). After staying in its corresponding register for a predetermined period of time (eg '-clock cycles), the sigma factor scaling is then performed on the output of each corresponding register (see Figure fSF (G 7 ( m/(7)). Sigma, is the standard deviation of the standard noise of the received signal. After the sigma scaling, continue to round the = and then pass to the register (still as shown In the registration, it is shown in the registration (four)·after (for example, a clock), each output is passed to the absolute value of the = and the secret block. The simple value of the square and the round of the square block Rounding is performed, and the newton is passed to the subtraction of the subtraction (as shown in Figure )). The output of the register is expressed as a ! value (ie, free of gravity, .··^) and (4) (ie, mother >-y〇'Sq-yl,...Sq_y7). Money provides these outputs to the squared output Use the device, (ΜϋΧ)' or square output MUX (as shown in s〇MUX in the figure). Select the value from the square output ,, which is selected by a controller (as shown in (10)) / and / (10) code Rate Wei. As described in the other embodiments above, 57 (4) is based on the coding rate and/or modulation of the symbols of the (4) compiled signal to control the caliber (4). Come. In the square output ugly, use the signal provided by the controller to make the appropriate selection of the item <the output from the squared output ,, and select and add. For example, the item (RXJ+LC〇(0 is shown in the figure as ScUO) As shown by out, the term, Q_oef-〇) 2' is added as shown in the figure Sq_Q〇out. The I-related output output from the square wheel does not indicate the distance from the axis, and the signal will be received. The I component is separated from the predetermined! coefficient corresponding to the cluster point of the appropriate cluster based on the appropriate chore rate and/or modulation. Similarly, the Q correlation output from the square output sigma output indicates the Q-axis distance and will receive the signal. Q-knife with cluster points corresponding to appropriate clusters based on proper coding rate and/or modulation The predetermined Q coefficients are separated. After the addition operation, the values are rounded up before the value is calculated from the symbol quantity to the bit metric calculator function block. The operation of the bit metric calculator function block within structure 1700 is similar to the operation of the bit metric calculator function block in the metric lu generator structure 1600 of the previous embodiment. The metric generator structure 18 shown in FIG. The symbol metric calculator function block (shown as SMC in FIG. 8) is different from the metric generator structure 16A of the foregoing embodiment and the metric generator 1700 of the foregoing embodiment, and the bit metric bit metric calculator function block The operation (shown as BMC in Fig. 8) is similar to the metric generator structure 16A of the foregoing embodiment and the metric generator 1700 of the foregoing embodiment. Also similar to the metric generator structure 1600 of the previous embodiment and the metric generator 1700 of the previous embodiment, the metric generator 1800 58 1326987 • receives the arranging rate and/or from a controller (shown in (10) of FIG. 8). Or modulating the control signals to control the operation of different functional blocks of the i-degree generator structure 1800. . - In the metric generator structure 1800, the received bQ value is first scaled by the sigma factor. The received I and Q values are passed to the register (shown as REG in the figure). After staying in the register for a predetermined period of time (for example, one clock cycle), the sigma factor is scaled for these inputs and Q values (as shown in _.7071/(7) in the figure). Where Sigma, π, is the standard deviation of the standard noise of the received signal. After the sigma _ is released, the values are rounded and passed to the register (as shown by REG in the figure). After staying in the register for a predetermined period of time (e.g., one clock cycle), these scaled I and Q values are then passed to the corresponding summation block. Similar to the embodiment of the above-described metric generator structure 1_ and the metric generator structure measurement, in order to support multiple coding rates and/or modulations, the metric generator structure uses a plurality of scaled I, (10) H received signals. The 丨 value (Rx—and the plural ^ coefficients (as shown in Ubefj in the figure), ... and 7) are all calculated simultaneously. Similarly, the difference between the received signal (4) (Rx) and the plurality of Q coefficients (shown as Q-Coef_0, ... and Q_c〇ef_7 in the figure) is calculated simultaneously. In some embodiments the precision of the 'value is 9 bits. It should be noted that by using the symmetry of the above cluster to calculate these "differences", the wipes only perform f addition, paste subtraction, and thus save the hardware. Then for each such " The difference value, (generated by performing addition and a coefficient appropriately selected based on the symmetry of the cluster shape) performs an absolute value operation. These values are then passed to the corresponding register H (as shown in the figure). Stay in its corresponding register for a predetermined 59 pass: =:::: clock force period) 'Next each corresponding register _ is the absolute value of the block and the square function 4 to pass it to the corresponding register ϋ (eg The output of the REG.-:: mother register in the figure is represented as "value (ie, heart., and Q value (ie, ς nc - output multiplexer (10) χΓ, then provide these outputs to square) or square turn out MUX (as shown in SOMUX in the figure). _= square input _ select value, this choice is controlled by a controller (as shown

Talk about the period change and 7 or the coding rate. As described above, the operation of certain functional blocks of the DPC decoding functionality is based on the encoding rate and/or modulation of the symbols of the decoded LDpc encoded signals. To make appropriate selections in the squared output MUX by using the signals provided by the controller. The appropriate items are rounded out from the square round and are selected and added. For example, the term (Rx - I + I_Coef - 〇) 2, as shown in S (Ll〇〇ut, and Sq-Q〇 in the item 2 ' _), is added to the I associated with the output of the MUX. Shanshe--, the turn-off #日7F out of the I-axis distance, the component of the received signal corresponds to the group and coefficient of the appropriate cluster based on the appropriate chore/side, and is divided. Similarly, the output from the square

The Q-related output from the MUX 指示 indicates the Q-axis distance: Separate the received signal (4) component surface from the predetermined Q factor of the appropriate cluster point at the appropriate coding rate and / or lang. Adding and transferring money, the weight of the record is reduced before the calculation of the H-distribution metric of the red-point metric. The metric is 1326987 (4) (K) (10) The operation of the meta-metric calculator and the calculation of the bit metric calculator in the foregoing embodiment and the calculation of the bit metric calculator function block in the metric generator structure 1700 of the foregoing embodiment. Similarly, as described in other embodiments, the iterative decoding process performed when decoding the Cong-coded signal generally includes bit node processing and check node processing, which may alternatively be performed or continuously performed. The bit node processing includes updating and Calculating the edge message Medgeb associated with the bit node. After the initialization of the first iteration (in which the predetermined value is used), the edge message Medgec associated with the check node is updated to perform the bit node correlation Update and calculation of the edge message Medgeb. The check node processing includes updating and calculating the edge associated with the check node Med. • Using the most recently updated edge message related to the bit node (4) To perform the update and calculation of the edge message Medgec with the checksum. In the process of performing these calculations, the hardware implementation is usually performed in the logarithmic domain (where multiplication is commensurate into addition 'division is reduced to subtraction). The various embodiments of the bit node processing and check node processing will be described in detail below with reference to the accompanying drawings. Figure 19 is a schematic diagram of a bit node processing functional μ卯 according to an embodiment of the present invention. The edge message Medgec and the bit metric (shown in the figure • bit-metrics) are all input into the bit node processing functionality. The edge message Medgec associated with the checksum node is also provided to the accumulation. The device (shown as Acc in the figure) and the FIFO (first in, first out) function block. The bit metric is also provided to the accumulator, in which the bit metric is provided to the multiplexer (as shown in the MUX in the accumulator) In the processing of the bit node, the first received edge message related to the check node, such as Medgec (〇), is added to the bit 61 1326987. After that, the sum of the additions (for example, _ age (8) and The second received side message related to the check node, such as, and, in the clock cycle, the sum of the second sum, _, _^ = (1) and the sum of the bits μ) The third received is related to the check node =: (2) is added. Donna, the butterfly (four) saves one; = two registers (a) are located in the accumulator - one is accumulating) used to provide (10) and the value 'the sum The value includes all the riding information (4) and the expected position of 4 degrees (ie, 龄 (Med age) + biUletric). This value, Σ (fine (4) < metric - metric, can be regarded as a bit The node handles the soft output in the functional (4). After the absence, the soft output is provided to the most important bit wheel domain processor (as shown in the figure _ Qp, 曰 then the output of the FIFO is provided to the subtraction function block, and from _ The output (which is only the appropriate edge information suppression associated with the check node) is subtracted from the soft output (provided by the pure, provided). The output result of the subtraction function block is the updated edge > interest-object related to the bit (four) point. The updated edge message associated with the bit node includes the sum of all edge messages Medgec (except for the computed special side message) associated with the checkpoint and the bit metric. When the check node processing is performed during the subsequent iterative decoding process, the updated side message Medgeb associated with the bit 70 node is output by the symbol value format processor (as shown) in a symbol numerical format to facilitate the min forest. deal with. The most significant bit indicator in the output of the symbolic numeric format processor, the remaining bits indicating the actual value. • Edge messages associated with bit 70卽 are stored in memory in symbolic value format. The edge message Medgee associated with the check node is stored in a 2's complement format, with 62 1326987 facilitating bit node processing during subsequent iterative decoding processes. As described above, according to the present invention, the skill is handled. ^ species ~ vocabulary to test the node ® _ 21, head 22 峨 峨 ship calibration material processing functional diagram. ..., : In the check node processing functional plane shown in FIG. 20, when the side message detail related to the check node is updated by the charm Medgeb associated with the bit node, the ♦ forest processing and the mi management processing are used. . The recently updated edge-cancellation associated with the bit node is simultaneously supplied to the mir^ processing function block and the delete (first in first out) block. The subsequent edge message Medgeb associated with the bit node is provided to the min forest processing function block 'a registerer (shown as REG in the figure) and the feedback channels are operated to perform all the bits associated with the bit node. Side message Medgeb's min Lin processing. Then the final result of the min forest processing output from another register (shown as reg in the figure) is supplied to the min forest-processing function block, and the sorted edge message Medgeb associated with the bit node is also from ρ I The f〇 is provided to the Lumin Lin-processing function block. The output of the mi-processing function block is the updated side message Medge<: associated with the check node. In the check node processing function 21 shown in FIG. 21, the edge message Medgec related to the check node is updated by the edge message Medgeb associated with the bit node; when, the . And ηώ small processing. The recently updated edge message Medgeb associated with the bit node is provided to both the blood bamboo processing function block and the FIF〇 (first in first out) block. As the subsequent edge message Medgeb associated with the bit lang point is supplied to the minli processing function block, a register 5| (as shown in the REG) and a feedback channel are operated to perform all the bit nodes with 63 1326987 Off side message Medgeb's mintt processing. Then the final result of the mmtt processing output from another register (shown as REG in the figure) is supplied to the ringing processing function block, and the edge message Medgeb associated with the bit node after proper sorting is also from the FIF. Provided to the ringing · processing - function block. The output of the marriage-processing function block is the updated side message MedgGc associated with the check node. It should be noted that the functionality of the mintf function block can be thought of as performing a min* process with a minimum comparison process. An embodiment of performing magnetic tt processing will be described in detail below. It is also noted that only one rigid block is required for all predetermined numbers of processors per macroblock. That is, each of the above embodiments includes a plurality of macroblocks that support LDPC decoding functionality, and these embodiments may be implemented using check node processing functionality 2 or check node processing functionality, and each embodiment The towel only needs one FIFG. In some cases, all 20 processors in each macroblock of the decoding property need only one. The verification node processing function 22GG and the check section shipability described below are also the same. The check node processing functionality 22 shown in Figure 22 is one possible way to implement check node processing functionality 2000. From a higher perspective, the functionality of the check node processing functionality 22 is very similar to the check node processing functionality leak. In Fig. 22, more transition processing of the _* processing function block and the mi-processing function block is provided. The edge message Medgeb of the bit block reception and the bit node is as the input 'Medgeb' is also expressed as X. Processing function, the operation of the block involves calculating two individual odd-number correction factors, as shown in the figure MW_) and _ ln(l+e), and determining the minimum between two separate values (ie, X and 丫The minimum value of 64). Determining which value is the minimum of two (x or y) is performed by the multiplexer (•). For this, the 'min forest processing function block calculates two separate values, x_y and x+y. However, these values are then supplied to the block of the crane to calculate the corresponding Kasuga correction value. The output of the forest processing function block is the sum of the minimum value (Uy) and the two logarithmic correction factors. The y value is used as the output of the _forest function block and is fed back to the same _forest function block for subsequent calculations. The mm forest-processing function block is somewhat similar to the _forest processing function block. However, the #nun forest-processing function block computes the result of the min-block function block (its output is shown as illusion and _ provides the appropriate sorted edge message associated with the bit node_object (as indicated by X) The value z can be regarded as the result of all the edge messages associated with the bit node - ie, min**(all Medgeb). The mi-processing of the Wei block includes calculating two one-touch logarithmic correction factors, such as MUe-(iv)) and _ln(1+ew) in the figure, and determine the minimum between two separate values (ie, the minimum of Z*x). Determine which value is two (the minimum of z(four) is bound by the gong (the ancestor). For this purpose, the processing function block calculates the two sides of the ζ+χ's silk material. The positive logarithmic weight is .. 'Processing the Wei block from the mir^ and mint processing the Wei block. (4) The final result is • The updated edge message Medge related to the check node. Note that it can be L The query table is used to compare the logarithmic correction values of the Wei block and the processing of the miscellaneous money, which can be implemented using some other types of storage structures. To this end, it is necessary to implement two separate services in each of the _forest processing function blocks and the min forest-processing function. 65 1326987 The check node processing functionality shown in Figure 23 is a way to implement the check node processing power. In the figure, the use of bamboo processing and shouting processing updates the edge message associated with the check node by the edge associated with the bit (4) Medgeb. From a higher perspective, the check node processing functionality The function of the fiber is very similar to the check node processing functionality 2100. More details on the (10) processing function block and the coffee processing function block are provided in FIG. Within the processing function block, the received side message threats associated with the bit nodes are immediately subjected to the imperfect comparison and the ship's numerical values are made, making the minimum values of all inputs easier to find. This operation is performed in the value comparison function block (as shown in _ CQM). The minimum value (as indicated by _) and the maximum value (as indicated by max) of all edge messages Medgeb associated with the bit node. The value of all the edge messages Medgeb associated with the bit node 比较 is compared to the output in the function block and then passed to the Μ# processing function block in the processing function block. The final output of the processing block is the min* of the Medgeb associated with the bit node (as indicated by Ms_aii) and all the bit nodes associated with the minimum temporary value. The edge message Medgeb's m丨n* processing result (as shown in in). The 11111 small processing function block receives each m i η* processing result (Ms_a 11 and Ms jn i η). The mbt-where lib lib block also receives the absolute value of x, ie I χ I. In the coffee processing function block, the n processing function is the absolute value of the received X, ie, | χ | and the miatf·processing function, all the bit messages associated with the bit node ^6 (min* processing of ^05) The result (such as Ms-all does not) is calculated. The result of the min* processing function block in the _processing block is provided to the edge processing function block _ Μϋχ as an input, except for the minimum input value. The bit 7L is the point-related edge message _* processing result (such as π) one is provided as another input to the _. processing function block. The selection output table of the 为 is the t processing function block The two separate assignments are used to generate Υ and subsequent 从 from the X value. Υ fXifX^O l〇ifX< Ζ: 0 ί Y ifS^O l~YifS = l Final value _ S疋FIF0 MSB (Most Significant Bit). The rule based on the values γ and z above, the value S value can help to confirm the updated profile of the updated edge message related to the check node; Embodiments of the node processing process can be implemented in a communication device including a Cong decoding function that can be used to decode a pulse coded signal. The embodiment will describe several possible methods for performing the calculation of the check node processing. For some embodiments 4, these designs are slightly modified by the =. These minor modifications are for Consistent with the hardware, .Ζ: the calculations necessary for the type of processing. Several of the processes used for verification/reasoning have been introduced above. For example, different embodiments of _* processing can be easily used with it Different embodiments of Lit's similar '(10) processing can also be easily manipulated using the schematic 67 丄jzoy»/ 丄jzoy»/X and y of the min* processing functionality 2400 of the present embodiment. X The difference X and y between y and y is also supplied to the MUX. Which of X or y between X and y is the minimum value (ie, the min graph. The min* processing in the figure is determined for two inputs, ie, the value z (ie z=xy). The difference MSB of each input, ie z', is used to select the input (x, y). Similarly, the determined value of X and y, z, is also provided to the logarithm. The correction factor calculation function block calculates -ln(10), and the logarithmic correction value is expressed as (4). The final fine* processing result is the minimum of the towel Value and ride number correction value (ie, sum. Figure 25 is a schematic diagram of a _logarithm table according to one embodiment of the present invention. As described above, the 'LUT (query table) can be used to provide a reservation based on the speed of z ( Or pre-existing value. The table can provide a logarithmic correction factor rabbit _ (binary) based on the different values of _ difference_2, and can also provide the actual value of the item -in〇+e such as I) and the item Binary assignment (1 〇 t). It can be seen that the difference Z between the coffee makers is relatively larger than the _ _ (ie, the larger positron of the tree) or the threshold less than one characteristic (ie When the relatively large negative number is used, the value of ^ is saturated and set to coffee. The _* logarithmic table (4) binary position of the present implementation—the precision of the (10) value is 3 bits § However, other precisions can be used without departing from the scope of the invention and the fine, the table has a l〇g_〇 The gain region of ut, the value in this region changes as a function of Z. ,] Field 2 changed from approximately +1.25 to -1.25, the value of log_out actually changed by a function of 2. However, when Z is large, 25, (10) - Qut's shop. Similarly / When the value of z is less than -U5, the value of i〇g-(10) is also saturated. Due to this characteristic of the logarithmic correction value, it can be implemented more efficiently and faster. 68 1326987 • The rationale is used to verify the node processing. Similarly, each can be (or pre-computed) and stored in a LUT implemented using different types of memory to provide more computation and processing for communication setup using LDPC decoding functionality for check nodes Other calculations in the process also benefit from it. Figure 26 is a schematic diagram of processing functional leakage according to another embodiment of the present invention. The functionality of Figure 26 can also perform min* processing, but in a manner that is more versatile than the foregoing implementation. In some aspects this embodiment is similar to the embodiment described above. | However, the ® 26 towel uses two separate Jane _ number correction factor calculation blocks. The mi in the figure also operates on two inputs, X and y. The difference z between X and y is determined (i.e., z = x - y). Each input X and y is also provided to the leg. The value of 乂 is the sum of two other values, that is, the minimum value of χ or y in the previous iteration (such as min(x,^old) and the logarithmic correction factor (1〇g_〇utk4) in the previous iteration. And the difference between X and y, MSB 'ie z', is used to select which of the inputs χ or y is the minimum of this iteration (ie, min(x, y)k). Again, the determined X The difference between and y, z, is also provided to two separate logarithmic correction factor calculation function blocks, respectively - ln(Ue-|z|) and seven (1)e+|z|); these two separate logarithms The calculation result value of the correction factor calculation function block is supplied to the other side. χ ·, the difference MSB ′ between y, that is, Z, which one of the values output by the two separate logarithmic correction factors of the silk selection function block will be used as the actual logarithmic correction value of this iteration. The logarithmic correction value for this iteration of the final selection is expressed as log_outk. The result of the last secret treatment is considered to be the minimum of X or y (ie, rain(x, y)k) and the logarithmic correction value (ie, the sum of 69 1326987 one... but 疋, in the embodiment of A The two values are kept separate to facilitate the execution of the steps. If necessary, the two values can be selectively added together. Figure 27 is a schematic representation of the "-" processing functional recommendation in accordance with one embodiment of the present invention. The functionality in this figure is somewhat similar to the min* processing functionality. The nun wood-processing in the figure operates on two inputs, fork and y. The difference z between X and 乂 is determined (ie z =x_y) Each input X and 乂 are also supplied to the face. The difference between the X and y MSB 'ie z' is used to select which of the inputs X or y is the minimum value (ie, _ (x, y )) Similarly, the difference between the determined X and y, z, is also provided to the logarithmic correction factor. The calculation function calculates the rhyme!—euy|); the logarithmic correction is shown as i〇g—〇ut. The final mm*-processing result is the sum of the minimum value in X or y and the logarithmic correction value (i.e., iQg - ◦ this). 28 is a schematic illustration of a pair of numbers table in accordance with one embodiment of the present invention. As mentioned in the above table, the LUT (query table) can be used to quickly provide a predetermined (or pre-emptive) value based on the value of z. The table can provide the seam correction factor, log_〇ut (binary) based on the difference value of x*y, that is, the value of z, and can also provide the actual value of the item _ln(1_e-u_y|) and the item Binary assignment (lQg__Qut). It can be seen that when the difference 2 between the two is relatively greater than a specific threshold (ie, a relatively large positive ) word) or relatively less than a specific threshold (ie, a relatively large new number), then The value of 1〇g—(10) is saturating and is set to 00000. The precision of the binary 1 〇 g - (10) value in the min* logarithm table in this embodiment is 5 bits. Of course, other precisions of the lion can be used without departing from the scope and spirit of the present invention. There is a log-out gain region in the table, and the value in this region occurs as a function of z 1326987 ‘intersection. For example, when z changes from about +ι·5 to _ι·5, the value of i〇g_out actually changes as a function of z. However, when z is greater than +1.5, the value of i〇g_〇ut is saturated. Similarly, when the value of z is less than -1.5, the value of i0g_out is also saturated. Regarding the value of i〇g_out in min*-processing, when z=〇, the predetermined value of __〇 can be used (as indicated by binary 01000, and marked with an asterisk *). This is because an illegal value will be generated if the number 0 is taken from the number of threads (i.e., ln(Q)). @This, in this case, a predetermined larger value estimate will be used, as shown in the logarithm table. Due to this mismatch of logarithmic correction values, _*_processing can be implemented more efficiently and faster for verifying node processing. Similarly, various values can be predetermined (or pre-computed) and stored in LUTs implemented using different types of memory to provide faster calculations and processing in a communication device using [hundred decoding functionality] Other calculations in the processing of the node also benefit from it. 29 and 30 are diagrams showing the functionality of a min-ki processing according to an embodiment of the present invention. /Thinking The min*-processing functionality as shown in Figure 29 is similar to the _processing functionality_. The functionality shown in Fig. 29 can also perform the mi parameter processing, but adopts a faster manner than the foregoing embodiment. In some aspects, this embodiment is similar to the embodiment of the process described above. However, the present embodiment employs two separate and identical correction factor calculation function blocks. #, f The min kernel processing in this figure also operates on two inputs, χ and y. X and county value z are compared (ie m). Every loser and y are also provided. / is = the sum of two other values' ie the minimum value of x^y in the previous iteration (eg, Xian (1326987 not) and the logarithmic correction factor (lQg_Gutk_〇) in the previous iteration.\And 丫The difference between the MSB 'ie z' is used to select the input or the y towel which is the minimum value of the money generation - (ie, min(x, y)k). Similarly, the determined X and y The difference between them, z, is also provided to two separate logarithmic correction factor calculation function blocks to calculate an lnU_e Μ)"·#);

The calculation result value of the early logarithmic correction factor calculation function block is supplied to another. The difference MSB ′ between X and y, i.e., z ′, selects which of the values rotated by the two separate log correction factor calculation blocks will be used as the actual logarithmic correction value for this iteration. The logarithmic correction value of this iteration of the most spring, and k is expressed as log_outk. The last processed result is treated as the sum of the minimum value in 疋X or y (i.e., min(x, y)k) and the logarithmic correction value (i.e., g_〇Utk). However, in this embodiment, the two values remain separate to facilitate subsequent computational steps. The min kernel processing functionality shown in Figure 30 is similar to the min*_ processing functionality 29〇〇^ except that the values of X and y are received, such that y is the minimum value of X or y in the previous iteration (eg mnO^yVi) is a combination with the logarithmic correction factor (1〇g_〇utk i) of the previous iteration. That is, y is y=min(x,y)H+__. This form of 1 is accepted. The bit degree precision in the various embodiments described above can be adopted and selected by the designer. While the number of bits is shown in some embodiments, it is apparent that other numerical precisions may be employed without departing from the scope and spirit of the invention. 3A is a schematic diagram of the syndrome calculation functionality 3100 in accordance with one embodiment of the present invention. For various methods of performing LDPC decoding, the most recent estimate of the decoded bits is 72 1326987 (partial syndrome check functional , block) (eg, The PSC does not) 'determine the parity of the gamma bits. The most recent estimate of the decoded bit is passed to the (10) exception logic gate and then passed to the two sequential connections (such as REG). The output of the first register is fed back to the logic gate. Then, it is determined that the parity parity is passed to the subsequent function block, and the syndrome that is determined to be developed (i.e., all the parity output by the 'partial syndrome verification function block) is equal to zero. When all the syndromes are actually equal to zero, then the decoding bit is passed, and the LDPC decoding function _ sex enables the most recent estimate of the fourth estimate as the best estimate of the touch. Figure 32 is a flow diagram of a method of performing a Cong decoding method, in accordance with one embodiment of the present invention. In block 3220, the block is received! The j, Q value (for example, Rx/Ry) and the bit 7L of the block 1 is generated. The method allows parallel and simultaneous processing of the received Bu Q value of the first block while performing the bit metric calculation of the first block. Then, in block 3230, block 2 is received! , Q value (eg, Rx/Ry), and generate a bit metric for block 2. Further, as shown in block 323(), the method includes the iterative decoding block 1 at the same time. At this time, the reception and metric calculation of one block (e.g., block 2) can be processed in parallel and simultaneously while iteratively decoding the pre-decoding block (e.g., block 1). Then, in block_, the method includes receiving the 量, Q value (e.g., 'Rx/Ry)' of the block 3 sub-generating block 3 metric. Furthermore, as shown in the box diagram, the method includes iterative decoding block 2 at the same time. As with the operation shown in the block order, Newton decodes the pre-receive block (e.g., block 2) simultaneously and simultaneously processes the reception and metric calculations of one block (e.g., block 3). 73 1326987 FIG. 33 is a flow diagram of an iterative coffee decoding method according to an embodiment of the present invention: in block 3310, the method includes using a side message associated with the check node to saturate the bit 4 point processing, Initialize 'set to a predetermined value. The side message Med age associated with the check node may be set to a threshold value in some embodiments. /Next' performs an iterative decoding processing operation. In iteration #1 3320, the method performs check node processing and syndrome calculations, as shown in the box. In the dumping, the method also performs bit node processing, as shown in block 3324. In iteration #2 3330, the method performs check node processing and syndrome calculation as shown in block 3332. In iteration #2, the method also performs a bit sample: as shown in block 3334. The present invention can perform the decoding iteration of each of the parameters, and the scope and spirit of the county. This is indicated by an ellipsis in Fig. 33 (i.e., ...). At the last load, the checksum processing and syndrome calculations are as shown in block 3342. In the final iteration, if the syndrome passes (or reaches the maximum of the decoding iteration), the method ranks the meta-section to output the solution' as shown in block 3344. It should be noted that the method described by the Society can also be implemented in various suitable (four) systems and/or device designs (communication systems, systems, communication transmitters, communication receivers, communication transceivers and/or functionalities therein). Without departing from the scope and spirit of the invention. In addition, it should be noted that the various functional, system and/or device designs and methods described in the various embodiments of the above embodiments can perform calculations in various logarithmic domains (eg, 1 〇, domain) so that additions can be used. A multiplication operation is performed, and a division operation is performed using subtraction. It is apparent that other modifications and changes can be made to the present invention without departing from the spirit and scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram of a communication system according to an embodiment of the present invention; FIG. 2 is a schematic diagram of a communication system according to another embodiment of the present invention; FIG. 3 is a hunger according to an embodiment of the present invention. ^ Schematic diagram of a coded bipartite graph; FIG. 4 is a schematic illustration of an LDpc decoding operation using bit metrics in accordance with one embodiment of the present invention, and FIG. 5 is a use of bit bits in accordance with another embodiment of the present invention (when 11 iterations are performed) Schematic diagram of LDPC decoding operation of the measurement; Figure 6 is a schematic diagram of LDPC decoding according to an embodiment of the present invention; - Figure 7 is a schematic diagram of LDPC decoding according to an embodiment of the present invention; Figure 8 is a schematic diagram of LDPC decoding according to an embodiment of the present invention; FIG. 9 is a schematic diagram of LDPC decoding according to an embodiment of the present invention; FIG. 10 is a schematic diagram of a metric generator according to an embodiment of the present invention; FIG. 11 is a gpSK display according to the present invention. And a schematic diagram of the QPSK coefficients used therein and the QPSK coefficients employed therein; the binary mapping of FIG. and FIG. 12 is an 8 PSK cluster and its pair according to an embodiment of the present invention. Schematic diagram of the 8 PSK coefficients used therein; the hexadecimal map 13 is a schematic diagram of a 16 QAM cluster and its 16 QAM coefficients for use in and according to an embodiment of the present invention; FIG. 15 is a schematic diagram of a modulation coefficient table according to an embodiment of the present invention; FIG. 15 is a schematic diagram of a 16APSK cluster of an embodiment and its corresponding ten 丄, /, carry bitmap 75 1326987 shot; 16 is a schematic structural diagram of a metric generator according to an embodiment of the present invention; FIG. 18 is a schematic structural diagram of a metric generator according to an embodiment of the present invention; 19 is a schematic diagram of bit node processing according to an embodiment of the present invention; FIG. 20 is a schematic diagram of check node processing according to an embodiment of the present invention;

21 is a schematic diagram of a check node process according to an embodiment of the present invention; FIG. 22 is a schematic diagram of check node processing according to an embodiment of the present invention; FIG. 23 is a schematic diagram of check node processing according to an embodiment of the present invention. Figure 24 is a schematic illustration of a min* process in accordance with one embodiment of the present invention; Figure 25 is a schematic illustration of a min* logarithm table in accordance with one embodiment of the present invention; Figure 26 is a schematic illustration of a min* process in accordance with another embodiment of the present invention; Figure 27 is a schematic illustration of min*_ processing in accordance with one embodiment of the present invention;

28 is a schematic diagram of a min*-logarithm table according to an embodiment of the present invention. FIG. 29 is a schematic diagram of min*-processing according to another embodiment of the present invention. FIG. 30 is a min*- according to still another embodiment of the present invention. Figure 31 is a flowchart of a syndrome calculation function block according to an embodiment of the present invention. Figure 32 is a flowchart of a LDPC decoding method according to an embodiment of the present invention. 33 is a flow of an iterative LDPC decoding method according to an embodiment of the present invention. [Main component symbol description] Communication system 100 Communication device 110 76 1326987 Transmitter 112 Encoder 114: Receiver 116 Decoder 118 Fee-communication channel 199 Communication device 120 Receiver 122 Decoder 124 Transmitter 126 Encoder 128 Satellite Communication Channel 130 Satellite TV Antenna 132Ί34 Wireless Communication Channel 140 Tower 142, 144 ϋ Wired Communication Channel 150 Local Antenna 152Ί54 Optical Fiber Communication Channel 160 Electro-Optical Interface 162 Optical-Electrical Interface 164 Communication System 200 'Information Bit 201 Coded Signal Bit 202 ' Discrete Value Modulation Symbol Sequence 203 Continuous Time Transmit Signal 204 Filtered Continuous Time Transmit Signal 205 Continuous Time Receive Signal 206 Filtered Continuous Time Receive Signal 207 Discrete Time Reception Signal 208 • Symbol metric 209 Best estimate 210 Encoder and symbol mapper Symbol mapper 220 Encoder 222 224 Transmit driver 230 - digital analog converter, analog front end 232 Transmit filter 234 260 Receive filter 262 Analog to digital converter solution 264 Measurer 270 Communication Channel 280 Transmitter 297 299 Variable Node 310 77 1326987 Bit Node 312 Check Node 322 I, Q Value 401 Symbol Measure 411 Bit Measure 421 Bit Node Bit Node Processor 430 Soft Output 435 Side Message 441 Iterative Decoding Process 450 Corrector Calculator 470 Bit Measure 500 Ping Pong Storage Structure 605 Bit/Check Processor 610 Barrel Shifter 615 Controller 650 Control Signal 652 Barrel Shifter 662 Macroblock 699 Measure Generator 803 bit/check processor 810 controller 850 control signal 852

Check node 320 edge 330 metric generator 410 symbol node calculator function block 420 bit metric bit metric calculator 422 side message 431 check node processor 440 function block 442 hard limiter 460 bit estimate 471 metric generation 603 Measure Memory 606, 607 Bit/Check Processor 611---612 Memory 620 LDPC Code 651 SRAM 660 Calibrator Computation Function Block 664 Virtual Binary Metric Memory 705 Metric Memory 806 807 Barrel Shift Element 815 LDPC Code 851 Barrel Shift Element 862 78 1326987 Macro Block 899 Measure Generator 903 Bit/Check Processor 911, 912 Controller 950 Control Signal 952 Macro Block 999 Measure Generator Structure 1600 Bit/Check Processor 811, 812 Bit/Check Processor 910 Bucket Shift Element 915 LDPC Code 951 SARM 960 Measure Generator Structure 1700 Measure Generator Structure 1800 79

Claims (1)

1326987 + 'Application Patent Range: The decoder includes: 1 decoder for decoding an LDPC coded signal, and a measure generator for: generating a first group of first to receive a corresponding symbol of the LDPC coded signal - 丨, q a value, a plurality of bit metrics, and a second plurality of metrics for receiving a second set of symbols corresponding to the second symbol of the LDPC coded signal; the metric memory for: storing the first set of singular elements Measuring and relying on the second singularity metric; the slab sputum = body management' to output the first plurality of bits in a domain sized from the stitching of the second plurality of bits 7G Measure; support double-clicking bell management, so that Sister New produces the second set of bit metrics while 彳H魄s 70 bits; multiple bits/checking processors for: continuous Receiving the first set of complex dollar metrics, the second set of complex female metrics, and the third set of plural metrics; 'the TLff point processing, including updating and plural ___ Multiple side messages 'and check nodes The method includes: updating a plurality of side messages related to the plurality of check nodes; and message transfer memory, configured to: store the plurality of check nodes after processing by the bit nodes in the plurality of bit/check processors a plurality of edge messages related to the bit node; 1326987, after processing by the check node in the plurality of bit edge check processors, storing a plurality of side messages related to the check nodes; And the related complex pair is read from the message transfer memory, and the plurality of bit node side messages are shifted; and the fine _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The bit/verification process is performed by the subsequent check node processing; the plural number of the recorded and the plural check is provided for the plural number from the side of the message The bit node processing of _ is performed on the plurality of bit it/check processing n. 2. The decoder of claim 1, wherein the method further comprises: outputting a processing benefit from the plurality of side messages corresponding to the most recently updated plurality of side messages associated with the plurality of bit nodes The meta/checksum_records the output and then makes a hard decision to generate a bit-optimal estimate of at least one of the first symbol and the second symbol of the _coded signal. 3. The decoder as claimed in claim i, wherein the step comprises: - a syndrome # function block, the secret corresponding to a plurality of side messages associated with the most recently updated plurality of bit nodes The plurality of bit/check processors receive the soft output and determine whether each of the plurality of syndromes used to generate the LDPC encoded signal is equal to zero. 4. The decoder of claim 1, wherein: 81 1326987 the metric memory, the plurality of bit/check processors, and the message transfer memory form a plurality of macroblocks The first macroblock; 'each of the plurality of macroblocks further includes a corresponding metric memory, a pair of corresponding bits/check processors, and corresponding messages Transmitting a memory; the bucket shifter and the message corresponding to each of the macroblocks of the plurality of macroblocks transmit a § memory communication connection. 5. A decoder for decoding an LDPC coded signal, the decoder comprising: a plurality of bit/check processors for: receiving a plurality of bit metrics; < performing bit node processing 'including updating and Wei a plurality of side messages of the bit __ and check node processing, including updating a plurality of side messages associated with the plurality of check nodes; message transfer memory for: at the plurality of bits/checks After processing the correction through the bit node processing, storing the plurality of side messages related to the plurality of bit positions; in the complex _侃/纽 processing, such as Lang _ shouting _, storing and resuming a plurality of side messages Checking the number of edges associated with the node; the barrel shifter is used to: shift the read-by-segment and the plurality of bit nodes from the ship to the ship; • providing the shifted plurality of side messages associated with the plurality of bit nodes to the plurality of bit/check processing H for subsequent check node processing; 82 1326987 for transferring memory from the message a plurality of the details of the body (4) and the plurality of test nodes The side message is shifted; the shifted plurality of side messages associated with the plurality of check nodes are provided to the plurality of bit/check processors for subsequent bit node processing. 6. The decoder of claim 5, further comprising: the metric generator' receiving the jQ value of the plurality of symbols corresponding to the LDPC coded signal and generating a plurality of bit metrics therefrom. 7. The decoder of claim 5, wherein the method further comprises: an output processor for using the plurality of side messages corresponding to the most recently updated plurality of bit nodes associated with the plurality of bit nodes The bit/checksum wipe receives the soft output and then makes a hard decision to generate a bit best estimate of at least one of the first symbol and the second symbol of the LDPC coded signal. 8 methods for decoding an LDPC coded signal, comprising: receiving a first 丨, a Q value corresponding to a first symbol of an LDPC coded signal, and generating a first plurality of bit metrics therefrom; and a threshold value, and generating a second group therefrom - a plurality of bit metrics; a plurality of bit metrics corresponding to the second symbol of the LDPC coded signal while receiving the plurality of bit metrics; storing the first plurality of bit metrics and the first support Double-receiving the memory, so as to receive the first output of the first group of multiple bit metrics; support the five-fold memory management, so that after receiving the first-known V-professional two groups Simultaneously outputting the second set of plurality of bit metrics; 83 326987 continuously receiving the first set of plural bit metrics, the second set of reduced bit metrics, and the third set of complex numbers a bit metric; performing a bit node process, updating a plurality of side messages associated with a plurality of bit nodes, and awaiting node processing, including updating a plurality of side messages associated with the plurality of check nodes; point After the processing, storing the plurality of bit sections __ a plurality of side messages; and, after the second pass (4) processing, the stalking _ _ _ phase _ a plurality of side messages; a plurality of side message shifting configurations for subsequent check node processing; shifting the plurality of side messages associated with the plurality of check nodes to a suitable configuration for subsequent bit nodes deal with. 9. The method of claim 8, further comprising: receiving a soft output corresponding to the most recently updated and a plurality of side messages, and then making a hard decision, thereby generating a code. A bit best estimate of at least one of the first symbol and the second symbol of the signal. 1. The method of claim 8, wherein the method further comprises: a soft round of a plurality of side messages associated with the plurality of bit nodes that have been recently updated; determining to generate an LDPG code Each θ of the calibrated sub-blade of the LDPG code is equal to zero.疋 84