CN101364809B

CN101364809B - Decoder

Info

Publication number: CN101364809B
Application number: CN2008101461654A
Authority: CN
Inventors: 安德鲁·布兰克斯拜; 阿尔文·莱·林
Original assignee: Zyray Wireless Inc
Current assignee: Broadcom Corp; Zyray Wireless Inc
Priority date: 2007-08-06
Filing date: 2008-08-06
Publication date: 2011-09-07
Anticipated expiration: 2028-08-06
Also published as: KR100992048B1; KR20090014998A; CN101364809A; TW200926615A; HK1129781A1; TWI407703B

Abstract

Multi-code LDPC (Low Density Parity Check) decoder. Multiple LDPC coded signals can be decoded using hardware provisioned for a minimum requirement needed to decode each of the multiple LDPC coded signals. In embodiments where each LDPC matrix (e.g., employed to decode each LDPC coded signal) includes a common number of non-null sub-matrices. In embodiments where each LDPC code includes a different number of non-null sub-matrices within its respective LDPC matrix, then a different number of memories are employed when decoding each LDPC coded signal. Various degrees of parallelism in decoding can also be employed in which different numbers of bit engines and check engines can be employed when decoding different LDPC coded signals.

Description

Decoder

Technical field

The present invention relates to communication system, more particularly, relate to the decoding technique of low-density checksum in the communication system (LowDensity Parity Check is called for short LDPC) code signal.

Background technology

Data communication system sustainable development for many years, in recent years, adopting the communication system of iteration error correcting code is the focus that researchers pay close attention to.Wherein of greatest concern is the communication system that adopts the LDPC sign indicating number.Under same state of signal-to-noise, use the error rate of the communication system of iterative code to be usually less than the communication system of using other coding.

One of this field continues and main developing direction is that signal to noise ratio in reducing communication system is to reach the specific error rate.Desirable target is the mountain farming limit (Shannon ' slimit) of attempting in the research communication channel, and mountain farming limit can be regarded as and is used in the data transmission rate of using in the channel with specific signal to noise ratio, can realize not having the error code transmission by this channel.In other words, farming limit in mountain is the theoretical limit at given modulation and encoding rate situation lower channel capacity.

The extraordinary decoding performance that can provide in some cases near mountain farming limit has been provided the LDPC sign indicating number.In theory, some LDPC decoder is proved the performance that can reach from 0.3 decibel of mountain farming limit.Length is that 1,000,000 abnormal LDPC code once reached this performance, and it has confirmed that it is very likely using the LDPC sign indicating number in communication system.

The use of ldpc coded signal continues to be applied to many new fields.Can adopt the example of several possible communication system of ldpc coded signal to comprise to be used for the communication system (for example in comprising IEEE 802.11 environment spaces of the emerging standard of IEEE 802.11n) of operation in the communication system (for example according to IEEE 802.3an 10Gbps (gigabit/sec) ethernet operation (10GBASE-T)) of 4 pairs of twisted-pair cables of employing that Fast Ethernet uses and the wireless environment.

For these special communication system applications fields, expect to have very much the error correcting code that can realize near capacity.Potential restriction (latency constraints) because of using traditional concatenated code to introduce has hindered their use in the high data rate communication systems application.

In general, in the communication system environment that adopts the LDPC sign indicating number, first communication equipment with encoder capabilities is arranged, the second communication equipment with decoder capabilities is arranged at the other end of communication channel at an end of communication channel.In most cases, these two communication equipment one or both have encoder ability (for example in intercommunication system).The LDPC sign indicating number can also be applied in various other application, (for example comprise those storage that adopt certain form, hard disk drive HDD uses and other memory device) application, wherein data were encoded before writing storage medium, and data are decoded after reading from this data medium/taking out then.

In many such existing communication equipment, the difficulty of an effective equipment of design adapted for decoding LDPC code signal and/or a maximum of communication equipment is storage and management (when for example, storing and transmitting verification limit message and bit limit message back and forth between verification engine and bit-engine) is updated and uses in the iterative decoding process all bit limit message (bit edge message) and required large tracts of land and the memory of verification limit message (check edge message).When handling relatively large piece size in LDPC sign indicating number environment, handling required memory requirement of these verification limit message and bit limit message and storage management will be difficult to handle very much.Thereby the present technique field needs and come adapted for decoding LDPC code signal to extract coding information within it with continuing to need a kind of better means.

In addition, when the size of the low-density parity check (LDPC) matrix H that is used for adapted for decoding LDPC code signal reached predetermined certain size, the interconnectivity between first processing module and second processing module (for example, verification engine and bit-engine) will significantly increase.

Summary of the invention

Equipment that the present invention relates to and method have further description in following description of drawings, embodiment and claim.

According to an aspect of the present invention, provide a kind of decoder, be used for decoding LDPC (low-density checksum) code signal, described decoder comprises:

A plurality of memories;

A plurality of bit-engine, and each bit-engine in described a plurality of bit-engine all is used for being connected at least one memory of described a plurality of memories;

A plurality of verification engines, each the verification engine in described a plurality of verification engines all is used for being connected at least one memory of described a plurality of memories; And

A plurality of multiplexers (MUX) are used for:

In the decoding process of first ldpc coded signal, optionally with described a plurality of bits

Engine and described a plurality of verification engine are connected to first word-select memory in described a plurality of memory;

And

In the decoding process of second ldpc coded signal, optionally with described a plurality of bits

Engine and described a plurality of verification engine are connected to second word-select memory in described a plurality of memory; And wherein:

Described a plurality of memory comprises the memory of predetermined quantity, and the memory of described predetermined quantity is used for representing a plurality of non-zero submatrices of a plurality of LDPC matrixes of corresponding a plurality of LDPC codings;

Described decoder described first ldpc coded signal that is used to decode, described first ldpc coded signal be corresponding to a LDPC matrix of described a plurality of LDPC matrixes, thereby be created on the best estimate of the bit that is encoded in first ldpc coded signal; And

Described decoder described second ldpc coded signal that is used to decode, described second ldpc coded signal be corresponding to the 2nd LDPC matrix of described a plurality of LDPC matrixes, thereby be created on the best estimate of the bit that is encoded in second ldpc coded signal.

Preferably, by a plurality of non-zero submatrices in a plurality of LDPC matrixes of the corresponding a plurality of LDPC codings that superpose each other, determine a part of memory in described a plurality of memory.

Preferably, by the stack of a plurality of non-zero submatrices in a plurality of LDPC matrixes of a plurality of LDPC codings of correspondence being carried out first greed (greedy), the degree of depth (depth) search, determine a part of memory in described a plurality of memory.

Preferably, by first greed, deep search are carried out in the stack of a plurality of non-zero submatrices in a plurality of LDPC matrixes of a plurality of LDPC codings of correspondence, determine a part of memory in described a plurality of memory;

And

Described first greed, deep search to small part is considered row affine tolerance (column affinitymatric), and the affine tolerance of described row is represented the row in the described LDPC matrix and the connectedness (connectedness) of another row at least in the described LDPC matrix and the row in described the 2nd LDPC matrix.

Preferably, the layout of a plurality of memories in the described communication equipment is based on merging patterns (mergepattern), by considering that to small part the affine tolerance of row generates described merging patterns, the affine tolerance of described row is represented the row in the described LDPC matrix and the connectedness of another row at least in the described LDPC matrix and the row in described the 2nd LDPC matrix.

Preferably, described a plurality of memories comprise a plurality of merging memories, first non-zero submatrices in the corresponding described LDPC matrix of a merging memory in described a plurality of merging memories, second non-zero submatrices in also corresponding described the 2nd LDPC matrix.

Preferably, a described LDPC matrix of described a plurality of LDPC matrixes comprises more than first non-zero submatrices;

Described the 2nd LDPC matrix of described a plurality of LDPC matrixes comprises more than second non-zero submatrices;

And

In the decode procedure of described first ldpc coded signal, when handling first non-zero submatrices of described more than first non-zero submatrices, use a memory in described a plurality of memory; In the decode procedure of described second ldpc coded signal, when handling first non-zero submatrices of described more than second non-zero submatrices, also use the described memory in described a plurality of memory.

Preferably, a described LDPC matrix of described a plurality of LDPC matrixes comprises the subclass of described a plurality of non-zero submatrices; And

Described the 2nd LDPC matrix of described a plurality of LDPC matrixes comprises the described subclass of described a plurality of non-zero submatrices and the non-zero submatrices that at least one is additional.

Preferably, in the decode procedure of described first ldpc coded signal, when using first non-zero submatrices of a described LDPC matrix, and in the decode procedure of described second ldpc coded signal, when using second non-zero submatrices of described the 2nd LDPC matrix, use a memory in described a plurality of memory; And

The position of the row and column of second non-zero submatrices in the position of the row and column of first non-zero submatrices in the described LDPC matrix and described the 2nd LDPC matrix is identical.

Preferably, when described first ldpc coded signal of decoding, when using first non-zero submatrices in the described LDPC matrix, and when second non-zero submatrices in described second ldpc coded signal of decoding, described the 2nd LDPC matrix of use, use a memory in described a plurality of memory;

Described first non-zero submatrices comprises first row and first row that are arranged in a described LDPC matrix;

And

Described second non-zero submatrices comprises second row and the secondary series that is arranged in described the 2nd LDPC matrix.

Preferably, in the processing procedure of bit node, a multiplexer in a plurality of multiplexers is connected to a memory in described a plurality of memory with a bit-engine of described a plurality of bit-engine; And

In the processing procedure of check-node, the described multiplexer in a plurality of multiplexers is connected to a described memory in described a plurality of memory with a verification engine of described a plurality of verification engines.

Preferably, described decoder is implemented in integrated circuit.

Preferably, described decoder is implemented in communication equipment, and described communication equipment is used for receiving described first ldpc coded signal or described second ldpc coded signal from communication channel; And

Implement in the following at least one of described communication equipment: satellite communication system, wireless communication system, wired communication system and optical fiber telecommunications system.

A plurality of memories;

A plurality of bit-engine, and each bit-engine in described a plurality of bit-engine all is connected at least one memory in described a plurality of memory;

A plurality of verification engines, each the verification engine in described a plurality of verification engines all is connected at least one memory in described a plurality of memory; And

A plurality of multiplexers (MUX) are used for:

When decoding during first ldpc coded signal, in the process that bit node is handled, the selected bit-engine of first in described a plurality of bit-engine is connected to first word-select memory in described a plurality of memory;

When described first ldpc coded signal of decoding, in the process of code check node processing, with institute

State the selected verification engine of first in a plurality of verification engines and be connected to described first word-select memory in described a plurality of memory;

When decoding during second ldpc coded signal, in the process that bit node is handled, the selected bit-engine of second in described a plurality of bit-engine is connected to second word-select memory in described a plurality of memory; And

When described second ldpc coded signal of decoding, in the process of code check node processing, the selected verification engine of second in described a plurality of verification engines is connected to described second word-select memory in described a plurality of memory; Wherein:

Preferably, described first of the described a plurality of bit-engine selected bit-engine is the described second selected bit-engine of described a plurality of bit-engine; And

The described first selected verification engine of described a plurality of verification engines is described second selected verification engines of described a plurality of verification engines.

Preferably, described first of the described a plurality of bit-engine selected bit-engine is all bit-engine of described a plurality of bit-engine; And

The described first selected verification engine of described a plurality of verification engines is all verification engines of described a plurality of verification engines.

Preferably, in the decode procedure of described first ldpc coded signal, described first ldpc coded signal disconnects from all bit-engine of described a plurality of bit-engine and all verification engines of described verification engine.

Preferably, in the decode procedure of described first ldpc coded signal, a multiplexer in described a plurality of multiplexers is used for a memory of described a plurality of memories is connected at least one bit-engine;

In the decode procedure of described first ldpc coded signal, the described multiplexer in described a plurality of multiplexers is used for the described memory of described a plurality of multiplexers is connected at least one verification engine; And

In the decode procedure of described second ldpc coded signal, the described multiplexer in described a plurality of multiplexers is used for the described memory of described a plurality of memories is disconnected from all bit-engine of described a plurality of bit-engine and all verification engines of described verification engine.

Preferably, by the described a plurality of non-zero submatrices in a plurality of LDPC matrixes of the described a plurality of LDPC codings of stack correspondence each other, determine a part of memory in described a plurality of memory.

Preferably, by first greed, deep search are carried out in the stack of the described a plurality of non-zero submatrices in a plurality of LDPC matrixes of the described a plurality of LDPC codings of correspondence, determine a part of memory in described a plurality of memory.

Preferably, by first greed, deep search are carried out in the stack of the described a plurality of non-zero submatrices in a plurality of LDPC matrixes of the described a plurality of LDPC codings of correspondence, determine a part of memory in described a plurality of memory; And

Described first greed, deep search to small part is considered the affine tolerance of row, and the affine tolerance of described row is represented the row in the described LDPC matrix and the connectedness of another row at least in the described LDPC matrix and the row in described the 2nd LDPC matrix.

Preferably, the layout of the described a plurality of memories in the described communication equipment is based on merging patterns, by considering that to small part the affine tolerance of row generates described merging patterns, the affine tolerance of described row is represented the row in the described LDPC matrix and the connectedness of another row at least in the described LDPC matrix and the row in described the 2nd LDPC matrix.

And

Preferably, described decoder is implemented in integrated circuit.

A plurality of memories;

A plurality of multiplexers (MUX) are used for:

When decoding during first ldpc coded signal, in the process that bit node is handled, described a plurality of bit-engine are connected to first word-select memory in described a plurality of memory;

When described first ldpc coded signal of decoding, in the process of code check node processing, described a plurality of verification engines are connected to described first word-select memory in described a plurality of memory;

When decoding during second ldpc coded signal, in the process that bit node is handled, described a plurality of bit-engine are connected to second word-select memory in described a plurality of memory;

When described second ldpc coded signal of decoding, in the process of code check node processing, described a plurality of verification engines are connected to described second word-select memory in described a plurality of memory;

When decoding during the 3rd ldpc coded signal, in the process that bit node is handled, described a plurality of bit-engine are connected to the 3rd word-select memory in described a plurality of memory; And

When described the 3rd ldpc coded signal of decoding, in the process of code check node processing, described a plurality of verification engines are connected to described the 3rd word-select memory in described a plurality of memory; Wherein:

Described decoder described first ldpc coded signal that is used to decode, described first ldpc coded signal be corresponding to a LDPC matrix of described a plurality of LDPC matrixes, thereby be created on the best estimate of the bit that is encoded in first ldpc coded signal;

Described decoder described second ldpc coded signal that is used to decode, described second ldpc coded signal be corresponding to the 2nd LDPC matrix of described a plurality of LDPC matrixes, thereby be created on the best estimate of the bit that is encoded in second ldpc coded signal; And

Described decoder described the 3rd ldpc coded signal that is used to decode, described the 3rd ldpc coded signal be corresponding to the 3rd LDPC matrix of described a plurality of LDPC matrixes, thereby be created on the best estimate of the bit that is encoded in the 3rd ldpc coded signal.

Described first greed, deep search to small part are considered the affine tolerance of row, and the affine tolerance of described row is represented row and the row in another row, described the 2nd LDPC matrix at least in the described LDPC matrix and the connectedness of the row in described the 3rd LDPC matrix in the described LDPC matrix.

Preferably, the layout of the described a plurality of memories in the described communication equipment is based on merging patterns, by considering that to small part the affine tolerance of row generates described merging patterns, the affine tolerance of described row is represented row and the row in another row, described the 2nd LDPC matrix at least in the described LDPC matrix and the connectedness of the row in described the 3rd LDPC matrix in the described LDPC matrix.

Preferably, described a plurality of memory comprises a plurality of merging memories, first non-zero submatrices in the corresponding described LDPC matrix of a merging memory in described a plurality of merging memory, second non-zero submatrices in also corresponding described the 2nd LDPC matrix, the 3rd non-zero submatrices in also corresponding described the 3rd LDPC matrix.

Described the 2nd LDPC matrix of described a plurality of LDPC matrixes comprises the subclass of described a plurality of non-zero submatrices and the non-zero submatrices that at least one is additional.

And

Preferably, described decoder is implemented in integrated circuit.

Various advantage of the present invention, various aspects and character of innovation, and the details of the embodiment of example shown in it will describe in detail in following description and accompanying drawing.

Description of drawings

The invention will be further described below in conjunction with drawings and Examples, in the accompanying drawing:

Fig. 1 and Fig. 2 show the different embodiment of communication system;

Fig. 3 shows the embodiment of the equipment that is used to carry out the LDPC decoding processing;

Fig. 4 shows the selectivity embodiment of the equipment that is used to carry out the LDPC decoding processing;

Fig. 5 shows the embodiment of LDPC coding bipartite graph;

Fig. 6 shows the embodiment of LDPC decoding function;

Fig. 7 shows the embodiment of the non-zero submatrices stack of a plurality of LDPC matrixes;

Fig. 8 shows provides memory, to adapt to embodiment to the processing of the non-zero submatrices of the LDPC matrix that superposes among Fig. 7;

Fig. 9 A and Fig. 9 B show the embodiment of decoding framework, are used for adapting to the processing of the non-zero submatrices of the LDPC matrix that Fig. 7 is superposeed;

Figure 10 shows the embodiment of decoding framework, is used for adapting to the processing of the non-zero submatrices of the LDPC matrix that Fig. 7 is superposeed;

Figure 11 shows the embodiment of decoding framework, is used to adapt to the processing to the non-zero submatrices of the LDPC matrix of stack;

Figure 12 shows the selectivity embodiment of decoding framework, is used to adapt to the processing to the non-zero submatrices of the LDPC matrix of stack;

Figure 13 and Figure 14 show the embodiment that hardware is provided for the non-zero submatrices of decoding stack LDPC matrix;

Figure 15 shows the embodiment of 2 connections between the separate memory, and described memory is used for the code check node processing of LDPC decoding process;

Figure 16 shows the internuncial embodiment that merges memory, and described merging memory is used for the code check node processing of LDPC decoding process;

Figure 17 shows the embodiment of the method for handling ldpc coded signal;

Figure 18 shows the embodiment of the method for handling ldpc coded signal;

Figure 19 shows to handling various ldpc coded signals the embodiment of the method for hardware is provided;

Figure 20 shows the selectivity embodiment of stack LDPC matrix.

Embodiment

LDPC (low-density checksum) sign indicating number is that capacity approaches forward error correction (ECC), is just adopted by mass communication standard (for example IEEE 802.3an, IEEE 802.11n, 802.20, DVB-S2).Relevant application comprises magnetic recording, wireless, the high speed data transfer by copper cable and optical fiber.

Among the embodiment, use the iterative decoding method to carry out the LDPC decoding processing, wherein, when carrying out code check node processing (being also referred to as the check engine sometimes handles) and bit node processing (being also referred to as bit-engine sometimes handles), return in the future and pass message (for example, verification limit message and bit limit message (have is to be also referred to as variable edge message)).Some the time, this is called as message-passing decoding handles, (for example, the LDPC bipartite graph is also referred to as " Tanner " figure in the industry sometimes) operation on the graphic of coding.

Use in the communications applications of ldpc coded signal at majority, multiple coding is supported in essential and/or expectation.Here comprise various reasons.On the one hand, various coding can be used for different noise circumstances and/or data characteristic.For example, when the operating environment of communication system changes (for example SNR changes), the specific coding of then using is the possibility adaptively modifying also, with the variation that conforms, keeps a kind of acceptable performance level (high-throughput accepted under for example acceptable low error rate).On the other hand, transceiver can be designed to be able to support the multi-protocols transceiver of the multiple coded system of different communication protocol.Many application also use LDPC coding to operate, and this LDPC coding corresponding LDPC matrix is based on submatrix, and some of them LDPC matrix uses the submatrix of order modification.

For example, IEEE 802.11n standard code 12 kinds of different LDPC codings, these LDPC codings are based on the submatrix structure.Equally, IEEE 802.16a standard code 24 kinds of different LDPC codings, they are also based on the submatrix structure.Aspects more of the present invention can be used in these and use in the example.

The submatrix structure of the LDPC code families that method use decoder provided by the invention is supported is to reduce the effective means of the enforcement complexity of decoder.Generally speaking, decoder only need be supported a kind of encoding scheme (for example when the specific coding signal of specific LDPC coding generation is used in decoding) in the LDPC code families at any time, and decoder constructs of the present invention makes memory device and computing unit efficiently to share.Thereby this can reduce decoder reduces decoder to the demand of memory space and computing unit volume to a great extent.

In addition, the present invention also provides the method for using multiple correlation technique all PDPC coding superimposed (super-position) (must be supported by application-specific) from the LDPC code families to obtain " merging " decoder constructs.This folding is used zero submatrix in the individual encoded structure, and in the graphic of LDPC coding based on measures of closeness (metrics based on proximity).

It should be noted that, method provided by the invention also may be used in other LDPC decoding structure, comprise aforesaid U.S. Provisional Patent Application 60/958,014 and the novel patent application 11/828 of U.S. utility, 532, its title is in the LDPC decoding structure of " Distributed processing LEPC (LoW Density Parity Check) decoder ".

Novel method provided by the invention uses single communication equipment and/or hardware to carry out the decode operation of various ldpc coded signals.Each code signal in these ldpc coded signals all has the corresponding LDPC matrix that can be used for carrying out decoding processing.The submatrix that may have in certain embodiments, equal number corresponding to each LDPC matrix of each LDPC coding.In other embodiments, the quantity of the submatrix in each LDPC encoder matrix may need inequality.The target of this method is the area overhead that minimizes communication equipment, reduces path congestion wherein simultaneously.

This method also can be used to be designed for the communication equipment of a plurality of ldpc coded signals of decoding.For example, the communication equipment of the ldpc coded signal of 12 kinds of any generations of encoding scheme can using an embodiment to obtain being used for decoding to use according to IEEE 802.11n standard.In addition, method of the present invention can use the mode that merges memory (for example using) when the mutual exclusion submatrix of decoding Different L DPC matrix to be optimized.

There is the whole bag of tricks to minimize to be used in the communication equipment quantity of hardware of a plurality of ldpc coded signals of decoding.For example, a kind of directly simple method comprises mutual superposition each LDPC matrix corresponding to each LDPC coding.No matter when the submatrix position obtains the result, and the LDPC matrix after the stack comprises nonzero element (non-null entry), and memory is used to store this submatrix position afterwards.This direct stacking method can provide enough hardware environment for a plurality of ldpc coded signals of decoding.In addition, the extra saving of the hardware components that obtains from this direct stacking method will be described among the embodiment of back.

The target of digital communication system is from a position or subsystem sends numerical data to another position or subsystem error-freely or with acceptable low error rate.As shown in Figure 1, data can be transmitted by the various communication channels in the plurality of communication systems: the media of magnetic media, wired, wireless, optical fiber, copper cable and other type.

Fig. 1 and Fig. 2 are respectively 100 and 200 schematic diagrames according to the communication system of different embodiments of the invention.

As shown in Figure 1, communication system 100 comprises a communication channel 199, and the communication equipment 110 (comprising transmitter 112 that has encoder 114 and the receiver 116 that has decoder 118) that will be positioned at communication channel 199 1 ends communicates to connect with another communication equipment 120 that is positioned at communication channel 199 other ends (comprising transmitter 126 that has encoder 128 and the receiver 122 that has decoder 124).In certain embodiments, communication equipment 110 and 120 all can only comprise a transmitter or a receiver.Communication channel 199 can realize by various dissimilar media (for example, utilize disc type satellite earth antenna 132 and 134 satellite communication channel 130, utilize tower 142 and 144 and/or radio communication channel 140, the wire communication channel 150 of local antenna 152 and 154 and/or utilize electrical-optical (E/O) interface 162 and the fiber optic communication channel 160 of light-electricity (O/E) interface 164).In addition, thus can link together by more than one media and form communication channel 199.

Not expect the error of transmission that occurs in the communication system in order reducing, to adopt error correction and channel coding schemes usually.Generally, these error correction and channel coding schemes comprise the use of transmitter end encoder and the use of receiver end decoder.

In the communication system 200 as shown in Figure 2, transmitting terminal in communication channel 299, information bit 201 is provided for transmitter 297, transmitter 297 can use encoder and symbol mapper 200 (can be considered as respectively is different functional blocks 222 and 224) to carry out coding to these information bits 201, thereby generate a centrifugal pump modulation symbol sequence 203, offer then and send driver 230.Send driver 230 and use DAC (digital to analog converter) 232 to generate to send signal 204 continuous time,, generate after the filtering that fully is fit to communication channel 299 and to send signal 205 continuous time then by transmitting filter 234.Receiving terminal in communication channel 299, continuous time, received signal 206 was provided for AFE (AFE (analog front end)) 260, and AFE 260 comprises receiving filter 262 (generate after the filtering continuous time received signal 207) and ADC (analog to digital converter) 264 (generation discrete time received signal 208).Measure maker (metric generator) 270 compute signs and measure (symbol metrics) 209, decoder 280 uses symbol to measure 209 the best-estimateds 210 of making centrifugal pump modulation symbol and coding information bit within it.

Decoder in the previous embodiment has various feature of the present invention.In addition, following some accompanying drawings and relevant description will be introduced other and the specific embodiment (introduction of some embodiment is more detailed) of supporting equipment of the present invention, system, functional and/or method.The signal of a kind of particular type of handling according to the present invention is a ldpc coded signal.Before providing more detailed introduction, earlier the LDPC sign indicating number is carried out summary description.

Fig. 3 shows an embodiment of the device 300 of carrying out the LDPC decoding processing.Device 300 comprises processing module 320 and memory 310.Memory 310 is connected to processing module 320, and memory 310 is used for stored energy and makes processing module 320 carry out various function operations instructions.Processing module 320 is used to carry out and/or control the mode of the LDPC decoding processing of carrying out according to the arbitrary embodiment described in the application or its equivalent embodiment.

Processing module 320 can use shared treatment facility, single treatment facility or a plurality of treatment facility to realize.Such processor can be microprocessor, microcontroller, digital signal processor, microcomputer, CPU, field programmable gate array, programmable logic device, state machine, logical circuit, analog circuit, digital circuit and/or based on any device of operational order processing signals (simulation and/or numeral).Memory 310 can be single memory device or a plurality of memory device.Such memory device can be any equipment of read-only memory, random access storage device, volatile memory, nonvolatile storage, static memory, dynamic memory, flash memory and/or storing digital information.Note, when treatment facility 320 was carried out its one or more functions by state machine, analog circuit, digital circuit and/or logical circuit, the memory of storage respective operations instruction was embedded in the circuit that comprises state machine, analog circuit, digital circuit and/or logical circuit.

Like this among some embodiment as if expectation, the mode (for example, moving to part, module and/or the functional module of bit-engine from the verification engine) of carrying out the LDPC decoding processing can offer the communication system 340 that the LDPC sign indicating number that uses expection is carried out the LDPC coding from installing 300.For example, also can offer any communication equipment 330 in the communication system 340 corresponding to the information (for example, the parity matrix of LDPC sign indicating number) of the LDPC sign indicating number that is used from processing module 320.In addition, in the arbitrary communication equipment 330 in the communication system 340 which kind of mode the LDPC sign indicating number of carrying out will be carried out in, also can provide from processing module 320.

If want, processing module 320 can be designed to generate the mode that generates multiple execution LDPC decoding according to a plurality of demands and/or expection.Among some embodiment, processing module 320 optionally provides the different information information of Different L DPC sign indicating number etc. (for example, corresponding to) to give different communication equipment and/or communication systems.Thereby the different communication link between the different communication equipment can be adopted different LDPC sign indicating numbers and/or carry out the mode of LDPC decoding.Obviously, processing module 320 can also provide identical information to each different communication equipment and/or communication system and can not break away from protection scope of the present invention and spirit.

Fig. 4 shows the device 400 of the execution LDPC decoding processing of another embodiment.Device 400 comprises processing module 420 and memory 410.Memory 410 is connected to processing module 420, and memory 410 is used for stored energy and makes processing module 420 carry out various function operations instructions.Processing module 420 (being served by memory 410) can be embodied as the equipment of any function that can carry out various module described herein and/or functional block.For example, processing module 420 (by memory 410 service) can be embodied as the equipment of the mode that is used to carry out and/or control the LDPC decoding processing carried out according to the arbitrary embodiment described in the application or its equivalent embodiment.

Processing module 420 can use shared treatment facility, single treatment facility or a plurality of treatment facility to realize.Such processor can be microprocessor, microcontroller, digital signal processor, microcomputer, CPU, field programmable gate array, programmable logic device, state machine, logical circuit, analog circuit, digital circuit and/or based on any device of operational order processing signals (simulation and/or numeral).Memory 410 can be single memory device or a plurality of memory device.Such memory device can be any equipment of read-only memory, random access storage device, volatile memory, nonvolatile storage, static memory, dynamic memory, flash memory and/or storing digital information.Note, when treatment facility 420 was carried out its one or more functions by state machine, analog circuit, digital circuit and/or logical circuit, the memory of storage respective operations instruction was embedded in the circuit that comprises state machine, analog circuit, digital circuit and/or logical circuit.

If expectation is like this, device 400 can be any one communication equipment 430, or the arbitrary portion in such communication equipment 430 among some embodiment.The communication equipment 430 that includes processing module 420 and memory 410 can be implemented in any communication system 440.Be also noted that the LDPC decoding processing among the application and/or each embodiment and the various equivalent embodiment thereof that revise according to the operating parameter that the LDPC decoding processing is carried out can be applicable to polytype communication system and/or communication equipment.

Fig. 5 is the schematic diagram of LDPC sign indicating number bipartite graph 500.In the field of business, the LDPC bipartite graph is also referred to as Tanner figure (Tan Natu).Have the binary parity check matrix to make nearly all element of matrix all be the code of null value (for example, this binary parity check matrix is a sparse matrix) thereby the LDPC sign indicating number is counted as.For example, H=(h _Ij) _MxNBeing counted as block length is the LDPC sign indicating number parity matrix of N.

The LDPC sign indicating number is the linear zone block code, so the set x ∈ C of all code words is distributed in the kernel of parity check matrix H.

H x^{T} = 0, &ForAll; x &Element; C

(1)

For the LDPC sign indicating number, H is the sparse binary matrix of m * n dimension.Every row of H is corresponding to a parity check, a group element h _IjExpression data symbol j participates in parity check i.Every row of H are corresponding to code-word symbol.

For each code word x, n symbol arranged, wherein m is parity character.Therefore, encoding rate r is given as:

r＝(n-m)/n(2)

The weight of row and column is defined as the quantity of set element of the given row or column of H respectively.The set element of H is chosen to be the performance requirement that satisfies coding.1 quantitaes is d in the i row of parity matrix _v(i), the quantitaes of the j of parity matrix 1 in capable is d _c(j).If to all i, d _v(i)=d _v, to all j, d _c(j)=d _c, so this LDPC sign indicating number is called as (d _v, d _c) regular LDPC sign indicating number, otherwise be called as abnormal LDPC code.

Introduction about the LDPC sign indicating number please refer to below with reference to file:

[1]R.Gallager，Low-Dentisy?Parity-Check?Codes，Cambridge，MA：MITPress，1963.

[2]R.G.?Gallager，“Low?dentisy?parity?check?codes，”IRE?Trans.Info.Theory.Vol.IT-8，Jan.1962，pp.21-28.

[3] M.G.Luby，M.Mitzenmacher，M.A.Shokrollahi，D.A.Spielman，and?V.Stemann.“Practical?Loss-Resilient?Codes”，Proc.29 ^th?Symp.On?Theory?OfComputing，1997，pp.150-159.

Rule LDPC sign indicating number can be expressed as bipartite graph 500, the left node of its parity matrix is code bit variable (or being " variable node " (or " bit node ") 510 in the bit coding/decoding method of adapted for decoding LDPC code signal), and the right side node is check equations (or " check-node " 520).Bipartite graph 500 (or being called smooth Figure 50 of receiving 0) by the LDPC sign indicating number of H definition can be defined by N variable node (for example, N bit node) and M check-node.Each variable node in N variable node 510 all has accurate d _v(i) individual limit (as limit 530) connects for example v of bit node _i512 with one or more check-nodes (M check-node interior).Limit 530 shown in the figure connects position node v _i512 with check-node c _j522.This d _vIndividual limit is (as d _vShown in 514) quantity d _vThe degree i that is called as variable node.Similarly, each check-node in M check-node 520 all has accurate d _c(j) individual limit is (as d _cShown in 524), connect this node and one or more variable node (or bit node) 510.The quantity d on this limit _cThe degree j that is called as check-node.

Variable node v _i(or bit node b _i) 512 with check-node c _jLimit 530 between 522 can be defined as e=(i, j).But on the other hand, (i, j), then the node on this limit can be expressed as e=(v (e), c (e)) (or e=(b (e), c (e))) to give deckle e=.Perhaps, the limit in the bipartite graph is corresponding to the set element of H, wherein, and set element h _JiRepresent that a limit connects bit (for example, variable) node i and parity check node j.

Suppose and provide variable node v _i(or bit node b _i), can be with from node v _i(or bit node b _i) one group of limit of launching is defined as E _v(i)={ e/v (e)=i} (or E _b(i)={ e/b (e)=i}).These limits are called as the bit limit, and are called as bit limit message corresponding to the message on these bit limits.

Suppose and provide check-node c _j, can be with from node c _jOne group of limit of launching is defined as E _c(j)={ e/c (e)=j}.These limits are called as the verification limit, and are called as verification limit message corresponding to the message on these verification limits.Then, the result of derivation is | E _v(i) |=d _v(or | E _b(i) |=d _b) and | E _c(j) |=d _c

In general, the code that any available bipartite graph is represented, its feature all is a graphic code.Be noted that the also available bipartite graph of abnormal LDPC code represents.But the degree of the every group node in the abnormal LDPC code can be selected according to some distribution.Therefore, for two different variable nodes of abnormal LDPC code

With | E _v(i ₁) | may be not equal to | E _v(i ₂) |.For two check-nodes also is this relation.The notion of abnormal LDPC code has provided introduction in above-mentioned reference paper [3].

In a word, by the diagram of LDPC sign indicating number, the parameter of LDPC sign indicating number can be defined by the degree that distributes, and described in the above-mentioned reference paper [3], relevant description is arranged also in the following reference paper as M.Luby etc.:

[4]T.J.Richardson?and?R.L.?Urbanke，“The?capacity?of?low-densityparity-check?code?under?message-passing?decoding”，IEEE?Trans.Inform.Theory，Vol.47，No.2，Feb.2001，pp.599-618.

This distribution can be described below:

Use λ _iExpression is from the mark of degree for the limit of the variable node emission of i, ρ _iExpression is from the mark of degree for the limit of the check-node of i emission, then degree distribute to (λ ρ) is defined as follows:

λ (x) = Σ_{i = 2}^{M_{v}} λ_{i} x^{i - 1}

With

ρ (x) = Σ_{i = 2}^{M_{c}} ρ_{i} x^{i - 1},

M wherein _vAnd M _cThe maximal degree of representing variable node and check-node respectively.

Though a plurality of embodiment described here adopts regular LDPC sign indicating number, be noted that feature of the present invention both had been applicable to regular LDPC sign indicating number, also was applicable to abnormal LDPC code.

It is also noted that the most embodiment that describe among the application adopt the such name of statement of " bit node " and " bit limit message " or equivalence.But in the prior art of LDPC decoding, " bit node " and " bit limit message " is otherwise known as " variable node " and " variable edge message " usually, and therefore, bit value (or variate-value) is that those attempt estimated value.These two kinds of names can be adopted by the application.

Fig. 6 shows an embodiment of LDPC decoding function 600.In order to carry out the decoding of ldpc coded signal, adopted functional block shown in Figure 6 with m bit signal sequence.In general, receive continuous time signal (continuous-time signal) from communication channel, shown in drawing reference numeral 601.This communication channel can be the channel of any kind, includes but not limited to the communication channel that channel maybe can transmit the other types of the continuous time signal that has used LDPC sign indicating number coding of reading of wire communication channel, radio communication channel, fiber optic communication channel, HDD.

610 pairs of these continuous time signals of AFE (analog front end) (AFE) are carried out any initial treatment (for example, by carrying out one or more processing such as filtering (simulation and/or digital filtering), gain-adjusted) and are carried out the numeral sampling, thereby generate discrete-time signal 611.This discrete-time signal 611 be otherwise known as digital signal, baseband signal or other name well known in the prior art.Usually, discrete-time signal 611 is divided into I, Q (homophase, the quadrature) value of signal.

Tolerance maker 620 receives discrete-time signal 611 (for example, it includes I, Q value), and calculates corresponding bit metric and/or log-likelihood ratio (LLR) 621, and it is corresponding to the reception value in the discrete-time signal 611.Among some embodiment, the calculating of these bit metric/LLR symbol tolerance 621 is processing of two steps, wherein, tolerance maker 620 at first calculates the symbol tolerance corresponding to the symbol of discrete-time signal 611, measures maker then and adopts this symbol to measure again to decompose these symbols tolerance and be bit metric/LLR 621.Use these bit metric/LLR 621 (for example to come initialization bit limit message by bit-engine 630 then, shown in drawing reference numeral 629), when handling 635 (for example, performed as bit-engine 630 and verification engine 640), the iterative decoding of carrying out ldpc coded signal will use this bit limit message.

The value of log-likelihood ratio (LLR) is λ _i, the value of corresponding receiving symbol is y _iSituation under, can be defined as follows at the initialization of the bit limit message of each variable node i:

λ_{i} = \ln [\frac{\Pr (x_{i} = 0 | y_{i})}{\Pr (x_{i} = 1 | y_{i})}]

(3)

Equally, at the bit node place, bit-engine 630 uses the bit limit message of recent renewal to calculate the corresponding soft information (for example, shown in soft information 632) of this bit.Yet, to carry out the iteration of repeatedly decoding usually, thereby be transmitted to verification engine 640 through initialized bit limit message, therein, in the iterative process of decoding for the first time, verification engine 640 adopts this information updating verification limit, initialized bit limit message.

At each check node, the LDPC decoding processing goes up formation parity check result (XOR) in the sign (sign) of inbound messages.This sign by finding out each outbound message is carried out as the XOR of the sign of the corresponding inbound messages with this parity check result.

Then, calculate the outbound message reliability of (for example, variable) node i from check-node j to bit according to following formula:

λ_{ji} = {2 \tanh}^{- 1} (\underset{k, h_{jk} = 1, k &NotEqual; i}{Π} \tanh (\frac{λ_{jk}}{2}))

(4)

Among the embodiment of some expectation, this calculating is carried out in log-domain, and is converting multiplication to addition, as follows:

λ_{ji} = {2 \tanh}^{- 1} (\exp {\underset{k, h_{jk} = 1, k &NotEqual; i}{Σ} \log (\tanh (\frac{λ_{jk}}{2}))})

(5)

After this, the limit message (for example, shown in verification limit message 641) that bit-engine 630 receives through upgrading from verification engine 640, and utilize their update bit limit message.Equally, bit-engine 630 is also used the bit metric/LLR 621 that receives from tolerance maker 620 when the renewal of bit limit message is carried out in foundation LDPC decoding.Then, these verification limit message 641 through upgrading are transferred back to bit node (for example, bit-engine 630), use the current iteration value of bit metric/LLR 621 and verification limit message to calculate the soft information 632 of this bit at this.At each bit (for example, variable) node place, the calculating of soft information comprise formation from the receiving symbol in the inbound messages (for example, verification limit message 641) of check-node LLR's and.The bit that decodes

Sign (sign) by the summation of obtaining provides.Each outbound message of iteration of being used for next time decoding calculates by deduct corresponding inbound messages from this summation.Handle 635 in order to continue iterative decoding, these bit limit message 631 are transmitted to verification engine 640 after being updated.

Carry out the iteration of decoding again then.At check node, verification engine 640 receive from bit node (for example) from bit node 630 send through updated bits limit message 631, and upgrade verification limit message in view of the above.Then, the verification limit message 641 through upgrading is sent back bit node (for example, bit-engine 630), use the current iteration value of bit metric/LLR 621 and verification limit message to calculate the soft information 632 of bit at this.After this, use the soft information 632 of this bit that has just calculated, bit-engine 630 reuses last value (from previous iteration just) the update bit limit message of verification limit message.The LDPC sign indicating number bipartite graph that is adopted during according to the just decoded signal of coding, iterative processing 635 is proceeded between bit node and check-node.

Bit node engine 630 and check-node engine 640 these performed iterative decoding treatment steps repeat, up to satisfying stopping criterion, shown in drawing reference numeral 661 (for example, after having carried out iterations predetermined or that self adaptation is determined, all syndromes of LDPC sign indicating number (for example all equal zero the back, all parity checks are all satisfied), and/or satisfied other stopping criterion).The another kind of mode that the LDPC decoding stops is the current estimated value when the LDPC code word

Stop when satisfying following the relation:

H {\hat{x}}^{T} = 0

In each decoding iterative process, soft information 632 can generate in bit-engine 630.Among this embodiment shown in the figure, soft information 632 can be offered the hard limiter (hard limiter) 650 of making hard decision, and whether hard information (for example, hard/best estimate 651) can offer syndrome calculator 660 and all equal zero with the syndrome of determining the LDPC sign indicating number.That is to say that syndrome calculator 660 determines whether that based on the current estimated value of LDPC code word each syndrome relevant with the LDPC sign indicating number all equals zero.

When syndrome is not equal to zero, continue iterative decoding again and handle 635, suitably between bit node engine 630 and check-node engine 640, upgrade and transmission bit limit message and verification limit message.Execute institute that iterative decoding handles in steps after, based on hard/best estimate 651 of soft information 632 these bits of output.

It is also to be noted that, for good decoding performance, in the bipartite graph length of cycle period as much as possible length be very important.Short cycle period for example 4 circulates, and may reduce the performance of the message-passing decoding method that is used for decoding LDPC numbering signal.

Though the mathematical computations of message-passing decoding method comprises hyperbolic function and logarithmic function (referring to equation (5)), in hardware was realized, these functions also can approach or directly realize by gate by look-up table (LUT).Mathematical computations only relates to addition, subtraction and xor operation.The quantity of fixing point required bit in realizing is by the speed of required coding efficiency, decoder convergence and whether essential compacting error code flat bed (error floor) (as descriptions of reference paper [5] institute) is next definite.

[5]Zhang，T.，Wang，Z.，and?Parhi，K.，“On?finite?precision?implementationof?low?density?parity?check?codes?decoder”，Proceedings?of?ISCAS，Sydney，Australia，May?2001，pp?202-205.

Fig. 7 shows the embodiment 700 of the non-zero submatrices stack of a plurality of LDPC matrixes.Embodiment 700 has described corresponding to two independent LDPC matrixes of two independent LDPC codings (coding 1, LDPC matrix 0 and encode 2, LDPC matrix 720).Each all comprises 4 submatrixs in the LDPC matrix 710 and 720, and wherein two is that zero submatrix, two are non-zero submatrix (for example comprising more than one nonzero element).

Coding 1, LDPC matrix 710 comprise non-zero submatrices 711 and non-zero submatrices 712; Coding 2, LDPC matrix 720 comprise non-zero submatrices 721 and non-zero submatrices 722.LDPC matrix 710 and 720 stack backs generate stack LDPC matrix 730.As shown in the figure, non-zero submatrices 711 and non-zero submatrices 712 are in same position in stack LDPC.In this embodiment, only stay next non-zero submatrices in the stack LDPC matrix 730.

Figure 8 shows that the embodiment 800 of memory supply with the processing demands of the non-zero submatrices that adapts to stack LDPC matrix 730 shown in Figure 7.The single memory structure that is used for each LDPC coding of stack LDPC matrix 730 is carried out decoding processing can adopt three memories, 810 structure (be shown among the figure and comprise memory 811, memory 812 and memory 813) or two memory constructions (be shown among the figure and comprise memory 821 and memory 822).In any one embodiment, each memory can selectivity be connected to bit-engine and verification engine, handle and code check node processing in order to carry out bit node respectively, thus update bit limit message and verification limit message.

Fig. 9 A and Fig. 9 B show the embodiment 901 and 902 of decoding device, are used for handling the non-zero submatrices of the stack LDPC matrix of Fig. 7.

Referring to Fig. 9 A, this embodiment comprises three memories (being memory 811, memory 812 and memory 813).Bit metric/LLR offers a plurality of bit-engine (for example bit-engine 931 and bit-engine 932).Handover module 991 is connected between bit-engine 931-932 and the memory 811-813.Another switch engine 992 is connected between verification engine 921-922 and the memory 811-813.

Should be noted that handover module 991 (and herein describe other handover module) can use the multiplexer (MUX) with a plurality of I/O ends, a plurality of MUX or allow other device that selection is connected between memory and bit-engine and memory and verification engine to realize.

In to LDPC coding 1 process of decoding, there is a memory not use (for example memory shown in the figure 812), and uses memory 811 to handle submatrix 711, use memory 813 processing submatrixs 712, otherwise or.

As selection, also can use single handover module (for example verification engine 921-922 can be connected to handover module 991).

After executing suitable bit node processing and code check node processing and satisfying stopping criterion, bit-engine 931-932 operation generates soft information, can obtain from this soft information for the best-estimated according to the coded-bit in coding 1 ldpc coded signal of encoding.

Referring to Fig. 9 B, in to LDPC coding 2 processes of decoding, be again to have a memory not use (for example memory shown in the figure 813), and use memory 811 to handle submatrix 721, use memory 812 processing submatrixs 722, otherwise or.

Same as selecting, also can use single handover module (for example verification engine 921-922 can be connected to handover module 991).

After executing suitable bit node processing and code check node processing and satisfying stopping criterion, bit-engine 931-932 operation generates soft information, can obtain from this soft information for the best-estimated according to the coded-bit in coding 2 ldpc coded signals of encoding.

The embodiment of Fig. 9 A and Fig. 9 B shows direct simple superposition method, has wherein used three independent memories.Below, the ldpc coded signal that two identical LDPC of foundation encode can use only has the structure of two memories to decode.

Figure 10 shows the schematic diagram of embodiment of the decoding device of the non-zero submatrices that is used for handling Fig. 7 stack LDPC matrix 730.How this embodiment only shows with two memories to come identical LDPC matrix 710 decode with 720 (relative use three memories).As shown in the figure, (LDPC matrix 710) submatrix 712 is not in identical submatrix position with (LDPC matrix 720) submatrix 722 in each LDPC matrix 710 and 720.In each LDPC matrix 710 and 720, these two sub-matrix positions are mutual exclusion (mutually exclusive).Therefore, can use independent memory (for example merging memory), foundation coding 1 first ldpc coded signal of encoding is being carried out in the process of decoding processing, execution is to the decoding processing of submatrix 712, and, carry out decoding processing to submatrix 722 to carrying out in the process of decoding processing according to coding 2 first ldpc coded signals of encoding.

About merging memory,, then obviously can remove this memory if certain memory is not used by the LDPC coding.Therefore, memory only needs to offer those submatrixs that have nonzero element among the resulting stack LDPC.And each memory also has at least one non-zero LDPC to be coded in wherein movable (this LDPC coding for example is used to decode).

As mentioned above, can obtain more high efficiency by the memory member that merges corresponding to the mutual exclusion non-zero submatrices.That group memory that stores mutual exclusion activity No group can be merged into single memory.The amount of memory that stores mutual exclusion activity No group many more (they can suitably be determined), the merging degree that then can reach is big more and can save more hardware (for example reducing the use amount of memory).

Referring to Figure 10, this embodiment only comprises two memories (being memory 1011 and memory 1012).Bit metric/LLR offers a plurality of bit-engine (for example bit-engine 1031 and bit-engine 1032).Handover module 1091 is connected between bit-engine 1031-1032 and the memory 1011-1012.Another switch engine 1092 is connected between verification engine 1021-1022 and the memory 1011-1012.

As another embodiment, should be noted that handover module 1091 (and herein describe other handover module) can use the multiplexer (MUX) with a plurality of I/O ends, a plurality of MUX or allow other device that selection is connected between memory and bit-engine and memory and verification engine to realize.

In to LDPC coding 1 process of decoding, two memory 1011-1012 are using.Memory 1011 is used to handle submatrix 711, and memory 1012 is used to handle submatrix 712, otherwise or.

After executing suitable bit node processing and code check node processing and satisfying stopping criterion, bit-engine 1031-1032 operation generates soft information, can obtain from this soft information for the best-estimated according to the coded-bit in coding 1 ldpc coded signal of encoding.

Again, in to LDPC coding 2 processes of decoding, two memory 1011-1012 are using.Memory 1011 is used to handle submatrix 721, and memory 1012 is used to handle submatrix 722, otherwise or.

After executing suitable bit node processing and code check node processing and satisfying stopping criterion, bit-engine 1031-1032 operation generates soft information, can obtain from this soft information for the best-estimated according to the coded-bit in coding 2 ldpc coded signals of encoding.

As selection,, also can use single handover module (for example verification engine 1021-1022 can be connected to handover module 1091) as another embodiment.

As shown in the figure, merging memory (for example memory shown in the figure 1012) can be used to carry out to the processing of 1 the non-zero submatrices 712 of encoding and be used to carry out processing to 2 the non-zero submatrices 722 of encoding.The principle of using the merging memory to carry out the decoding processing of mutual exclusion non-zero submatrices also can expand to bigger LDPC matrix.

Figure 11 shows the schematic diagram of embodiment 1100 of the decoding device of the non-zero submatrices that is used to handle stack LDPC matrix.This embodiment can promote, with the decoding processing of the code signal that is applicable to the LDPC matrix of wanting size arbitrarily.

Referring to Figure 11, this embodiment comprises a plurality of memories 1110 (being memory 1111-1113).Bit metric/LLR offers a plurality of bit-engine (for example bit-engine 1131 and bit-engine 1133).Handover module 1191 is connected between bit-engine 1131-1133 and a plurality of memory 1110.Another switch engine 1192 is connected between verification engine 1121-1123 and a plurality of memory 1110.

Again, as another embodiment, should be noted that handover module 1191 (and herein describe other handover module) can use the multiplexer (MUX) with a plurality of I/O ends, a plurality of MUX or allow other device that selection is connected between a plurality of memories 1110 and a plurality of bit-engine 1131-1133 and these memories 1110 and a plurality of verification engine 1121-1123 to realize.

In the process that first signal of being encoded according to a LDPC is decoded, first subclass of memory 1110 is used for handling the non-zero submatrices of the LDPC matrix that a LDPC encodes.

In the process that the secondary signal of being encoded according to the 2nd LDPC is decoded, second subclass of memory 1110 is used for handling the non-zero submatrices of the LDPC matrix that the 2nd LDPC encodes.

In the process that the 3rd signal of being encoded according to the 3rd LDPC is decoded, the three subsetss of memory 1110 are used for handling the non-zero submatrices of the LDPC matrix that the 2nd LDPC encodes.

So analogize ...

In certain embodiments, when each code signal of decoding, use a plurality of memories 1110 of equal number.In other embodiments, when the code signal of decoding different, use a plurality of memories of varying number.For example, in various embodiments, each of above-mentioned first subclass, second subclass and three subsetss can comprise the memory of equal number, perhaps comprises the memory of varying number.

Handover module

1191 and 1192 is used for guaranteeing suitable connection between a plurality of bit-engine 1131-1133 and a plurality of memory 1110 obtaining in the required verification limit message of the implementation of update bit limit message, and

handover module

1191 and 1192 is used for guaranteeing that suitable connection between a plurality of verification engine 1121-1123 and a plurality of memory 1110 is to obtain in the required bit limit message of implementation of upgrading verification limit message.

After executing suitable bit node processing and code check node processing and satisfying stopping criterion, bit-engine 1131-1132 operation generates soft information, can obtain the best-estimated for the coded-bit in the ldpc coded signal of encoding according to this interested specific LDPC from this soft information.

Figure 12 shows the schematic diagram of another embodiment 1200 of the decoding device of the non-zero submatrices that is used to handle stack LDPC matrix.

Referring to Figure 12, this embodiment comprises a plurality of memories 1210 (being memory 1211-1213).Bit metric/LLR offers a plurality of bit-engine (for example bit-engine 1231 and bit-engine 1233).Handover module 1291 is connected between a plurality of bit-engine 1231-1233 and a plurality of memory 1210.Same switch engine 1191 also provides selectable connectedness between verification engine 1221-1223 and a plurality of memory 1210.

In the process that first signal of being encoded according to a LDPC is decoded, first subclass of memory 1210 is used for handling the non-zero submatrices of the LDPC matrix that a LDPC encodes.

In the process that the secondary signal of being encoded according to the 2nd LDPC is decoded, second subclass of memory 1210 is used for handling the non-zero submatrices of the LDPC matrix that the 2nd LDPC encodes.

In the process that the 3rd signal of being encoded according to the 3rd LDPC is decoded, the three subsetss of memory 1210 are used for handling the non-zero submatrices of the LDPC matrix that the 2nd LDPC encodes.

So analogize ...

In certain embodiments, when each code signal of decoding, use a plurality of memories 1210 of equal number.In other embodiments, when the code signal of decoding different, use a plurality of memories of varying number.For example, in various embodiments, each of above-mentioned first subclass, second subclass and three subsetss can comprise the memory of equal number, perhaps comprises the memory of varying number.

Handover module 1291 is used for guaranteeing suitable connection between a plurality of bit-engine 1231-1233 and a plurality of memory 1210 obtaining in the required verification limit message of the implementation of update bit limit message, and handover module 1291 is used for also guaranteeing that suitable connection between a plurality of verification engine 1221-1223 and a plurality of memory 1210 is to obtain in the required bit limit message of implementation of upgrading verification limit message.

After carrying out suitable bit node processing and node checking treatment, and run into that bit-engine 1231-1232 will generate soft information when stopping criterion from best estimate, described best estimate can be to make according to the ldpc coded signal of the LDPC sign indicating number coding of special interests.

Figure 13 and 14 shows the hardware instruction of the non-zero submatrices of the stack LDPC matrix that is used to decode.

With reference to Figure 13, each ldpc coded signal of decoding according to embodiment 4300 has the non-zero submatrices of equal number.In the ldpc coded signal process of decoding according to each LDPC sign indicating number coding, unique difference is that the memory subclass that each code signal adopts is different.

For example, when decoding according to sign indicating number 1 encoded signals, corresponding LDPC matrix comprises ' X ' non-zero submatrices, all bit-engine that provide (provisioned bit engines) can be used for bit node and handle.All verification engines that provide are used for checking treatment.Ading up to of memory ' Y ', use wherein ' the individual memory of X ', promptly use the subclass 1 in these ' Y ' individual memories.

When decoding according to sign indicating number 2 encoded signals, corresponding LDPC matrix comprises ' the individual non-zero submatrices of X ', all bit-engine that provide can be used for bit node and handle.The verification engine that all provide is used for checking treatment.Ading up to of memory ' Y ', use wherein ' the individual memory of X ', promptly use the subclass 2 in these ' Y ' individual memories.So analogize, as shown in FIG..

As seen, in embodiment 1300, when the different ldpc coded signal of decoding, its unique difference is the difference of the subclass of the memory that uses.

When decoding during according to each ldpc coded signal of the coding of each the LDPC sign indicating number among Figure 13, the quantity of bit-engine of using and verification engine is the same.

With reference to Figure 14, embodiment 1400 shows the embodiment of the employing depth of parallelism (various degrees ofparallelism) in various degree.This embodiment 1400 shows changeability preferably and the flexibility when the ldpc coded signal of decoding different.

For example, when decoding according to sign indicating number a encoded signals, corresponding LDPC matrix comprises ' the individual non-zero submatrices of a1 '.Ading up to ' a2 subclass in the bit-engine that provides of M ' can be used for bit node and handles, ading up to ' a3 subclass in the verification engine that provides of L ' can be used for the node checking treatment, and can use the subclass a4 that adds up in ' Z ' available memory in ' a2 ' or ' the individual memory of a3 ', can use ' individual memory of Z '.

When decoding according to sign indicating number b encoded signals, corresponding LDPC matrix comprises ' the individual non-zero submatrices of b2 '.Ading up to ' b2 subclass in the bit-engine that provides of M ' can be used for bit node and handles, ading up to ' b3 subclass in the verification engine that provides of L ' can be used for the node checking treatment, and can use the subclass b4 that adds up in ' Z ' available memory in ' b2 ' or ' the individual memory of b3 ', can use ' individual memory of Z '.So analogize, as shown in FIG..

For example, in embodiment 1400, can use repeatedly circulation to carry out each sub-iteration (for instance, bit node is handled or node check processing).The bit node of attention in an example handled, can be in the very first time, use provides the first half of the bit-engine update bit limit message (bit edge messages) of quantity, and can in second time, use provide the bit-engine update bit of quantity limit message back half, this can regard half depth of parallelism bit node processing method as, like this, substep is finished and is separated numeral iteration (for instance, bit node is handled) in two steps.

In another embodiment, note node checking treatment in another example, can in the very first time, use provide the verification of quantity engine upgrade verification limit message first 1/3rd, and in second time, use provides the verification engine of quantity to upgrade second 1/3rd of verification limit message, and in the 3rd time, use the verification engine that quantity is provided upgrade verification limit message last 1/3rd.This can regard depth of parallelism node verifying method as, and like this, substep is finished and separated numeral iteration (node checking treatment for instance) in three steps.

Significantly, under the situation that does not depart from scope and spirit of the present invention, can make multiple conversion to the present invention, therefore, the cycle-index that each sub-iteration adopts can change according to certain embodiments.

Get back to embodiment 1400, each LDPC matrix need not to comprise the non-zero submatrices of equal number.When the specific ldpc coded signal (when all memories that provides are provided) of decoding, the memory that is used for corresponding zero submatrix of specific LDPC can disconnect.In the decode procedure of signal specific, when specific memory is not used, this memory can be disconnected (remove for instance, and connect) from the remainder with circuit disturbs initiatively computing (active computation) and can save energy to prevent free storage.The disconnection of this memory can be set to 0 (or maximum " maxval ") to the input of memory by each variable node and check-node and realize, these variable nodes and check-node link to each other with this specific untapped submatrix (zero submatrix) of this particular code that is used to decode respectively.

Figure 15 and 16 shows and uses at least one to merge the embodiment of memory (merge memory).In these embodiments, the memory that existence can following use.

When decoding according to sign indicating number 0 and 1 encoded signals, memory A can use, and when other yard of decoding, the memory A free time.

When decoding according to sign indicating number 2 and 3 encoded signals, memory B can use, and when other yard of decoding, memory B is idle.

Figure 15 shows the connectedness that is used for according between 2 mutual exclusion memories of LDPC decoding processing code check node processing.This embodiment shows when decoding how to use memory A during according to sign indicating number 0 and 1 encoded signals, and when showing encoded signals when other yard of decoding, how memory A is removed from hardware to connect (disconnection for instance).When some signal of decoding, when memory A did not use, memory A disconnected (for instance, removing connection) effectively from the remainder of hardware/circuit and disturbs initiatively computing to prevent free storage, and can save the energy.The disconnection of this memory can be set to 0 (or maximum " maxval ") to the input of memory by each variable node and check-node and realize, these variable nodes and check-node link to each other with this specific untapped submatrix (zero submatrix) of this particular code that is used to decode respectively.

This embodiment also shows when decoding how to use memory B during according to sign indicating number 2 and 3 encoded signals, and when showing code signal when other yard of decoding, how memory B is removed from hardware to connect (disconnection for instance).When some signal of decoding, when memory B did not use, memory B disconnected (for instance, removing connection) effectively from the remainder of hardware/circuit and disturbs initiatively computing to prevent free storage, and can save the energy.The disconnection of this memory can be set to 0 (or maximum " maxval ") to the input of memory by each variable node and check-node and realize, these variable nodes and check-node link to each other with this specific untapped submatrix (zero submatrix) of this particular code that is used to decode respectively.

It should be noted that among the figure and not shown this variable/bit-engine to being connected of memory A and B, in following figure, also not shown this variable/bit-engine arrives the connection of memory C.Yet, for those skilled in the art, after the connectedness that shows the verification engine, it will be appreciated by those skilled in the art that the connectedness of the variable/bit-engine of being correlated with.

As seen, memory A and B can merge to single memory C.Then, when decoding according to

sign indicating number

0,1,2 and 3 encoded signals, memory C can use, and when other yard of decoding encoded signals, the described memory C free time.

It should be noted that be when providing separately at this when merging memory, it can keep the connectedness of all appearance.In the example shown in Figure 15 and 16, when using memory C (Figure 16), original connectedness of memory A and memory B (Figure 15) can be kept.

For example, consider at memory A and memory B and have the mutual exclusion code character, and memory A be in the embodiment in the submatrix that is different from memory B is capable (for instance, among memory A and the memory B each is corresponding to the submatrix of diverse location in LDPC matrix really), memory A will link to each other with different check-nodes with B so, and can merge among the memory C.Similarly, memory C can keep the connectedness of memory A to check-node, also can keep the connectedness of memory B to check-node.

Figure 16 shows the embodiment 1600 that is used for according to the connectedness of the merging memory of the code check node processing of LPDC decoding processing.Go on foot among the embodiment two, adopt 3MUX to replace memory A and B to allow single memory C.

Figure 17 shows the embodiment of the method 1700 that is used to handle ldpc coded signal.

With reference to Figure 17, as shown in square frame 1710, this method 1700 comprises the reception continuous time signal at first.As shown in square frame 1712, the reception of this continuous time signal and processing procedure can comprise carries out the down-conversion of any necessity to generate second continuous time signal to first continuous time signal.Can be by being that base band frequency realizes frequency translation with the carrier frequency Direct Conversion.Alternatively, this frequency translation can be passed through IF (intermediate frequency) realization.In arbitrary embodiment, when this method of execution, this continuous time signal that receives generally is down-converted to the base band continuous time signal.Similarly, gain-adjusted/gain controlling of certain type can be applied to the continuous time signal that this receives.

As shown in square frame 1720, this method 1700 can comprise that also sampling first (or second) continuous time signal is to generate discrete signal and therefrom to extract I, Q (homophase, integration) component.Can use ADC (analog to digital converter) or similar device with from suitable down-conversion (and can through filtering, gain-adjusted etc. processing) the continuous time signal that receives generate discrete signal.Also can extract I, the Q component of the single sampling of discrete-time signal in this step.Then, as shown in square frame 1730, method 1700 comprises this I of demodulation, Q component, and can comprise that () sign map for instance, to having the mapped constellation figure of constellation point is to generate the centrifugal pump modulation symbol sequence to this I, Q component.

As shown in square frame 1740, next step of method 1700 comprises that carrying out the limit information updating stops criterion (for instance, default number of iterations equals 0 up to all symbols, or stops criterion up to running into other) up to running into.This step can be regarded the LPDC decoding of execution according to above-mentioned various embodiment as.This LPDC decoding generally comprises the verification engine that the bit-engine that is used for update bit limit message (for instance, variable limit message) handles (as shown in square frame 1742) and be used to upgrade verification limit message and handles (as shown in square frame 1744).

As shown in square frame 1746, method 1700 also can comprise when the interested specific LPDC code signal of decoding, and the selected hardware of sampling is to offer selected LDPC sign indicating number.For example, this method 1700 is used to carry out the processing to different ldpc coded signals, (and therefore having different LDPC matrixes respectively) that these ldpc coded signals are to use different LDPC sign indicating numbers to generate.Depend on decoded signal, method 1700 is used to select the hardware that provides suitable, to carry out the decoding to interested specific LPDC code signal.

As shown in square frame 1750, run into stop criterion after, method 1700 comprise based on corresponding to the soft information of the bit side information of latest update to make hard decision (hard decision).This method 1700 comprises the best estimate of the LDPC coded-bit (LDPC code word or LDPC sign indicating number district for instance) (comprising information bit) that output is extracted at last from the continuous time signal that receives.

Figure 18 shows the embodiment of the method 1800 that is used to handle ldpc coded signal.

As shown in square frame 1810, this method 1800 starts from all required LDPC matrixes of identification all ldpc coded signals of decoding.

Then as shown in square frame 1820, this method 1800 generates the stack result (comprising for instance, the stack of each submatrix position of all LDPC matrixes) of all LDPC matrixes.

Then as shown in square frame 1830, this method 1800 provides the memory of the submatrix that adapts to each stack result.This can finish in several ways, and can comprise a step arbitrarily.In one embodiment, this comprises the first greedy deep search that this last stack LDPC matrix is carried out, to determine required memory number (as shown in square frame 1822).

Though can adopt polynomial time to merge searching algorithm to obtain the solution that memory provides, it always can not provide from minimum memory solution.In 4 node embodiment, it is alphabetical that this node can be regarded as.

Message groups	The merging ability
		A	B、C
B	A、D
		C	A
D	B

Memory A can merge with memory B, and can not take place further to merge.The minimum memory solution of this 4 node can merge memory A and memory B (for instance, merging to memory E), and merges memory C and memory D (for instance, merging to memory F).

Also can adopt first deep search to obtain minimum memory solution, such one first full deep search is detailed, and can find actual minimum memory solution.Yet some embodiment has shown the difficulty when this scheme of use.Can regulate to adapt to IEEE802.11n standard and all 12 LDPC sign indicating numbers (each yard has own corresponding LDPC matrix) herein the tree root of solution when considering, the tree root that is then used in IEEE 802.11n standard has 2041 branches.The result of the maximal tree degree of depth is about 105.(O (2041) ¹⁰⁵) region of search can not under the situation that does not need conditions such as a large amount of processing and time, finish whole search.

Can adopt one or more heuristic that method (heuristic) is finished the search of minimum storage requirement (or less relatively storage requirement) and the stack LDPC matrix that in the end obtains in the merging of memory become simpler.Can adopt along the tolerance of those affine row of row.In addition, can be used for management merges search and heuristics some hypothesis of method and comprise: and (1) variable/and bit node can compress toward each other, check-node can cover the relatively large zone in the stack LDPC matrix that obtains at last, and (2) memory that will provide tightly bunchiness around (tightly clustered) around variable/bit node.

This search such method of heuristicing of can sampling, the memory that belongs to the stack LDPC matrix column that obtains at last are bunchiness tightly, and check-node is connected to the different lines of this stack LDPC matrix.

Then can generate this and be listed as affine tolerance based on being connected between the row of specific submatrix and other submatrix in the stack LDPC matrix that in the end obtains and the row.In another embodiment following, this is listed as the first greedy deep search that affine tolerance can be used for controlling/managing the stack LDPC matrix that obtains at last.

As shown in square frame 1824, this can comprise that also the memory set that will have the mutual exclusion active code merges in the memory.As shown in square frame 1826, this method 1800 also can comprise the merging patterns (for instance, merging based on the first greedy deep search and mutual exclusion) that generate memory, and based on this memory is set.

Then, as shown in square frame 1831, method 1800 uses the 1st subclass decoding of the memory that provides to have first ldpc coded signal of the first corresponding LDPC matrix.

As shown in square frame 1832, if ldpc coded signal will be decoded, so, method 1800 then can use the n subclass decoding of the memory that provides to have the nLDPC code signal of the corresponding LDPC matrix of n.

Figure 19 shows the method 1900 that various ldpc coded signals are handled provides hardware that is used to.

As shown in square frame 1910, this method 1900 starts from based on all needed all the LDPC matrixes of ldpc coded signal of connectedness identification decoding between each row and other row.

As shown in square frame 1920, this method 1900 then generates the stack result (comprising for instance, the stack of each submatrix position of all LDPC matrixes) of all LDPC matrixes.

As shown in square frame 1930, method 1900 then uses row affine as tolerance, and the first greedy deep search of carrying out stack result is to determine the required memory number and the group (merging patterns for instance) of merging.

As shown in square frame 1940, this method 1900 then provides suitable memory based on merging patterns to each submatrix of stack result.

Figure 20 shows the optional embodiment 2000 of stack LDPC matrix.This embodiment 2000 adopts the decoding processing of 12 codes with execution in IEEE 802.11n standard corresponding to the stack of 12 independent LDPC matrixes.When 12 independent LDPC matrixes are superposeed (and their each submatrix), in the end have 205 non-zero submatrices altogether in the stack LDPC matrix of Chu Xianing.

Message corresponding to each non-zero submatrices can be stored in the memory.Can move verification and bit-engine, they can be suitably and optionally read information or writing information is extracting the suitable non-zero submatrices of each signal specific that can be used for decoding in the memory of operation from the memory of operation like this, and any is encoded in 12 kinds of encoding schemes that these signal specific are used according to IEEE 802.11n standard.

In this embodiment, it is all available at any time having only 88 memories in these 205 memories.In these 205 memories, have at least 117 to be idle always.Significantly, when decoding first code signal, first subclass (88 memories) in these 205 memories can be used, and when decoding second code signal, second subclass (88 memories) in these 205 memories can be used.

Can significantly reduce these 205 amount of memory that provide by the sampling merging patterns, and the first greedy deep search that can pass through to use last stack LDPC matrix adopts the memory of minimum number (may not being in fact really minimum) to determine the quantity of required memory.Such merging patterns have been shown in appendix, and can have obtained this specific merging patterns by using the affine first greedy deep search of row as the last stack LDPC matrix of measuring.These merging patterns only need to provide 102 memories (comparing with 205).It is about 50% that visible memory can be saved, and this also will make adjacent path greatly compress.And in fact, can find a solution, the amount of memory that needs can be less than 102 memories (for instance, use first comprehensive deep search), can find, use 102 memories that provide (for instance, use the first greedy deep search found) have zone balance relatively preferably than and signal congested.

In the decode procedure of signal specific, when specific memory is not used, this memory can be disconnected (remove for instance, and connect) from the remainder with circuit and disturb initiatively computing and can save energy to prevent free storage.The disconnection of this memory can be set to 0 (or maximum " maxval ") to the input of memory by each variable node and check-node and realize, these variable nodes and check-node link to each other with this specific untapped submatrix (zero submatrix) of this particular code that is used to decode respectively.

It should be noted that the many code methods that occur can use on any submatrix/period of the day from 11 p.m. to 1 a.m clock based on the LDPC decoder herein, at this, the message stores of corresponding submatrix/period of the day from 11 p.m. to 1 a.m clock is (SRAM, set of registers etc. for instance) in certain type memory.In addition, when attempting to obtain more effective memory solution, the method for heuristicing of use can be carried out details (backend implementationdetail) according to the rear end and carry out more accurate tuning.In other words, depend on the application-specific that many codes LDPC decoder need be carried out, can heuristic method to this according to this application-specific so and carry out more accurate tuning.

It should be noted that various module described herein (encoder, decoder, processing module etc. for instance) all can be independent treatment facility or a plurality of treatment facility.Such treatment facility can be microprocessor, microcontroller, digital signal processor, micro calculator, CPU, field programmable gate array, programmable logic device, state machine, analog circuit, digital circuit and/or any device according to operational order processing signals (numeral and/or simulation).This memory can be independent memory device or a plurality of memory device.But such memory device can be any memory of read-only memory, random access storage device, static memory, dynamic memory, flash memory and/or storing digital information.Should note, when treatment facility was carried out one or more function by state machine, analog circuit, digital circuit and/or logical circuit, the memory of storage instruction corresponding was implantable in the circuit that comprises this state machine, analog circuit, digital circuit and/or logical circuit.In such an embodiment, the memory stores correspondence is in some step and/or the instruction at least shown in this, and the processing module that links to each other with described memory is carried out these instructions.

More than invention has been described by means of the explanation function of appointment and the method step of relation.For the convenience of describing, boundary and order that these functions are formed module and method step are defined herein specially.Yet, as long as given function and relation can realize suitably that the variation of boundary and order allows.The boundary of any above-mentioned variation or order should be regarded as in the scope of claim protection.

Below also invention has been described by means of the functional module that some critical function is described.For the convenience of describing, the boundary that these functions are formed module is defined herein specially.When these important function are suitably realized, change its boundary and allow.Similarly, flow chart modules is illustrated by special definition herein also and some important function is extensive use that the boundary of flow chart modules and order can be otherwise defined, as long as still can realize these critical functions.The variation of the boundary of above-mentioned functions module, flow chart functional module and order must be regarded as in the claim protection range.

Those skilled in the art also know functional module described herein and other illustrative modules, module and assembly, can combine as example or by the integrated circuit of discrete component, specific function, the processor that has suitable software and similar device.

In addition, though to describe the purpose of details be clear and understand that the foregoing description, the present invention are not limited to these embodiment.That any those skilled in the art know, to these features and embodiment carry out that various changes or equivalence are replaced and technical scheme, all belong to protection scope of the present invention.

Annex is introduced

Can adopt multiple mode and embodiment to generate merging patterns so that providing at the hardware of the equipment of a plurality of ldpc coded signals that are used for decoding to be provided.Possible embodiment relates to that any is decoded in 12 kinds of encoding schemes using according to IEEE 802.11n standard.

In this embodiment, as seen, when sampling merges search, only need 102 memories, and when using simple stacking method, need 205 memories.

Annex (merging patterns)

Do not merge memory, row 0 row 0, coding 0 (0,0), coding 1 (0,0), coding 2 (0,0), coding 3 (0,0), coding 4 (0,0), coding 5 (0,0), coding 6 (0,0), coding 7 (0,0), coding 8 (0,0), coding 9 (0,0), coding 10 (0,0), coding 11 (0,0)

Do not merge memory, row 0 row 2, coding 1 (0,2), coding 2 (0,2), coding 3 (0,2), coding 4 (0,2), coding 5 (0,2), coding 6 (0,2), coding 7 (0,2), coding 8 (0,2), coding 9 (0,2), coding 10 (0,2), coding 11 (0,2)

Do not merge memory, row 0 row 3, coding 1 (0,3), coding 2 (0,3), coding 3 (0,3), coding 5 (0,3), coding 6 (0,3), coding 7 (0,3), coding 9 (0,3), coding 10 (0,3), coding 11 (0,3)

Do not merge memory, row 0 row 4, coding 0 (0,4), coding 2 (0,4), coding 3 (0,4), coding 4 (0,4), coding 5 (0,4), coding 6 (0,4), coding 7 (0,4), coding 8 (0,4), coding 9 (0,4), coding 10 (0,4), coding 11 (0,4)

Do not merge memory, row 0 row 7, coding 0 (0,7), coding 1 (0,7), coding 2 (0,7), coding 3 (0,7), coding 7 (0,7), coding 8 (0,7), coding 9 (0,7), coding 10 (0,7), coding 11 (0,7)

Do not merge memory, row 0 row 8, coding 0 (0,8), coding 3 (0,8), coding 4 (0,8), coding 5 (0,8), coding 6 (0,8), coding 7 (0,8), coding 8 (0,8), coding 9 (0,8), coding 11 (0,8)

Do not merge memory, row 0 row 23, coding 0 (0,23), coding 1 (0,23), coding 2 (0,23), coding 3 (0,23), coding 4 (0,23), coding 5 (0,23), coding 6 (0,23), coding 7 (0,23), coding 8 (0,23), coding 9 (0,23), coding 10 (0,23), coding 11 (0,23)

Do not merge memory, row 1 row 0, coding 0 (1,0), coding 1 (1,0), coding 2 (1,0), coding 3 (1,0), coding 5 (1,0), coding 6 (1,0), coding 7 (1,0), coding 8 (1,0), coding 9 (1,0), coding 10 (1,0), coding 11 (1,0)

Do not merge memory, row 1 row 1, coding 1 (1,1), coding 2 (1,1), coding 3 (1,1), coding 4 (1,1), coding 5 (1,1), coding 6 (1,1), coding 7 (1,1), coding 8 (1,1), coding 9 (1,1), coding 10 (1,1), coding 11 (1,1)

Do not merge memory, row 1 row 2, coding 0 (1,2), coding 1 (1,2), coding 2 (1,2), coding 3 (1,2), coding 5 (1,2), coding 6 (1,2), coding 7 (1,2), coding 9 (1,2), coding 10 (1,2), coding 11 (1,2)

Do not merge memory, row 1 row 4, coding 0 (1,4), coding 1 (1,4), coding 2 (1,4), coding 3 (1,4), the coding 4 (1,4), the coding 5 (1,4), the coding 6 (1,4), the coding 7 (1,4), coding 8 (1,4), coding 9 (1,4), coding 10 (1,4), coding 11 (1,4)

Do not merge memory, row 1 row 5, coding 0 (1,5), coding 3 (1,5), coding 6 (1,5), coding 7 (1,5), coding 9 (1,5), coding 10 (1,5), coding 11 (1,5)

Do not merge memory, row 1 row 7, coding 0 (1,7), coding 2 (1,7), coding 3 (1,7), coding 4 (1,7), coding 5 (1,7), coding 6 (1,7), coding 7 (1,7), coding 9 (1,7), coding 10 (1,7), coding 11 (1,7)

Do not merge memory, row 1 row 8, coding 0 (1,8), coding 1 (1,8), coding 2 (1,8), coding 3 (1,8), coding 4 (1,8), coding 7 (1,8), coding 10 (1,8), coding 11 (1,8)

Do not merge memory, row 1 row 22, coding 0 (1,22), coding 1 (1,22), coding 2 (1,22), coding 3 (1,22), coding 4 (1,22), coding 5 (1,22), coding 6 (1,22), coding 7 (1,22), coding 8 (1,22), coding 9 (1,22), coding 10 (1,22), coding 11 (1,22)

Do not merge memory, row 1 row 23, coding 0 (1,23), coding 1 (1,23), coding 2 (1,23), coding 3 (1,23), coding 4 (1,23), coding 5 (1,23), coding 6 (1,23), coding 7 (1,23), coding 8 (1,23), coding 9 (1,23), coding 10 (1,23), coding 11 (1,23)

Do not merge memory, row 2 row 0, coding 0 (2,0), coding 1 (2,0), coding 2 (2,0), coding 3 (2,0), coding 4 (2,0), coding 5 (2,0), coding 6 (2,0), coding 7 (2,0), coding 9 (2,0), coding 10 (2,0), coding 11 (2,0)

Do not merge memory, row 2 row 1, coding 1 (2,1), coding 2 (2,1), coding 3 (2,1), coding 5 (2,1), coding 6 (2,1), coding 7 (2,1), coding 8 (2,1), coding 9 (2,1), coding 10 (2,1), coding 11 (2,1)

Do not merge memory, row 2 row 2, coding 1 (2,2), coding 2 (2,2), coding 3 (2,2), coding 4 (2,2), coding 5 (2,2), coding 6 (2,2), coding 7 (2,2), coding 9 (2,2), coding 10 (2,2), coding 11 (2,2)

Do not merge memory, row 2 row 3, coding 1 (2,3), coding 2 (2,3), coding 3 (2,3), coding 5 (2,3), coding 6 (2,3), coding 7 (2,3), coding 8 (2,3), coding 9 (2,3), coding 10 (2,3), coding 11 (2,3)

Do not merge memory, row 2 row 4, coding 0 (2,4), coding 2 (2,4), coding 3 (2,4), coding 4 (2,4), coding 5 (2,4), coding 6 (2,4), coding 7 (2,4), coding 8 (2,4), coding 9 (2,4), coding 10 (2,4), coding 11 (2,4)

Do not merge memory, row 2 row 8, coding 0 (2,8), coding 2 (2,8), coding 3 (2,8), coding 4 (2,8), coding 6 (2,8), coding 7 (2,8), coding 8 (2,8), coding 10 (2,8), coding 11 (2,8)

Do not merge memory, row 2 row 21, coding 0 (2,21), coding 1 (2,21), coding 2 (2,21), coding 3 (2,21), coding 4 (2,21), coding 5 (2,21), coding 6 (2,21), coding 7 (2,21), coding 8 (2,21), coding 9 (2,21), coding 10 (2,21), coding 11 (2,21)

Do not merge memory, row 2 row 22, coding 0 (2,22), coding 1 (2,22), coding 2 (2,22), coding 3 (2,22), coding 4 (2,22), coding 5 (2,22), coding 6 (2,22), coding 7 (2,22), coding 8 (2,22), coding 9 (2,22), coding 10 (2,22), coding 11 (2,22)

Do not merge memory, row 3 row 0, coding 0 (3,0), coding 1 (3,0), coding 2 (3,0), coding 3 (3,0), coding 4 (3,0), coding 5 (3,0), coding 6 (3,0), coding 7 (3,0), coding 8 (3,0), coding 9 (3,0), coding 10 (3,0), coding 11 (3,0)

Do not merge memory, row 3 row 1, coding 0 (3,1), coding 1 (3,1), coding 2 (3,1), coding 3 (3,1), coding 5 (3,1), coding 6 (3,1), coding 7 (3,1), coding 9 (3,1), coding 10 (3,1), coding 11 (3,1)

Do not merge memory, row 3 row 2, coding 1 (3,2), coding 2 (3,2), coding 3 (3,2), coding 5 (3,2), coding 6 (3,2), coding 7 (3,2), coding 9 (3,2), coding 10 (3,2), coding 11 (3,2)

Do not merge memory, row 3 row 3, coding 0 (3,3), coding 2 (3,3), coding 3 (3,3), coding 4 (3,3), coding 5 (3,3), coding 6 (3,3), coding 7 (3,3), coding 9 (3,3), coding 10 (3,3), coding 11 (3,3)

Do not merge memory, row 3 row 4, coding 0 (3,4), coding 1 (3,4), coding 2 (3,4), coding 3 (3,4), coding 4 (3,4), coding 5 (3,4), coding 6 (3,4), coding 7 (3,4), coding 8 (3,4), coding 10 (3,4), coding 11 (3,4)

Do not merge memory, row 3 row 5, coding 0 (3,5), coding 2 (3,5), coding 3 (3,5), coding 5 (3,5), coding 6 (3,5), coding 7 (3,5), coding 8 (3,5), coding 9 (3,5), coding 10 (3,5), coding 11 (3,5)

Do not merge memory, row 3 row 8, coding 0 (3,8), coding 1 (3,8), coding 2 (3,8), coding 3 (3,8), coding 4 (3,8), coding 7 (3,8), coding 8 (3,8), coding 9 (3,8), coding 10 (3,8), coding 11 (3,8)

Do not merge memory, row 3 row 20, coding 0 (3,20), coding 1 (3,20), coding 2 (3,20), coding 3 (3,20), coding 4 (3,20), coding 5 (3,20), coding 6 (3,20), coding 7 (3,20), coding 8 (3,20), coding 9 (3,20), coding 10 (3,20), coding 11 (3,20)

Do not merge memory, row 3 row 21, coding 0 (3,21), coding 1 (3,21), coding 2 (3,21), coding 3 (3,21), coding 4 (3,21), coding 5 (3,21), coding 6 (3,21), coding 7 (3,21), coding 8 (3,21), coding 9 (3,21), coding 10 (3,21), coding 11 (3,21)

Do not merge memory, row 4 row 1, coding 0 (4,1), coding 1 (4,1), coding 2 (4,1), coding 3 (4,1), coding 5 (4,1), coding 6 (4,1), coding 7 (4,1), coding 9 (4,1), coding 10 (4,1), coding 11 (4,1)

Do not merge memory, row 4 row 2, coding 1 (4,2), coding 2 (4,2), coding 3 (4,2), coding 4 (4,2), coding 5 (4,2), coding 6 (4,2), coding 7 (4,2), coding 9 (4,2), coding 10 (4,2), coding 11 (4,2)

Do not merge memory, row 4 row 3, coding 1 (4,3), coding 2 (4,3), coding 3 (4,3), coding 6 (4,3), coding 7 (4,3), coding 9 (4,3), coding 10 (4,3), coding 11 (4,3)

Do not merge memory, row 4 row 4, coding 0 (4,4), coding 2 (4,4), coding 3 (4,4), coding 4 (4,4), coding 5 (4,4), coding 6 (4,4), coding 7 (4,4), coding 8 (4,4), coding 9 (4,4), coding 10 (4,4), coding 11 (4,4)

Do not merge memory, row 4 row 5, coding 1 (4,5), coding 2 (4,5), coding 3 (4,5), coding 5 (4,5), coding 6 (4,5), coding 7 (4,5), coding 8 (4,5), coding 10 (4,5), coding 11 (4,5)

Do not merge memory, row 5 row 0, coding 0 (5,0), coding 1 (5,0), coding 2 (5,0), coding 3 (5,0), coding 4 (5,0), coding 5 (5,0), coding 6 (5,0), coding 7 (5,0), coding 8 (5,0), coding 9 (5,0), coding 10 (5,0), coding 11 (5,0)

Do not merge memory, row 5 row 1, coding 1 (5,1), coding 2 (5,1), coding 3 (5,1), coding 4 (5,1), coding 5 (5,1), coding 6 (5,1), coding 7 (5,1), coding 8 (5,1), coding 9 (5,1), coding 10 (5,1), coding 11 (5,1)

Do not merge memory, row 5 row 2, coding 1 (5,2), coding 2 (5,2), coding 3 (5,2), coding 5 (5,2), coding 6 (5,2), coding 7 (5,2), coding 8 (5,2), coding 9 (5,2), coding 10 (5,2), coding 11 (5,2)

Do not merge memory, row 5 row 4, coding 0 (5,4), coding 1 (5,4), coding 2 (5,4), coding 3 (5,4), coding 5 (5,4), coding 6 (5,4), coding 7 (5,4), coding 9 (5,4), coding 10 (5,4), coding 11 (5,4)

Do not merge memory, row 5 row 6, coding 1 (5,6), coding 2 (5,6), coding 3 (5,6), coding 5 (5,6), coding 6 (5,6), coding 7 (5,6), coding 8 (5,6), coding 9 (5,6), coding 11 (5,6)

Do not merge memory, row 5 row 8, coding 0 (5,8), coding 1 (5,8), coding 2 (5,8), coding 3 (5,8), coding 4 (5,8), coding 7 (5,8), coding 8 (5,8), coding 11 (5,8)

Merge memory, coding 0 (11,8), coding 1 (2,5), coding 3 (2,5), coding 4 (11,8), coding 6 (2,5), coding 7 (2,5), coding 8 (11,8), coding 10 (2,5), coding 11 (2,5)

Merge memory, coding 0 (8,3), coding 1 (1,3), coding 2 (1,3), coding 3 (1,3), the coding 4 (8,3),, the coding 5 (1,3), the coding 6 (1,3), the coding 7 (1,3), coding 8 (1,3), coding 9 (1,3), coding 10 (1,3), coding 11 (1,3)

Merge memory, coding 0 (4,19), coding 1 (4,19), coding 2 (4,19), coding 3 (3,19), coding 4 (4,19), coding 5 (4,19), coding 6 (4,19), coding 7 (3,19), coding 8 (4,19), coding 9 (4,19), coding 10 (4,19)

Merge memory, coding 0 (10,0), coding 1 (7,2), coding 2 (4,17), coding 3 (3,17), coding 4 (10,0), coding 5 (7,2), coding 6 (3,17), coding 8 (10,0), coding 9 (7,2), coding 10 (3,17), coding 11 (3,17)

Merge memory, coding 0 (9,0), coding 1 (6,1), coding 3 (0,20), coding 4 (9,0), coding 5 (6,1), coding 6 (5,7), coding 7 (0,20), coding 8 (9,0), coding 9 (6,1), coding 10 (4,11), coding 11 (0,20)

Merge memory, coding 0 (6,18), coding 1 (6,18), coding 2 (2,18), coding 3 (2,18), coding 4 (6,18), coding 5 (6,18), coding 6 (2,18), coding 7 (2,18), coding 8 (6,18), coding 9 (6,18), coding 10 (2,18), coding 11 (2,18)

Merge memory, coding 0 (4,20), coding 1 (4,20), coding 2 (4,20), coding 3 (1,20), coding 4 (4,20), coding 5 (4,20), coding 6 (4,20), coding 7 (1,20), coding 8 (4,20), coding 9 (4,20), coding 10 (4,20), coding 11 (1,20)

Merge memory, coding 0 (7,0), coding 1 (7,0), coding 2 (0,18), coding 3 (0,18), coding 4 (7,0), coding 5 (7,0), coding 6 (0,18), coding 8 (7,0), coding 9 (7,0), coding 10 (0,18), coding 11 (0,18)

Merge memory, coding 0 (11,13), coding 1 (7,13), coding 3 (3,13), coding 4 (11,13), coding 6 (3,13), coding 7 (3,13), coding 8 (11,13), coding 9 (7,13), coding 10 (3,13), coding 11 (3,13)

Merge memory, coding 0 (8,0), coding 1 (7,1), coding 2 (2,16), coding 3 (2,16), coding 4 (8,0), coding 5 (7,1), coding 6 (2,16), coding 7 (2,16), coding 8 (8,0), coding 9 (7,1), coding 10 (2,16), coding 11 (2,16)

Merge memory, coding 0 (11,0), coding 1 (5,3), coding 2 (5,3), coding 3 (2,19), coding 4 (11,0), coding 5 (5,3), coding 6 (5,3), coding 8 (11,0), coding 9 (5,3), coding 10 (5,3), coding 11 (2,19)

Merge memory, coding 0 (6,17), coding 1 (6,17), coding 3 (2,17), coding 4 (6,17), coding 5 (6,17), coding 6 (4,16), coding 7 (2,17), coding 8 (6,17), coding 9 (6,17), coding 10 (2,17), coding 11 (2,17)

Merge memory, coding 0 (4,0), coding 1 (4,0), coding 2 (4,0), coding 3 (1,19), coding 4 (4,0), coding 5 (4,0), coding 6 (4,0), coding 7 (1,19), coding 8 (4,0), coding 9 (4,0), coding 10 (4,0), coding 11 (1,19)

Merge memory, coding 0 (8,16), coding 1 (0,16), coding 2 (5,16), coding 3 (0,16), coding 4 (8,16), coding 5 (0,16), coding 6 (0,16), coding 7 (0,16), coding 8 (8,16), coding 9 (0,16), coding 10 (5,16), coding 11 (0,16)

Merge memory, coding 0 (5,19), coding 1 (5,19), coding 2 (5,19), coding 3 (0,19), coding 4 (5,19), coding 5 (5,19), coding 6 (5,19), coding 7 (0,19), coding 8 (5,19), coding 9 (5,19), coding 10 (5,19), coding 11 (0,19)

Merge memory, coding 0 (7,17), coding 1 (7,17), coding 2 (1,17), coding 3 (1,17), coding 4 (7,17), coding 5 (7,17), coding 6 (1,17), coding 7 (1,17), coding 8 (7,17), coding 9 (7,17), coding 11 (1,17)

Merge memory, coding 0 (5,12), coding 1 (6,5), coding 2 (5,12), coding 3 (2,12), coding 4 (5,12), coding 5 (5,12), coding 6 (2,12), coding 7 (2,12), coding 8 (5,12), coding 9 (2,12), coding 10 (2,12), coding 11 (2,12)

Merge memory, coding 0 (9,15), coding 1 (7,15), coding 3 (2,15), coding 4 (9,15), coding 5 (7,15), coding 6 (5,15), coding 7 (2,15), coding 8 (9,15), coding 9 (7,15), coding 10 (5,15), coding 11 (2,15)

Merge memory, coding 0 (11,12), coding 1 (7,6), the coding 2 (4,12), the coding 3 (3,1S), the coding 4 (11,12), coding 5 (7,6), coding 6 (4,12), coding 7 (3,18), coding 8 (11,12), coding 9 (4,12), coding 10 (4,12), coding 11 (3,18)

Merge memory, coding 0 (8,15), coding 1 (4,15), coding 2 (3,15), coding 3 (3,15), coding 4 (8,15), coding 6 (3,15), coding 7 (3,15), coding 8 (8,15), coding 9 (6,9), coding 10 (4,15), coding 11 (3,15)

Merge memory, coding 0 (9,2), coding 1 (6,12), coding 4 (9,1), coding 5 (6,12), coding 6 (5,13), coding 7 (1,12), coding 8 (10,2), coding 9 (6,12), coding 10 (1,12), coding 11 (1,12)

Merge memory, coding 0 (6,0), coding 1 (6,0), coding 2 (0,17), coding 3 (0,17), coding 4 (6,0), coding 5 (6,0), coding 6 (5,17), coding 7 (0,17), coding 8 (6,0), coding 9 (6,0), coding 10 (5,17)

Merge memory, coding 0 (8,4), coding 1 (3,12), coding 2 (3,12), coding 3 (3,12), coding 4 (8,4), coding 5 (3,12), coding 7 (3,12), coding 8 (8,4), coding 9 (7,14)

Merge memory, coding 0 (9,4), coding 1 (1,15), coding 2 (1,15), coding 3 (1,15), coding 4 (9,4), coding 5 (1,15), coding 6 (1,15), coding 7 (1,19), coding 8 (9,4), the coding 9 (1,15), the coding 11 (1,15)

Merge memory, coding 0 (0,12), coding 1 (0,12), coding 2 (5,10), coding 3 (0,12), coding 4 (0,12), coding 6 (0,12), coding 7 (0,12), coding 8 (0,12), coding 9 (5,10), coding 10 (5,10), coding 11 (0,12)

Merge memory, coding 0 (10,4), coding 2 (0,15), coding 3 (0,15), coding 4 (10,4), coding 5 (0,15), coding 7 (0,15), coding 8 (10,4), coding 9 (0,15), coding 10 (0,15)

Merge memory, coding 0 (5,18), coding 1 (5,18), coding 2 (5,18), coding 3 (1,18), coding 4 (5,18), coding 5 (5,18), coding 6 (5,18), coding 7 (1,18), coding 8 (5,18), coding 9 (5,18), coding 10 (5,18)

Merge memory, coding 0 (10,13), coding 1 (6,7), coding 2 (1,13), coding 3 (1,13), coding 4 (10,13), coding 5 (1,13), coding 6 (1,13), coding 7 (1,13), coding 8 (10,13), coding 9 (6,7), coding 11 (1,13)

Merge memory, coding 0 (7,16), coding 1 (7,16), coding 3 (1,16), coding 4 (7,16), coding 5 (7,16), coding 8 (7,16), coding 9 (7,16), coding 10 (1,16)

Merge memory, coding 0 (11,4), coding 1 (2,13), coding 2 (2,13), coding 3 (2,13), coding 4 (11,4), coding 5 (2,13), coding 7 (2,13), coding 8 (11,4), coding 9 (2,13)

Merge memory, coding 0 (9,8), coding 1 (3,16), coding 2 (3,16), coding 3 (3,16), coding 4 (10,5), coding 5 (3,16), coding 7 (3,16), coding 8 (9,8), coding 9 (3,16), coding 11 (3,16)

Merge memory, coding 0 (10,1), coding 1 (4,13), coding 3 (3,7), coding 4 (10,1), coding 5 (4,13), coding 6 (3,7), coding 7 (3,7), coding 8 (8,1), coding 9 (4,13), coding 10 (4,13), coding 11 (3,7)

Merge memory, coding 0 (10,14), coding 1 (6,14), coding 3 (2,14), coding 4 (10,1), coding 5 (6,14), coding 6 (2,14), coding 7 (2,14), coding 8 (10,14), coding 9 (2,14), coding 11 (2,14)

Merge memory, coding 0 (11,11), coding 1 (4,7), coding 2 (4,7), coding 3 (3,11), coding 4 (3,11), coding 5 (4,7), coding 6 (3,11), coding 7 (3,11), coding 8 (3,11), coding 9 (3,11), coding 11 (3,11)

Merge memory, coding 0 (9,14), coding 2 (4,14), coding 3 (1,14), coding 4 (9,14), coding 5 (4,14), coding 6 (4,14), coding 7 (1,14), coding 8 (9,14), coding 10 (1,14)

Merge memory, coding 0 (2,11), coding 1 (2,11), coding 2 (2,11), coding 3 (2,11), coding 4 (9,11), coding 5 (2,11), coding 7 (2,11), coding 8 (6,11)

Merge memory, coding 0 (11,5), coding 1 (0,14), coding 2 (5,14), coding 3 (0,14), the coding 4 (9,6),, the coding 5 (5,14), the coding 6 (0,14), the coding 7 (0,14), coding 8 (9,5), coding 9 (5,14), coding 10 (0,14), coding 11 (0,14)

Merge memory, coding 0 (7,11), coding 1 (7,11), coding 2 (0,13), coding 3 (0,13), coding 4 (11,6), coding 5 (7,11), coding 7 (0,13), coding 8 (11,6), coding 9 (7,11), coding 10 (0,13), coding 11 (0,13)

Merge memory, coding 0 (6,4), coding 1 (3,14), coding 2 (3,14), coding 3 (3,14), coding 4 (6,4), coding 5 (6,4), coding 7 (3,14), coding 8 (6,4), coding 10 (3,14), coding 11 (3,14)

Merge memory, coding 0 (10,6), coding 1 (5,11), coding 2 (3,10), coding 3 (3,10), coding 4 (11,7), coding 5 (7,3), coding 6 (5,11), coding 7 (3,10), coding 8 (7,3), coding 9 (7,3), coding 10 (5,11), coding 11 (3,10)

Merge memory, coding 0 (7,10), coding 1 (6,10), coding 3 (0,10), coding 4 (6,10), coding 6 (0,10), coding 7 (0,10), coding 8 (11,10), coding 9 (6,10)

Merge memory, coding 0 (10,7), coding 2 (1,11), coding 3 (1,11), coding 4 (7,5), coding 5 (7,5), coding 6 (1,11), coding 7 (1,11), coding 8 (7,7), coding 9 (1,11), coding 11 (1,11)

Merge memory, coding 0 (2,10), coding 2 (2,10), coding 3 (2,10), coding 4 (2,10), coding 5 (2,10), coding 6 (2,10), coding 7 (2,10), coding 8 (10,9), coding 11 (2,10)

Merge memory, coding 0 (8,9), coding 2 (0,11), coding 3 (0,11), coding 4 (0,11), coding 5 (0,11), coding 7 (0,11), coding 8 (0,11), coding 10 (0,11), coding 11 (0,11)

Merge memory, coding 0 (9,10), coding 1 (4,10), coding 2 (4,10), coding 4 (10,10), coding 5 (4,10), coding 6 (4,10), coding 8 (4,10), coding 9 (4,10), coding 10 (4,10)

Merge memory, coding 0 (5,9), coding 1 (5,9), coding 2 (5,9), coding 4 (7,9), coding 5 (5,9), coding 6 (5,9), coding 8 (9,9), coding 10 (5,9)

Merge memory, coding 0 (4,6), coding 1 (1,10), coding 2 (4,6), coding 3 (1,10), coding 4 (4,6), coding 5 (1,10), coding 6 (4,6), coding 7 (1,10), coding 8 (1,10), coding 10 (1,10), coding 11 (1,10)

Merge memory, coding 0 (0,9), coding 1 (0,9), coding 2 (0,9), coding 3 (0,9), coding 4 (8,7), coding 5 (0,9), coding 7 (0,9), coding 8 (8,7), coding 9 (0,9), coding 11 (0,9)

Merge memory, coding 0 (6,6), coding 1 (1,6), coding 2 (4,9), coding 3 (1,6), coding 4 (4,9), coding 5 (6,6), coding 6 (1,6), coding 7 (1,6), coding 8 (6,6), coding 9 (4,9), coding 10 (4,9), coding 11 (1,6)

Merge memory, coding 0 (6,2), coding 1 (6,2), coding 2 (1,9), coding 3 (1,9), coding 4 (1,9), coding 5 (6,2), coding 6 (1,9), coding 7 (1,9), coding 9 (6,2), coding 11 (1,9)

Merge memory, coding 0 (8,8), coding 1 (3,6), coding 2 (3,6), coding 3 (3,6), coding 4 (8,8), coding 6 (3,6), coding 7 (3,6), coding 8 (8,8), coding 9 (3,6), coding 10 (3,6), coding 11 (3,6)

Merge memory, coding 1 (2,9), coding 2 (5,5), coding 3 (2,9), coding 4 (5,5), coding 6 (5,5), coding 7 (2,9), coding 8 (2,9), coding 9 (5,5), coding 10 (5,5),, coding 11 (2,9)

Merge memory, coding 0 (6,3), coding 1 (6,3), coding 2 (0,6), coding 3 (0,6), coding 4 (6,3), coding 5 (6,3), coding 6 (0,6), coding 7 (0,6), coding 9 (6,3), coding 10 (0,6), coding 11 (0,6)

Merge memory, coding 0 (4,8), coding 1 (2,7), coding 2 (2,7), coding 3 (2,7), coding 4 (4,8), coding 5 (2,7), coding 6 (4,8), coding 7 (2,7), coding 8 (4,8), coding 10 (2,7), coding 11 (2,7)

Merge memory, coding 0 (7,8), coding 1 (7,8), coding 3 (2,6), coding 4 (7,8), coding 5 (7,8), coding 6 (2,6), coding 7 (2,6), coding 8 (7,8), coding 9 (2,6), coding 11 (2,6), coding 10 (2,6)

Merge memory, coding 0 (7,4), coding 1 (7,4), coding 3 (3,9), coding 4 (7,4), coding 5 (3,9), coding 6 (3,9), coding 7 (3,9), coding 8 (7,4), coding 9 (7,4), coding 10 (3,9), coding 11 (3,9)

Merge memory, coding 0 (6,8), coding 1 (0,5), coding 2 (0,5), coding 3 (0,5), coding 4 (6,8), coding 5 (6,8), coding 6 (0,5), coding 7 (0,5), coding 8 (6,8), coding 9 (6,8), coding 10 (0,5), coding 11 (0,5)

Merge memory, coding 0 (10,8), coding 1 (0,1), coding 2 (0,1), coding 3 (0,1), coding 4 (10,8), coding 5 (0,1), coding 6 (0,1), coding 7 (0,1), coding 8 (10,8), the coding 9 (0,1), the coding 10 (0,1), the coding 11 (0,1)

Claims

1. a decoder is used to the low density odd-even check coded signal of decoding, and it is characterized in that, described decoder comprises:

A plurality of memories;

A plurality of multiplexers are used for:

In the decoding process of first low density odd-even check coded signal, optionally described a plurality of bit-engine and described a plurality of verification engine are connected to first word-select memory in described a plurality of memory;

And

In the decoding process of second low density odd-even check coded signal, optionally described a plurality of bit-engine and described a plurality of verification engine are connected to second word-select memory in described a plurality of memory; And wherein:

Described a plurality of memory comprises the memory of predetermined quantity, and the memory of described predetermined quantity is used for representing a plurality of non-zero submatrices of a plurality of low-density parity check (LDPC) matrixes of corresponding a plurality of low-density checksum codings;

Described decoder described first low density odd-even check coded signal that is used to decode, described first low density odd-even check coded signal is corresponding to first low-density parity check (LDPC) matrix of described a plurality of low-density parity check (LDPC) matrixes, wherein, bit-engine and verification engine are carried out iterative decoding and are handled up to satisfying stopping criterion, after satisfying stopping criterion, bit-engine generates soft information, thereby is created on the best estimate of the bit that is encoded in first low density odd-even check coded signal; And

Described decoder described second low density odd-even check coded signal that is used to decode, described second low density odd-even check coded signal is corresponding to second low-density parity check (LDPC) matrix of described a plurality of low-density parity check (LDPC) matrixes, wherein, bit-engine and verification engine are carried out iterative decoding and are handled up to satisfying stopping criterion, after satisfying stopping criterion, bit-engine generates soft information, thereby is created on the best estimate of the bit that is encoded in second low density odd-even check coded signal.

2. decoder according to claim 1 is characterized in that, by a plurality of non-zero submatrices in a plurality of low-density parity check (LDPC) matrixes of the corresponding a plurality of low-density checksum codings that superpose each other, determines a part of memory in described a plurality of memory.

3. decoder according to claim 1, it is characterized in that, by first greed, deep search are carried out in the stack of a plurality of non-zero submatrices in a plurality of low-density parity check (LDPC) matrixes of a plurality of low-density checksum codings of correspondence, determine a part of memory in described a plurality of memory.

4. decoder according to claim 1, it is characterized in that, by first greed, deep search are carried out in the stack of a plurality of non-zero submatrices in a plurality of low-density parity check (LDPC) matrixes of a plurality of low-density checksum codings of correspondence, determine a part of memory in described a plurality of memory; And

Described first greed, deep search to small part is considered the affine tolerance of row, and the affine tolerance of described row is represented the row in described first low-density parity check (LDPC) matrix and the connectedness of another row at least in described first low-density parity check (LDPC) matrix and the row in described second low-density parity check (LDPC) matrix.

5. decoder according to claim 1, it is characterized in that, the layout of a plurality of memories in the described communication equipment is based on merging patterns, by considering that to small part the affine tolerance of row generates described merging patterns, the affine tolerance of described row is represented the row in described first low-density parity check (LDPC) matrix and the connectedness of another row at least in described first low-density parity check (LDPC) matrix and the row in described second low-density parity check (LDPC) matrix.

6. decoder according to claim 1, it is characterized in that, described a plurality of memory comprises a plurality of merging memories, first non-zero submatrices in corresponding described first low-density parity check (LDPC) matrix of a merging memory in described a plurality of merging memory, second non-zero submatrices in also corresponding described second low-density parity check (LDPC) matrix.

7. a decoder is used to the low density odd-even check coded signal of decoding, and it is characterized in that, described decoder comprises:

A plurality of memories;

A plurality of multiplexers are used for:

When decoding during first low density odd-even check coded signal, in the process that bit node is handled, the selected bit-engine of first in described a plurality of bit-engine is connected to first word-select memory in described a plurality of memory;

When described first low density odd-even check coded signal of decoding, in the process of code check node processing, the selected verification engine of first in described a plurality of verification engines is connected to described first word-select memory in described a plurality of memory;

When decoding during second low density odd-even check coded signal, in the process that bit node is handled, the selected bit-engine of second in described a plurality of bit-engine is connected to second word-select memory in described a plurality of memory; And

When described second low density odd-even check coded signal of decoding, in the process of code check node processing, the selected verification engine of second in described a plurality of verification engines is connected to described second word-select memory in described a plurality of memory; Wherein:

Described a plurality of memory comprises the memory of predetermined quantity, and the memory of described predetermined quantity is used for representing a plurality of non-zero submatrices of a plurality of low-density parity check (LDPC) matrixes of corresponding a plurality of low-density checksum codings; ,

Described decoder first low density odd-even check coded signal that is used to decode, described first low density odd-even check coded signal is corresponding to first low-density parity check (LDPC) matrix of described a plurality of low-density parity check (LDPC) matrixes, wherein, bit-engine and verification engine are carried out iterative decoding and are handled up to satisfying stopping criterion, after satisfying stopping criterion, bit-engine generates soft information, thereby is created on the best estimate of the bit that is encoded in first low density odd-even check coded signal; And

Described decoder second low density odd-even check coded signal that is used to decode, described second low density odd-even check coded signal is corresponding to second low-density parity check (LDPC) matrix of described a plurality of low-density parity check (LDPC) matrixes, wherein, bit-engine and verification engine are carried out iterative decoding and are handled up to satisfying stopping criterion, after satisfying stopping criterion, bit-engine generates soft information, thereby is created on the best estimate of the bit that is encoded in second low density odd-even check coded signal.

8. decoder according to claim 7 is characterized in that, the described first selected bit-engine of described a plurality of bit-engine is described second selected bit-engine of described a plurality of bit-engine; And

9. decoder according to claim 7 is characterized in that, the described first selected bit-engine of described a plurality of bit-engine is all bit-engine of described a plurality of bit-engine; And

10. a decoder is used to the low density odd-even check coded signal of decoding, and it is characterized in that, described decoder comprises:

A plurality of memories;

A plurality of multiplexers are used for:

When decoding during first low density odd-even check coded signal, in the process that bit node is handled, described a plurality of bit-engine are connected to first word-select memory in described a plurality of memory;

When described first low density odd-even check coded signal of decoding, in the process of code check node processing, described a plurality of verification engines are connected to described first word-select memory in described a plurality of memory;

When decoding during second low density odd-even check coded signal, in the process that bit node is handled, described a plurality of bit-engine are connected to second word-select memory in described a plurality of memory;

When described second low density odd-even check coded signal of decoding, in the process of code check node processing, described a plurality of verification engines are connected to described second word-select memory in described a plurality of memory;

When decoding during the 3rd low density odd-even check coded signal, in the process that bit node is handled, described a plurality of bit-engine are connected to the 3rd word-select memory in described a plurality of memory; And

When described the 3rd low density odd-even check coded signal of decoding, in the process of code check node processing, described a plurality of verification engines are connected to described the 3rd word-select memory in described a plurality of memory; Wherein:

Described decoder described first low density odd-even check coded signal that is used to decode, described first low density odd-even check coded signal is corresponding to first low-density parity check (LDPC) matrix of described a plurality of low-density parity check (LDPC) matrixes, wherein, bit-engine and verification engine are carried out iterative decoding and are handled up to satisfying stopping criterion, after satisfying stopping criterion, bit-engine generates soft information, thereby is created on the best estimate of the bit that is encoded in first low density odd-even check coded signal;

Described decoder described second low density odd-even check coded signal that is used to decode, described second low density odd-even check coded signal is corresponding to second low-density parity check (LDPC) matrix of described a plurality of low-density parity check (LDPC) matrixes, wherein, bit-engine and verification engine are carried out iterative decoding and are handled up to satisfying stopping criterion, after satisfying stopping criterion, bit-engine generates soft information, thereby is created on the best estimate of the bit that is encoded in second low density odd-even check coded signal; And

Described decoder described the 3rd low density odd-even check coded signal that is used to decode, described the 3rd low density odd-even check coded signal is corresponding to the 3rd low-density parity check (LDPC) matrix of described a plurality of low-density parity check (LDPC) matrixes, wherein, bit-engine and verification engine are carried out iterative decoding and are handled up to satisfying stopping criterion, after satisfying stopping criterion, bit-engine generates soft information, thereby is created on the best estimate of the bit that is encoded in the 3rd low density odd-even check coded signal.