TWI407703B - Multi-code ldpc (low density parity check) decoder - Google Patents

Abstract

A decoder for decoding low density parity check coding signal is provided to perform a decoding by a minimum hardware by selecting a plurality of bit engines and check engines by a multiplexer. Each bit engine of a plurality of bit engines(931, 932) is coupled in at least one or more memory among a plurality of memories(811, 812, 813). Each check engine of a plurality of check engines(921, 922) is coupled in at least one or more memory among a plurality of memories. A plurality of multiplexers (991, 992) selectively connects a plurality of bit engines and a plurality of check engines to first selected memories for decoding processing of a first LDPC(Low Density Parity Check) coding signal. A plurality of multiplexers selectively connects a plurality of bit engines and a plurality of check engines to second selected memories for the decoding processing of a second LDPC coding signal.

Description

decoder

The present invention relates to communication systems, and more particularly to a decoding technique for Low Density Parity Check (LDPC) coded signals in a communication system.

The data communication system has been continuously developed for many years. In recent years, the communication system using the iterative error correction code has been the focus of researchers. The most interesting of these is the communication system using LDPC codes. In the case of the same signal to noise ratio, the bit error rate of a communication system using stacked codes is generally lower than that of a communication system using other codes.

A continuing and major development in this area is to reduce the signal-to-noise ratio in communication systems to achieve a specific bit error rate. The ideal goal is to try to study the Shannon’s limit in the communication channel. The Shannon limit can be seen as the data transmission rate used in the channel with a specific signal-to-noise ratio, through which the error-free transmission can be realized. In other words, the Shannon limit is the theoretical limit of channel capacity for a given modulation and coding rate.

The LDPC code has been proven to provide very good decoding performance close to the Shannon limit in some cases. In theory, some LDPC decoders have been shown to achieve a performance of 0.3 dB from the Shannon limit. This performance has been achieved with an irregular LDPC code of one million in length, which confirms that it is highly promising to apply LDPC codes in communication systems.

The use of LDPC coded signals continues to be used in many new areas. Examples of several possible communication systems that can employ LDPC coded signals include communication systems employing four pairs of twisted pair cables for high speed Ethernet applications (eg, 10 Gbps (gigabits per second) Ethernet according to IEEE 802.3an) Network operation (10GBASE-T) and wireless environment Operating communication systems (eg, within the IEEE 802.11 environmental space including the IEEE 802.11n emerging standard).

For these special communication system applications, it is highly desirable to have an error correction code that enables near capacity. The latency constraints introduced by the use of traditional link codes prevent their use in high data rate communication system applications.

Generally, in a communication system environment employing an LDPC code, there is a first communication device having an encoder capability at one end of the communication channel and a second communication device having a decoder capability at the other end of the communication channel. In most cases, one or both of the two communication devices have encoder and decoder capabilities (e.g., within a two-way communication system). LDPC codes can also be used in a variety of other applications, including those that use some form of data storage (eg, hard disk drive HDD applications and other storage devices) where the data is encoded before being written to the storage medium, and then the data is It is decoded after being read/removed from the data medium.

In many such existing communication devices, one of the greatest difficulties in designing efficient devices and/or communication devices for decoding LDPC coded signals is storage and management during the iterative decoding process (eg, between the check engine and the bit engine). The large area and memory required for all bit edge messages and check edge messages that are updated and used when storing and passing check edge messages and bit side messages. When dealing with relatively large block sizes in an LDPC code environment, the memory requirements and memory management required to process these check edge messages and bit side messages will be very difficult to handle. Thus, there is a need in the art and will continue to require a better means of decoding LDPC coded signals to extract information encoded therein.

In addition, when the size of the low density parity check matrix H for decoding the LDPC coded signal reaches a predetermined size, between the first processing module and the second processing module (for example, the check engine and the bit engine) The interconnectivity will increase significantly.

The apparatus and method of the present invention are further described in the following description of the drawings, specific embodiments, and claims.

According to an aspect of the present invention, there is provided a decoder for decoding an LDPC (Low Density Parity Check) encoded signal, the decoder comprising: a plurality of memories; a plurality of bit engines, and the plurality of bits Each bit engine in the meta engine is configured to connect to at least one of the plurality of memories; a plurality of check engines, each of the plurality of check engines being used for Connecting to at least one of the plurality of memories; and a plurality of multiplexers (MUXs) for selectively selecting the plurality of bits during a decoding process of the first LDPC coded signal An engine and the plurality of check engines are coupled to the first selected one of the plurality of memories; and selectively selecting the plurality of bit engines and during the decoding process of the second LDPC encoded signal The plurality of verification engines are coupled to a second selected one of the plurality of memories; and wherein: the plurality of memories comprise a predetermined number of memories, the predetermined number of memories being used to represent correspondence Multiple of multiple LDPC matrices of multiple LDPC codes a zero submatrix; the decoder is configured to decode the first LDPC coded signal, the first LDPC coded signal corresponding to a first LDPC matrix of the plurality of LDPC matrices, thereby generating a coded within the first LDPC coded signal a best estimate of the bit; and the decoder is configured to decode the second LDPC coded signal, the second LDPC coded signal corresponding to a second LDPC matrix of the plurality of LDPC matrices, thereby generating a second LDPC The best estimate of the encoded bit within the encoded signal.

Preferably, a part of the memory in the plurality of memories is determined by superimposing a plurality of non-zero sub-matrices in the plurality of LDPC matrices corresponding to the plurality of LDPC codes.

Preferably, performing a first greedy, depth search by superimposing a plurality of non-zero sub-matrices in a plurality of LDPC matrices corresponding to the plurality of LDPC codes, A portion of the memory in the plurality of memories is determined.

Preferably, a part of the memory in the plurality of memories is determined by performing a first greedy, deep search on a superposition of a plurality of non-zero sub-matrices in the plurality of LDPC matrices corresponding to the plurality of LDPC codes; and the first Greedy, deep search at least partially considers column affinity matrics, the column affine metrics representing columns in the first LDPC matrix and at least another column in the first LDPC matrix and the second The connectedness of the columns in the LDPC matrix.

Advantageously, the layout of the plurality of memories within the communication device is based on a merge pattern, the merge mode being generated by at least partially considering a column affine metric representing the first LDPC matrix The connectivity of the column in the column with at least one other column of the first LDPC matrix and the column in the second LDPC matrix.

Preferably, the plurality of memories comprise a plurality of merged memories, and one of the plurality of merged memories corresponds to a first non-zero submatrix in the first LDPC matrix, and corresponds to the first A second non-zero submatrix in the two LDPC matrix.

Advantageously, said first LDPC matrix of said plurality of LDPC matrices comprises a first plurality of non-zero sub-matrices; said second LDPC matrix of said plurality of LDPC matrices comprising a second plurality of non-zero sub-matrices; In the decoding process of the first LDPC coded signal, when processing the first non-zero sub-matrix of the first plurality of non-zero sub-matrices, using one of the plurality of memories; In the decoding process of the second LDPC coded signal, when processing the first non-zero sub-matrix of the second plurality of non-zero sub-matrices, the one of the plurality of memories is also used.

Advantageously, said first LDPC matrix of said plurality of LDPC matrices comprises a subset of said plurality of non-zero sub-matrices; and said second LDPC matrix of said plurality of LDPC matrices comprises said plurality of non- The subset of zero submatrices and at least one additional non-zero submatrix.

Preferably, in the decoding process of the first LDPC coded signal, when the first non-zero sub-matrix of the first LDPC matrix is used, and during the decoding process of the second LDPC coded signal, when used When the second non-zero submatrix of the second LDPC matrix is used, one of the plurality of memories is used; and the positions and rows of the rows and columns of the first non-zero submatrix in the first LDPC matrix The positions of the rows and columns of the second non-zero submatrix in the second LDPC matrix are the same.

Advantageously, when decoding said first LDPC coded signal, using a first non-zero submatrix in said first LDPC matrix, and when decoding said second LDPC coded signal, using said second LDPC matrix a second non-zero submatrix, using one of the plurality of memories; the first non-zero submatrix comprising a first row and a first column in the first LDPC matrix; The second non-zero submatrix includes a second row and a second column located in the second LDPC matrix.

Preferably, during processing of the bit node, one of the plurality of multiplexers connects a bit engine of the plurality of bit engines to one of the plurality of memories; And in the processing of the check node, the one of the plurality of multiplexers connects one of the plurality of check engines to the one of the plurality of memories body.

Preferably, the decoder is implemented in an integrated circuit.

Advantageously, said decoder is implemented in a communication device for receiving said first LDPC coded signal or said second LDPC coded signal from a communication channel; and said communication device is in at least one of Implementation: satellite communication systems, wireless communication systems, wired communication systems, and fiber-optic communication systems.

According to an aspect of the present invention, a decoder is provided for decoding LDPC (Low Density Parity Check) encoding a signal, the decoder comprising: a plurality of memory; a plurality of bit engines, and each of the plurality of bit engines is connected to the plurality of At least one memory in the memory; a plurality of verification engines, each of the plurality of verification engines being coupled to at least one of the plurality of memories; and a plurality of multiplexing And (MUX), configured to: when decoding the first LDPC coded signal, connect a first selected one of the plurality of bit engines to the plurality of memorys during bit node processing a first selected memory; when decoding the first LDPC encoded signal, connecting a first selected one of the plurality of verify engines to the plurality of check engines during processing of the check node The first selected memory in the memory; when decoding the second LDPC encoded signal, connecting the second selected positioning meta engine of the plurality of bit engines to the a second selected one of the plurality of memories; and when decoding said When the LDPC encodes the signal, in the process of the check node processing, the second selected check engine of the plurality of check engines is connected to the second selected one of the plurality of memories; wherein The plurality of memories include a predetermined number of memories for indicating a plurality of non-zero sub-matrices of the plurality of LDPC matrices corresponding to the plurality of LDPC codes; the decoder is for decoding Determining a first LDPC coded signal, the first LDPC coded signal corresponding to a first LDPC matrix of the plurality of LDPC matrices, thereby generating a best estimate of a bit coded within the first LDPC coded signal; Decoder for decoding the second LDPC coded signal, the second LDPC coded signal corresponding to a second LDPC matrix of the plurality of LDPC matrices, thereby generating an optimum of the bit coded in the second LDPC coded signal estimate.

Advantageously, said first selected positioning meta engine of said plurality of bit engines is said second selected positioning meta engine of said plurality of bit engines; and said first of said plurality of check engines The selected verification engine is the second selected verification engine of the plurality of verification engines.

Advantageously, said first selected positioning meta engine of said plurality of bit engines is all bit engines of said plurality of bit engines; and said first selected check engine of said plurality of check engines Is all of the check engines of the plurality of check engines.

Preferably, in the decoding process of the first LDPC coded signal, the first LDPC coded signal is disconnected from all bit engines of the plurality of bit-rate engines and all check engines of the check engine.

Preferably, in the decoding process of the first LDPC coded signal, one of the plurality of multiplexers is configured to connect one of the plurality of memories to at least one bit engine; In the decoding process of the first LDPC coded signal, the multiplexer of the plurality of multiplexers is configured to connect the memory of the plurality of multiplexers to at least one check engine; And in the decoding process of the second LDPC coded signal, the multiplexer of the plurality of multiplexers is configured to use the memory in the plurality of memories from the plurality of bit engines All of the bit engines and all of the check engines of the check engine are disconnected.

Preferably, a part of the memory in the plurality of memories is determined by superimposing the plurality of non-zero sub-matrices in the plurality of LDPC matrices corresponding to the plurality of LDPC codes.

Preferably, a part of the memory in the plurality of memories is determined by performing a first greedy, deep search on the superposition of the plurality of non-zero sub-matrices in the plurality of LDPC matrices corresponding to the plurality of LDPC codes.

Preferably, by using a plurality of LDPC matrices corresponding to the plurality of LDPC codes The superposition of the plurality of non-zero sub-matrices performs a first greedy, deep search to determine a portion of the memory in the plurality of memories; and the first greedy, depth search at least partially considers the column affine metric, The listed affine metrics represent connectivity of columns in the first LDPC matrix to at least one other column in the first LDPC matrix and columns in the second LDPC matrix.

Advantageously, the layout of said plurality of memories within said communication device is based on a merge mode, said merge mode being generated by at least partially considering a column affine metric, said column affine metric representing said first LDPC matrix The column is connected to at least one other column of the first LDPC matrix and columns in the second LDPC matrix.

Preferably, the plurality of memories comprise a plurality of merged memories, and one of the plurality of merged memories corresponds to a first non-zero submatrix in the first LDPC matrix, and corresponds to the first A second non-zero submatrix in the two LDPC matrix.

Advantageously, said first LDPC matrix of said plurality of LDPC matrices comprises a first plurality of non-zero sub-matrices; said second LDPC matrix of said plurality of LDPC matrices comprising a second plurality of non-zero sub-matrices; In the decoding process of the first LDPC coded signal, when processing the first non-zero sub-matrix of the first plurality of non-zero sub-matrices, using one of the plurality of memories; In the decoding process of the second LDPC coded signal, when processing the first non-zero sub-matrix of the second plurality of non-zero sub-matrices, the one of the plurality of memories is also used.

Advantageously, said first LDPC matrix of said plurality of LDPC matrices comprises a subset of said plurality of non-zero sub-matrices; and said second LDPC matrix of said plurality of LDPC matrices comprises said plurality of non-zero The subset of sub-matrices and at least one additional non-zero sub-matrix.

Preferably, in the decoding process of the first LDPC coded signal, when the first non-zero sub-matrix of the first LDPC matrix is used, and during the decoding process of the second LDPC coded signal, when used The second non-zero of the second LDPC matrix a sub-matrix, using one of the plurality of memories; and a position of a row and a column of the first non-zero submatrix in the first LDPC matrix and a second non in the second LDPC matrix The rows and columns of the zero submatrix have the same position.

Advantageously, when decoding said first LDPC coded signal, using a first non-zero submatrix in said first LDPC matrix, and when decoding said second LDPC coded signal, using said second LDPC matrix a second non-zero submatrix, using one of the plurality of memories; the first non-zero submatrix comprising a first row and a first column in the first LDPC matrix; The second non-zero submatrix includes a second row and a second column located in the second LDPC matrix.

Preferably, during processing of the bit node, one of the plurality of multiplexers connects a bit engine of the plurality of bit engines to one of the plurality of memories; And in the processing of the check node, the one of the plurality of multiplexers connects one of the plurality of check engines to the one of the plurality of memories body.

Preferably, the decoder is implemented in an integrated circuit.

Advantageously, said decoder is implemented in a communication device for receiving said first LDPC coded signal or said second LDPC coded signal from a communication channel; and said communication device is in at least one of Implementation: satellite communication systems, wireless communication systems, wired communication systems, and fiber-optic communication systems.

According to an aspect of the present invention, there is provided a decoder for decoding an LDPC (Low Density Parity Check) encoded signal, the decoder comprising: a plurality of memories; a plurality of bit engines, and the plurality of bits Each bit engine in the meta-induction is connected to at least one of the plurality of memories; a plurality of check engines, each of the plurality of check engines being connected to at least one of the plurality of memories; and a plurality of multiplexers (MUXs) for: when Decoding the first LDPC encoded signal, connecting the plurality of bit engines to the first selected one of the plurality of memories during processing of the bit node; and decoding the first LDPC encoded signal And in the process of verifying node processing, connecting the plurality of check engines to the first selected memory of the plurality of memories; when decoding the second LDPC coded signal, at a bit node In the process of processing, connecting the plurality of bit engines to the second selected one of the plurality of memories; when decoding the second LDPC coded signals, during the process of verifying the nodes, The plurality of check engines are coupled to the second selected one of the plurality of memories; when the third LDPC coded signal is decoded, the plurality of bits are processed during bit node processing An engine is coupled to the third selected one of the plurality of memories; And when decoding the third LDPC coded signal, in the process of verifying node processing, connecting the plurality of check engines to the third selected one of the plurality of memories; The plurality of memories includes a predetermined number of memories, the predetermined number of memories being used to represent a plurality of non-zero sub-matrices in a plurality of LDPC matrices corresponding to the plurality of LDPC codes; the decoder is configured to decode the An LDPC coded signal, the first LDPC coded signal corresponding to a first LDPC matrix of the plurality of LDPC matrices, thereby generating a best estimate of a bit coded within the first LDPC coded signal; the decoder is for Decoding the second LDPC coded signal, the second An LDPC coded signal corresponding to a second LDPC matrix of the plurality of LDPC matrices, thereby generating a best estimate of a bit coded within the second LDPC coded signal; and the decoder for decoding the third LDPC coded signal And the third LDPC coded signal corresponds to a third LDPC matrix of the plurality of LDPC matrices, thereby generating a best estimate of the bit coded within the third LDPC coded signal.

Preferably, a part of the memory in the plurality of memories is determined by superimposing the plurality of non-zero sub-matrices in the plurality of LDPC matrices corresponding to the plurality of LDPC codes.

Preferably, a part of the memory in the plurality of memories is determined by performing a first greedy, deep search on the superposition of the plurality of non-zero sub-matrices in the plurality of LDPC matrices corresponding to the plurality of LDPC codes.

Preferably, a part of the memory in the plurality of memories is determined by performing a first greedy, deep search on a superposition of the plurality of non-zero sub-matrices in the plurality of LDPC matrices corresponding to the plurality of LDPC codes; and The first greedy, depth search at least partially considers a column affine metric, the column affine metric representing a column in the first LDPC matrix and at least another column in the first LDPC matrix, the second LDPC The columns in the matrix, and the connectivity of the columns in the third LDPC matrix.

Advantageously, the layout of said plurality of memories within said communication device is based on a merge mode, said merge mode being generated by at least partially considering a column affine metric, said column affine metric representing said first LDPC matrix The column is connected to at least one other column of the first LDPC matrix, a column in the second LDPC matrix, and a column in the third LDPC matrix.

Preferably, the plurality of memories comprise a plurality of merged memories, and one of the plurality of merged memories corresponds to a first non-zero submatrix in the first LDPC matrix, and corresponds to the first The second non-zero submatrix in the two LDPC matrix also corresponds to the third non-zero submatrix in the third LDPC matrix.

Advantageously, said first LDPC matrix of said plurality of LDPC matrices comprises A subset of the plurality of non-zero sub-matrices; and the second LDPC matrix of the plurality of LDPC matrices includes a subset of the plurality of non-zero sub-matrices and at least one additional non-zero sub-matrix.

Advantageously, when decoding said first LDPC coded signal, using a first non-zero submatrix in said first LDPC matrix, and when decoding said second LDPC coded signal, using said second LDPC matrix a second non-zero submatrix, using one of the plurality of memories; the first non-zero submatrix comprising a first row and a first column in the first LDPC matrix; The second non-zero submatrix includes a second row and a second column located in the second LDPC matrix.

Preferably, the decoder is implemented in an integrated circuit.

Advantageously, said decoder is implemented in a communication device for receiving said first LDPC coded signal or said second LDPC coded signal from a communication channel; and said communication device is in at least one of Implementation: satellite communication systems, wireless communication systems, wired communication systems, and fiber-optic communication systems.

The various advantages, aspects, and novel features of the invention, as well as the details of the embodiments illustrated herein, are described in the following description and drawings.

100‧‧‧Communication system

110‧‧‧Communication equipment

112‧‧‧transmitter

114‧‧‧Encoder

116‧‧‧ Receiver

118‧‧‧Decoder

120‧‧‧Communication equipment

122‧‧‧ Receiver

124‧‧‧Decoder

126‧‧‧transmitter

128‧‧‧Encoder

130‧‧‧ Satellite communication channel

132, 134‧‧‧ disc satellite receiving antenna

140‧‧‧Wireless communication channel

142, 144‧‧ ‧ tower

150‧‧‧Wired communication channel

152, 154‧‧‧Local antenna

160‧‧‧Fiber communication channel

162‧‧‧Electrical-optical (E/O) interface

164‧‧‧Optical-Electric (O/E) interface

199‧‧‧Communication channel

200‧‧‧Communication system

200‧‧‧Encoder and symbol mapper

201‧‧‧Information Bits

203‧‧‧Discrete value modulation symbol sequence

204‧‧‧Send time signal

205‧‧‧Send signal after continuous filtering

206‧‧‧Received signals in continuous time

207‧‧‧Received signals after continuous filtering

208‧‧‧Discrete time receiving signal

209‧‧‧symbol metrics

210‧‧‧ best estimate

222, 224‧‧‧ functional blocks

230‧‧‧Send drive

232‧‧‧Digital-to-Analog Converter (DAC)

234‧‧‧Transmission filter

260‧‧‧Analog Front End (AFE)

262‧‧‧ Receive Filter

264‧‧• Analog to Digital Converter (ADC)

270‧‧‧metric generator

280‧‧‧Decoder

297‧‧‧transmitter

299‧‧‧Communication channel

300‧‧‧ device

310‧‧‧ memory

320‧‧‧Processing module

330‧‧‧Communication equipment

340‧‧‧Communication system

400‧‧‧ device

410‧‧‧ memory

420‧‧‧Processing module

430‧‧‧Communication equipment

440‧‧‧Communication system

500‧‧‧LDPC code bipartite graph

510‧‧‧ bit nodes

512‧‧‧ bit nodes

520‧‧‧Check node

522‧‧‧Check node

524‧‧‧ side

530‧‧‧

600‧‧‧LDPC decoding function

610‧‧‧Analog Front End (AFE)

611‧‧‧Discrete time signal

620‧‧‧Metric Generator

621‧‧‧ bit metric and/or log likelihood ratio (LLR)

630‧‧‧ bit engine

632‧‧‧Soft Information

635‧‧‧ Iterative decoding processing

640‧‧‧Check engine

641‧‧‧Check side messages

650‧‧‧hard limiter

651‧‧‧hard/best estimate

660‧‧‧Calculator

700‧‧‧Examples

710, 720‧‧‧LDPC matrix

711‧‧‧Non-zero submatrix

712‧‧‧Non-zero submatrix

721‧‧‧Non-zero submatrix

722‧‧‧Non-zero submatrix

730‧‧‧Overlay LDPC matrix

810‧‧‧Three memory structures

811‧‧‧ memory

812‧‧‧ memory

813‧‧‧ memory

821‧‧‧ memory

822‧‧‧ memory

901, 902‧‧‧Examples

921‧‧‧Check Engine

922‧‧‧Check engine

931‧‧‧ bit engine

932‧‧‧ bit engine

991‧‧‧Switch Module

992‧‧‧Switching engine

1011‧‧‧ memory

1012‧‧‧ memory

1021‧‧‧Check Engine

1022‧‧‧Check Engine

1031‧‧‧ bit engine

1032‧‧‧ bit engine

1091‧‧‧Switching module

1092‧‧‧Switching engine

1110‧‧‧Multiple memories

1111-1113‧‧‧ memory

1121‧‧‧Check engine

1123‧‧‧Check engine

1131‧‧‧ bit engine

1133‧‧‧ bit engine

1191‧‧‧Switching Module

1192‧‧‧Switching engine

1210‧‧‧Multiple memories

1211-1213‧‧‧Memory

1221‧‧‧Check Engine

1223‧‧‧Check Engine

1231‧‧‧ bit engine

1233‧‧‧ bit engine

1291‧‧‧Switching Module

1 and 2 illustrate different embodiments of a communication system; FIG. 3 illustrates an embodiment of an apparatus for performing LDPC decoding processing; and FIG. 4 illustrates an alternative embodiment of an apparatus for performing LDPC decoding processing Figure 5 shows an embodiment of an LDPC coded bipartite graph; Figure 6 shows an embodiment of an LDPC decoding function; Figure 7 shows an embodiment of a non-zero sub-matrix superposition of a plurality of LDPC matrices; Figure 8 shows An embodiment of providing memory to accommodate processing of non-zero sub-matrices of the LDPC matrix superimposed in FIG. 7; 9A and 9B illustrate an embodiment of a decoding architecture for adapting the processing of the non-zero sub-matrices of the LDPC matrix superimposed in FIG. 7; FIG. 10 shows an embodiment of a decoding architecture for adapting to FIG. Processing of non-zero sub-matrices of LDPC matrices superimposed; Figure 11 shows an embodiment of a decoding architecture for adapting the processing of non-zero sub-matrices of superimposed LDPC matrices; Figure 12 shows the selectivity of the decoding architecture Embodiments for adapting processing of non-zero sub-matrices of superimposed LDPC matrices; Figures 13 and 14 show an embodiment of providing hardware for decoding non-zero sub-matrices of superimposed LDPC matrices; Figure 15 shows 2 An embodiment of a connection between mutually independent memories for use in check node processing during LDPC decoding processing; FIG. 16 illustrates an embodiment of merged memory connectivity, the merged memory The body is used for check node processing in the LDPC decoding process; FIG. 17 shows an embodiment of a method of processing an LDPC coded signal; FIG. 18 shows an embodiment of a method of processing an LDPC coded signal; Handling various LDPC coded signals to provide hardware An embodiment of the method; Figure 20 shows an alternative embodiment of a superimposed LDPC matrix.

The LDPC (Low Density Parity Check) code is a capacity approximation forward error correction code (ECC) that is being adopted by a large number of communication standards (eg, IEEE 802.3an, IEEE 802.11n, 802.20, DVB-S2). Related application areas include magnetic recording, wireless, and high-speed data transmission over copper and fiber.

In one embodiment, an LDPC decoding process is performed using an iterative decoding method in which check node processing (sometimes referred to as check engine processing) and bit node processing (sometimes referred to as bit engine processing) are performed. Messages are passed back and forth (for example, check edge messages and bit edge messages (also known as variable edge messages). Sometimes this is called For message passing decoding processing, operations are performed on encoded graphical indications (eg, LDPC bipartite graphs, sometimes referred to in the industry as "Tanner" maps).

In most communication applications that use LDPC coded signals, it is necessary and/or desirable to support multiple codes. There are various reasons for this. On the one hand, various codes can be used for different noise environments and/or data characteristics. For example, when the operating environment of the communication system changes (eg, SNR changes), the particular code being used may also be adaptively changed to accommodate changes in the environment, maintaining an acceptable level of performance (eg, acceptable low errors) Acceptable high throughput at bit rate). On the other hand, the transceiver can be designed as a multi-protocol transceiver capable of supporting multiple encoding schemes of different communication protocols. Many applications also operate using LDPC encoding, which corresponds to sub-matrix based LDPC matrices, and some of which use sub-matrices with order changes.

For example, the IEEE 802.11n standard specifies 12 different LDPC codes based on a sub-matrix structure. Similarly, the IEEE 802.16a standard specifies 24 different LDPC codes, which are also based on sub-matrix structures. Some aspects of the invention may be used in these application examples.

The method provided by the present invention uses the sub-matrix structure of the LDPC coding family supported by the decoder as an effective way to reduce the implementation complexity of the decoder. In general, at any time the decoder only needs to support one of the LDPC coding families (eg, when decoding a particular coded signal generated using a particular LDPC code), the decoder construction of the present invention enables the memory and computational units to Efficient sharing. This can greatly reduce the decoder's need for memory space and computational units to reduce the size of the decoder.

In addition, the present invention also provides a method for obtaining a "merged" decoder configuration from all PDPC code super-positions in the LDPC coding family (which must be supported by a particular application) using a variety of related techniques. This merging technique uses a zero submatrix in the individual coding structure and is based on metrics based on proximity in the graphical representation of the LDPC encoding.

It is to be noted that the method provided by the present invention is also applicable to other LDPC decoding configurations, including the aforementioned U.S. Provisional Patent Application No. 60/958,014, and U.S. Utility Model Application Serial No. 11/828,532, the entire disclosure of which is assigned to Density Parity Check) coder in the LDPC decoding structure.

The novel method provided by the present invention uses a single communication device and/or hardware to perform decoding operations of various LDPC encoded signals. Each of these LDPC coded signals has a corresponding LDPC matrix that can be used to perform decoding processing. In some embodiments, each LDPC matrix corresponding to each LDPC encoding may have the same number of sub-matrices. In other embodiments, the number of sub-matrices in each LDPC coding matrix may need to be different. The goal of the method is to minimize the area overhead of the communication device while reducing path congestion therein.

The method can also be used to design a communication device for decoding a plurality of LDPC coded signals. For example, an embodiment may be used to obtain a communication device for decoding an LDPC coded signal generated according to any of the 12 coding schemes used in the IEEE 802.11n standard. Moreover, the method of the present invention can be optimized in a manner that combines memory (eg, when decoding mutually exclusive sub-matrices of different LDPC matrices).

There are various ways to minimize the number of hardware used to decode multiple LDPC coded signals in a communication device. For example, a straightforward method involves superimposing each LDPC matrix corresponding to each LDPC code. Whenever the submatrix position results, the superimposed LDPC matrix includes a non-null entry, after which the memory is used to store the submatrix position. This direct superposition method can provide a sufficient hardware environment for decoding multiple LDPC coded signals. In addition, the additional savings of the hardware portion obtained from this direct superposition method will be described in the following embodiments.

The goal of a digital communication system is to transmit digital data to another location or subsystem from one location or subsystem without error or at an acceptable low error rate. As shown in Figure 1, data can be transmitted over a variety of communication channels within a variety of communication systems: magnetic media, wired, wireless, fiber optic, copper, and other types of media.

1 and 2 are schematic illustrations of communication systems 100 and 200, respectively, in accordance with various embodiments of the present invention.

As shown in FIG. 1, communication system 100 includes a communication channel 199 for communicating communications device 110 (including transmitter 112 with encoder 114 and receiver 116 with decoder 118) at one end of communication channel 199. Another communication device 120 at the other end of the channel 199 (including the transmitter 126 with the encoder 128 and the receiver 122 with the decoder 124) is communicatively coupled. In some embodiments, communication devices 110 and 120 can each include only one transmitter or one receiver. Communication channel 199 can be implemented by a variety of different types of media (e.g., satellite communication channel 130 utilizing satellite dish receiving antennas 132 and 134, wireless communication channel 140 utilizing towers 142 and 144 and/or local antennas 152 and 154, Wired communication channel 150 and/or fiber optic communication channel 160 utilizing an electro-optic (E/O) interface 162 and an opto-electric (O/E) interface 164). Additionally, communication channels 199 may be formed by more than one medium being coupled together.

In order to reduce undesired transmission errors within the communication system, error correction and channel coding schemes are typically employed. In general, these error correction and channel coding schemes include the use of a transmitter-side encoder and the use of a receiver-side decoder.

In the communication system 200 shown in FIG. 2, at the transmitting end of the communication channel 299, the information bit 201 is supplied to the transmitter 297, and the transmitter 297 can use the encoder and the symbol mapper 220 (which can be regarded as different respectively). Function blocks 222 and 224) perform encoding of these information bits 201 to generate a discrete value modulation symbol sequence 203 which is then provided to transmit driver 230. Transmit driver 230 generates a continuous time transmit signal 204 using a DAC (Digital to Analog Converter) 232 and then, through transmit filter 234, generates a filtered continuous time transmit signal 205 that is sufficiently suitable for communication channel 299. At the receiving end of communication channel 299, continuous time received signal 206 is provided to an AFE (analog front end) 260, which includes receive filter 262 (which generates filtered continuous time received signal 207) and an ADC (analog to digital converter) 264 ( A discrete time received signal 208) is generated. A metric generator 270 calculates symbol metrics 209, and decoder 280 uses symbol metrics 209 to make discrete value modulators The number and the best estimate 210 of the information bits encoded within it.

The decoder in the foregoing embodiments has various features of the present invention. In addition, some of the following figures and related descriptions will introduce other and specific embodiments that support the devices, systems, functionality, and/or methods of the present invention (the description of some embodiments is more detailed). One particular type of signal processed in accordance with the present invention is an LDPC encoded signal. Before giving a more detailed introduction, the LDPC code is briefly described.

FIG. 3 illustrates one embodiment of an apparatus 300 that performs LDPC decoding processing. The device 300 includes a processing module 320 and a memory 310. The memory 310 is coupled to the processing module 320, and the memory 310 is used to store operational instructions that enable the processing module 320 to perform various functions. The processing module 320 is configured to perform and/or control the manner of LDPC decoding processing performed in accordance with any of the embodiments described herein or its equivalent embodiments.

The processing module 320 can be implemented using a shared processing device, a single processing device, or multiple processing devices. Such processors may be microprocessors, microcontrollers, digital signal processors, microcomputers, central processing units, field programmable gate arrays, programmable logic devices, state machines, logic circuits, analog circuits, digital circuits, and/or Or any device that processes signals (analogous and/or digital) based on operational instructions. Memory 310 can be a single storage device or multiple storage devices. Such storage devices may be read-only memory, random access memory, volatile memory, non-volatile memory, static memory, dynamic memory, flash memory, and/or any device that stores digital information. Note that when the processing device 320 performs one or more of its functions through a state machine, an analog circuit, a digital circuit, and/or a logic circuit, the memory storing the corresponding operational command is embedded in a state machine, analog circuit, digital circuit, and/or logic. Inside the circuit of the circuit.

In some embodiments, if desired, the manner in which the LDPC decoding process is performed (e.g., the portion of the bit engine from the check engine, the module, and/or the functional module) may be provided from device 300 for execution using the expected LDPC code. LDPC encoded communication system 340. For example, information corresponding to the LDPC code being used (e.g., a parity check matrix of the LDPC code) may also be provided from the processing module 320 to any of the communications system 340. Letter device 330. Moreover, the manner in which the LDPC code to be executed within any of the communication devices 330 within the communication system 340 will be performed may also be provided from the processing module 320.

If desired, the processing module 320 can be designed to generate a plurality of ways to perform LDPC decoding in accordance with a plurality of requirements and/or expectations. In some embodiments, the processing module 320 selectively provides different information (eg, information corresponding to different LDPC codes, etc.) to different communication devices and/or communication systems. Thus, different communication links between different communication devices may employ different LDPC codes and/or perform LDPC decoding. It will be apparent that the processing module 320 can provide the same information to each of the various communication devices and/or communication systems without departing from the scope and spirit of the invention.

FIG. 4 shows an apparatus 400 for performing an LDPC decoding process of another embodiment. The device 400 includes a processing module 420 and a memory 410. The memory 410 is coupled to the processing module 420, and the memory 410 is used to store operational instructions that enable the processing module 420 to perform various functions. Processing module 420 (served by memory 410) can be implemented as a device capable of performing any of the various modules and/or functional blocks described herein. For example, the processing module 420 (served by the memory 410) can be implemented as a device for performing and/or controlling the manner of LDPC decoding processing performed in accordance with any of the embodiments described herein or its equivalent embodiments. .

The processing module 420 can be implemented using a shared processing device, a single processing device, or multiple processing devices. Such processors may be microprocessors, microcontrollers, digital signal processors, microcomputers, central processing units, field programmable gate arrays, programmable logic devices, state machines, logic circuits, analog circuits, digital circuits, and/or Or any device that processes signals (analogous and/or digital) based on operational instructions. Memory 410 can be a single storage device or multiple storage devices. Such storage devices may be read-only memory, random access memory, volatile memory, non-volatile memory, static memory, dynamic memory, flash memory, and/or any device that stores digital information. Note that when the processing device 420 performs one or more of its functions through a state machine, an analog circuit, a digital circuit, and/or a logic circuit, the memory storing the corresponding operational command is embedded in a state machine, analog circuit, digital circuit, and/or logic. Circuit circuit Inside.

In some embodiments, if desired, device 400 can be any type of communication device 430, or any portion of such communication device 430. Communication device 430, including processing module 420 and memory 410, can be implemented within any communication system 440. It is also noted that the various embodiments of the LDPC decoding process and/or the operational parameter modification in accordance with the LDPC decoding process and various equivalent embodiments thereof in the present application are applicable to various types of communication systems and/or communication devices.

FIG. 5 is a schematic diagram of an LDPC code bipartite graph 500. In the industry, the LDPC bipartite graph is also known as the Tanner graph (tanner graph). The LDPC code is treated as a code having a binary parity check matrix such that almost all elements of the matrix are zero (for example, the binary parity check matrix is a sparse matrix). For example, H = (hi, j) MxN is regarded as an LDPC code parity check matrix having a block length of N.

The LDPC code is a linear block code, so the set xC of all codewords is distributed within the null space of the parity check matrix H.

For an LDPC code, H is a sparse binary matrix of m x n dimensions. Each row of H corresponds to one parity, and a set of elements hij indicates that data symbol j participates in parity i. Each column of H corresponds to a code character number.

For each codeword x, there are n symbols, where m are parity symbols. Therefore, the coding rate r is given as: r = (n - m) / n (2)

The weights of rows and columns are defined as the number of collection elements for a given row or column of H , respectively. The set elements of H are selected to meet the performance requirements of the encoding. The number of 1 in the i-th column of the parity check matrix is represented as d _v (i) , and the number of 1 in the j-th row of the parity check matrix is represented as d _c (j) . If for all i , d _v (i) = d _v , for all j , d _c (j) = d _c , then this LDPC code is called (d _v , d _c ) regular LDPC code, otherwise it is It is called an irregular LDPC code.

For an introduction to the LDPC code, please refer to the following reference documents:

[1] R. Gallager, Low-Dentisy Parity-Check Codes, Cambridge, MA: MITT Press, 1963.

[2] R. G. Gallager, “Low dentisyparity check codes,” IRE Trans. Info. Theory. Vol. IT-8, Jan. 1962, pp. 21-28.

[3] MG Luby, M. Mitzenmacher, MA Shokrollahi, DA Spielman, and V. Stemann, "Practical Loss-Resilient Codes", Proc. 29 th Symp. On Theory of Computing, 1997, pp. 150-159.

The regular LDPC code can be represented as a bipartite graph 500, with the left node of the parity check matrix being a code bit variable (or a "variable node" (or "bit node") 510 in the bit decoding method for decoding the LDPC encoded signal) ), the right node is the check equation (or "check node" 520). A bipartite graph 500 (or referred to as a Tanner graph 500) of the LDPC code defined by H may be defined by N variable nodes (eg, N bit nodes) and M check nodes. Each of the N variable nodes 510 has an exact d _v (i) edges (such as edge 530), and a connected bit node such as v _i 512 and one or more check nodes ( M check nodes) Inside). The edge 530 shown in the figure is connected to the bit node v _i 512 and the check node c _j 522. D _v of the sides (shown as d _v 514) is referred to as d _v the number of variable node i. Similarly, each of the M check nodes 520 has an exact d _c ( j ) edge (as indicated by d _c 524 ) that connects the node to one or more variable nodes (or bits) Node) 510. The number d _{c of} the edges is called the degree j of the check node.

The edge 530 between the variable node v _i (or the bit node b _i ) 512 and the check node c _j 522 may be defined as e = (i, j) . However, on the other hand, given the edge e = (i, j) , the node of the edge can be represented as e = (v(e), c(e)) (or e = (b(e), c( e)) Or, the edge in the bipartite graph corresponds to the set element of H , wherein the set element h _ji represents an edge-connected bit (eg, variable) node i and parity node j .

Assuming that the variable node v _i (or the bit node b _i ) is given, a set of edges emitted from the node v _i (or the bit node b _i ) can be defined as E _v (i) = {e | v(e ) = i} (or E _b (i) = {e | b(e) = i}) . These edges are referred to as bit edges, and messages corresponding to these bit edges are referred to as bit edge messages.

Assuming that the check node c _j is given, a set of edges emitted from the node c _j can be defined as E _c (j) = {e | c(e) = j} . These edges are called check edges, and messages corresponding to these check edges are called check edge messages. Next, the result of the derivation is | E _v (i) |= d _v (or | E _b (i) |= d _b ) and | E _c (j) |= d _c .

In general, any code that can be represented by a bipartite graph is characterized by a graphic code. It should be noted that the irregular LDPC code can also be represented by a bipartite graph. However, the degree of each set of nodes within the irregular LDPC code can be selected according to certain distributions. Therefore, for two different variable node sums of the irregular LDPC code, | E _v (i ₁ ) | may not be equal to | E _v (i ₂ ) |. This relationship is also true for two check nodes. The concept of irregular LDPC codes was first introduced in the above referenced document [3].

In summary, through the illustration of the LDPC code, the parameters of the LDPC code can be defined by the degree of distribution, as described by M. Luby et al. in the above referenced document [3], and the following reference documents also have related descriptions:

[4] TJ Richardson and RL Urbanke, "The capacity of low-density parity-check code under message-passing decoding", IEEE Trans. Inform. Theory, Vol. 47, No. 2, Feb. 2001, pp. 599- 618.

This distribution can be described as follows: λ _i represents the fraction of the edge emitted from the variable node of degree i , ρ _i represents the fraction of the edge emitted from the check node of degree i , then the degree distribution pair (λ, ρ) The definition is as follows: , where Mv and Mc represent the maximum degree of the variable node and the check node, respectively.

Although the various embodiments described herein employ a regular LDPC code, it is noted that the features of the present invention are applicable to both regular LDPC codes and irregular LDPC codes.

It is also noted that most of the embodiments described in this application employ "bit node" and "bit side message" or equivalent expressions. But usually in the prior art of LDPC decoding, "bit node" and "bit side message" are also called The "variable nodes" and "variable side messages", therefore, the bit values (or variable values) are those that are attempted to be estimated. Both of these nomenclatures can be used in this application.

FIG. 6 illustrates one embodiment of an LDPC decoding function 600. In order to perform decoding of an LDPC coded signal having an m- bit signal sequence, the functional blocks shown in FIG. 6 are employed. In general, a continuous-time signal is received from the communication channel, as indicated by reference numeral 601. The communication channel can be any type of channel including, but not limited to, a wired communication channel, a wireless communication channel, a fiber optic communication channel, a read channel of an HDD, or other type of communication channel capable of transmitting continuous time signals that have been encoded using LDPC codes.

The analog front end (AFE) 610 performs any initial processing on the continuous time signal (eg, by performing one or more processes of filtering (analog and/or digital filtering), gain adjustment, etc.) and performs digital sampling to generate a discrete time signal 611. The discrete time signal 611 is also referred to as a digital signal, a baseband signal, or other designation known in the art. Typically, the discrete time signal 611 is divided into I, Q (in-phase, quadrature) values of the signal.

Metric generator 620 receives discrete time signal 611 (eg, including I, Q values) and calculates a corresponding bit metric and/or log likelihood ratio (LLR) 621 that corresponds to receipt within discrete time signal 611 value. In some embodiments, the calculation of these bit metrics/LLR symbol metrics 621 is a two-step process in which metric generator 620 first calculates a symbol metric corresponding to the symbol of discrete time signal 611, and then the metric generator re-uses The symbol metric decomposes these symbol metrics into bit metrics / LLR 621. These bit metrics/LLRs 621 are then used by the bit engine 630 to initialize the bit side message (e.g., as indicated by reference numeral 629), and the iterative decoding process 635 of the LDPC coded signal is performed (e.g., as a bit engine) This bit side message will be used when 630 and check engine 640 are executed.

In the case where the value of the log likelihood ratio (LLR) is λ _i and the value of the corresponding received symbol is y _i , the initialization of the bit side message for each variable node i can be defined as follows:

Similarly, at the bit node, bit engine 630 calculates the corresponding soft information for the bit using the most recently updated bit side message (e.g., as shown by soft message 632). However, it is common to perform multiple decoding iterations, so that the initialized bit side message is passed to the check engine 640, in which the check engine 640 uses the initialized bit side during the first decoding iteration. The message updates the check edge message.

At each check node, the LDPC decoding process forms a parity result (XOR) on the sign of the inbound message. This is performed by finding the sign of each outbound message as the XOR of the sign of the corresponding inbound message with the result of the parity.

Then, the reliability of the outbound message from the check node j to the bit (eg, variable) node i is calculated according to the following formula:

In some desirable embodiments, this calculation is performed in the logarithmic domain to convert the multiplication to addition as follows:

Thereafter, bit engine 630 receives updated side messages from check engine 640 (e.g., as indicated by check edge message 641) and uses them to update the bit edge messages. Likewise, bit engine 630 also uses the bit metric/LLR 621 received from metric generator 620 when performing an update of the bit side message in accordance with LDPC decoding. These updated check edge messages 641 are then passed back to the bit node (e.g., bit engine 630) where the bit metric/LLR 621 and the current iteration value of the check edge message are used to calculate the bit. Soft information 632. At each bit (e.g., variable) node, the calculation of soft information includes forming an inbound message (e.g., check edge message 641) from the check node. The sum of the symbols of the LLR. The decoded bits are given by the sign of the summed _sign. Each outbound message for the next decoding iteration is calculated by subtracting the corresponding inbound message from the sum. To continue the iterative decoding process 635, these bit side messages 631 are passed to the check engine 640 after being updated.

Then perform the decoding of the iteration again. At the check node, the check engine 640 receives the updated bit edge message 631 sent from the bit node (e.g., from the bit node 630) and updates the check edge message accordingly. The updated check edge message 641 is then transmitted back to the bit node (e.g., bit engine 630) where the bit metric/LLR 621 and the current iteration value of the check edge message are used to calculate the softness of the bit. Information 632. Thereafter, using the soft information 632 of the just calculated bit, the bit engine 630 again updates the bit edge message using the previous value of the check edge message (from the previous iteration). The iterative process 635 continues between the bit node and the check node in accordance with the LDPC code bipartite graph employed in encoding the signal being decoded.

These iterative decoding processing steps performed by the bit node engine 630 and the check node engine 640 are repeated until the stopping criteria are met, as indicated by reference numeral 661 (eg, a predetermined or adaptive determined iteration has been performed) After the number of times, all syndromes of the LDPC code are equal to zero (eg, all parity is satisfied), and/or other stop criteria have been met). Another way to stop LDPC decoding is to stop when the current estimate of the LDPC codeword satisfies the following relationship:

Soft information 632 is generated in bit engine 630 each time the iterative process is decoded. In the embodiment shown in the figure, soft information 632 can be provided to a hard limiter 650 that makes a hard decision, and hard information (e.g., hard/best estimate 651) can be provided for correction. Sub-calculator 660 determines if the syndromes of the LDPC code are all equal to zero. That is, the syndrome calculator 660 determines whether each syndrome associated with the LDPC code is equal to zero based on the current estimate of the LDPC codeword.

When the syndrome is not equal to zero, the iterative decoding process 635 is resumed, and the bit side message is updated and communicated between the bit node engine 630 and the check node engine 640 as appropriate. And check edge messages. After all the steps of the iterative decoding process have been performed, the hard/best estimate 651 of the bit is output based on the soft information 632.

It should also be noted that for good decoding performance, it is important that the length of the loop period in the bipartite graph is as long as possible. A short loop period, such as 4 loops, may degrade the performance of the message passing decoding method used to decode the LDPC numbered signal.

Although the mathematical calculations of the message passing decoding method include hyperbolic functions and logarithmic functions (see equation (5)), in hardware implementations, these functions can also be approximated by a lookup table (LUT) or directly through a logic gate. Mathematical calculations only involve addition, subtraction, and XOR operations. The number of bits required in a fixed point implementation is determined by the required coding performance, the speed at which the decoder converges, and whether it is necessary to suppress the error floor (as described in reference [5]).

[5] Zhang, T., Wang, Z., and Parhi, K., "On finite precision implementation of low density parity check codes decoder", Proceedings of ISCAS , Sydney, Australia, May 2001, pp 202-205.

FIG. 7 illustrates an embodiment 700 of non-zero sub-matrix superposition of a plurality of LDPC matrices. Embodiment 700 describes two separate LDPC matrices (code 1, LDPC matrix 710 and code 2, LDPC matrix 720) corresponding to two separate LDPC codes. Each of the LDPC matrices 710 and 720 includes four sub-matrices, two of which are zero sub-matrices and two of which are non-zero sub-matrices (eg, containing more than one non-zero element).

The code 1, the LDPC matrix 710 includes a non-zero sub-matrix 711 and a non-zero sub-matrix 712; the code 2, the LDPC matrix 720 includes a non-zero sub-matrix 721 and a non-zero sub-matrix 722. The LDPC matrices 710 and 720 are superimposed to generate a superimposed LDPC matrix 730. As shown, the non-zero sub-matrices 711 and the non-zero sub-matrices 712 are in the same position in the superimposed LDPC. In this embodiment, only one non-zero submatrix is left in the superimposed LDPC matrix 730.

FIG. 8 illustrates an embodiment 800 of memory processing to accommodate the processing requirements of the non-zero sub-matrices of the superimposed LDPC matrix 730 shown in FIG. Used for superimposing LDPC matrices A single memory structure in which each LDPC code in 730 performs a decoding process may employ a three-memory 810 configuration (shown as including memory 811, memory 812, and memory 813) or a two-memory configuration (shown as Including memory 821 and memory 822). In either embodiment, each memory can be selectively coupled to a bit engine and a check engine for performing bit node processing and check node processing, respectively, to update the bit side message and the check side message. .

Figures 9A and 9B illustrate embodiments 901 and 902 of a decoding apparatus for processing non-zero sub-matrices in the superposed LDPC matrix of Figure 7.

Referring to Figure 9A, this embodiment includes three memories (i.e., memory 811, memory 812, and memory 813). The bit metric/LLR is provided to a plurality of bit engines (eg, bit engine 931 and bit engine 932). The switching module 991 is connected between the bit engines 931-932 and the memories 811-813. Another switching engine 992 is coupled between the verification engines 921-922 and the memory 811-813.

Note that the switch module 991 (and the other switch modules described herein) can use a multiplexer (MUX) with multiple inputs/outputs, multiple MUXs, or allow memory and bit engine and memory with the school. It is implemented by checking other devices connected between the engines.

In the process of decoding LDPC code 1, one memory is not used (for example, memory 812 shown in the figure), and sub-matrix 711 is processed using memory 811, sub-matrix 712 is processed using memory 813, or vice versa. .

Alternatively, a single switching module can be used (e.g., check engine 921-922 can be coupled to switching module 991).

After performing the appropriate bit node processing and check node processing and satisfying the stopping criteria, the bit engine 931-932 operates to generate soft information from which the LDPC encoded signal encoded according to the code 1 can be obtained. The best estimate of the coding bit.

Referring to FIG. 9B, in the process of decoding the LDPC code 2, another memory is not used (for example, the memory 813 shown in the figure), and the memory 811 is used. The sub-matrix 721 is processed, the sub-matrix 722 is processed using the memory 812, or vice versa.

Also alternatively, a single switching module can be used (eg, the check engines 921-922 can be connected to the switching module 991).

After performing the appropriate bit node processing and verifying the node processing and satisfying the stopping criteria, the bit engine 931-932 operates to generate soft information from which the LDPC encoded signal encoded according to the encoding 2 can be obtained. The best estimate of the coding bit.

The embodiment of Figures 9A and 9B shows a direct simple superposition method in which three separate memories are used. Hereinafter, an LDPC coded signal coded according to the same two LDPC codes can be decoded using a configuration of only two memories.

FIG. 10 shows a schematic diagram of an embodiment of a decoding apparatus for processing a non-zero submatrix of the superimposed LDPC matrix 730 of FIG. This embodiment shows how the same LDPC matrices 710 and 720 can be decoded with only two memories (relatively using three memories). As shown, sub-matrix 712 (of LDPC matrix 710) and sub-matrix 722 (of LDPC matrix 720) are not in the same sub-matrix position in each LDPC matrix 710 and 720. In each LDPC matrix 710 and 720, the two sub-matrix locations are mutually exclusive. Therefore, a separate memory (for example, a merged memory) can be used, and in the process of decoding the first LDPC coded signal encoded according to the code 1, the decoding process of the sub-matrix 712 is performed, and the code 2 is encoded. The decoding process of the sub-matrix 722 is performed in the process of performing the decoding process on the encoded first LDPC coded signal.

Regarding the merged memory, if a certain memory is not used by the LDPC encoding, it is apparent that the memory can be removed. Therefore, the memory only needs to be provided to those sub-matrices with non-zero elements in the resulting superimposed LDPC. Moreover, each memory also has at least one non-zero LDPC code active therein (e.g., for decoding the LDPC code).

As mentioned above, higher efficiency can be obtained by merging memory components corresponding to mutually exclusive non-zero sub-matrices. The set of memory storing the mutually exclusive active encoding group can Merged into a single memory. The larger the number of memories in which the mutually exclusive active code group is stored (which can be appropriately determined), the greater the degree of integration that can be achieved and the ability to save more hardware (for example, reducing the amount of memory used).

Referring to Figure 10, this embodiment includes only two memories (i.e., memory 1011 and memory 1012). The bit metric/LLR is provided to a plurality of bit engines (e.g., bit engine 1031 and bit engine 1032). The switching module 1091 is connected between the bit engine 1031-1032 and the memory 1011-1012. Another switching engine 1092 is connected between the verification engines 1021-1022 and the memory 1011-1012.

As with another embodiment, it is noted that the switching module 1091 (and other switching modules described herein) can use a multiplexer (MUX) with multiple inputs/outputs, multiple MUXs, or allow memory and bits. The engine and the memory and the check engine are selected to connect to other devices.

In the process of decoding LDPC code 1, both memories 1011-1012 are in use. The memory 1011 is for processing the sub-matrix 711, and the memory 1012 is for processing the sub-matrix 712, or vice versa.

After performing the appropriate bit node processing and check node processing and satisfying the stopping criteria, the bit engine 1031-1032 operates to generate soft information from which the LDPC encoded signal encoded according to the code 1 can be obtained. The best estimate of the coding bit.

Also, in the process of decoding LDPC code 2, both memories 1011-1012 are in use. The memory 1011 is for processing the sub-matrix 721, and the memory 1012 is for processing the sub-matrix 722, or vice versa.

After performing the appropriate bit node processing and check node processing and satisfying the stopping criteria, the bit engine 1031-1032 operates to generate soft information from which the LDPC encoded signal encoded according to the code 2 can be obtained. The best estimate of the coding bit.

Alternatively, as with another embodiment, a single switching module can also be used (e.g., the verification engine 1021-1022 can be coupled to the switching module 1091).

As shown, merged memory (e.g., memory 1012 as shown in the figure) can be used to perform processing of non-zero sub-matrices 712 of code 1 and for performing processing of non-zero sub-matrices 722 of code 2. The principle of using merged memory to perform decoding processing of mutually exclusive non-zero sub-matrices can also be extended to larger LDPC matrices.

11 shows a schematic diagram of an embodiment 1100 of a decoding apparatus for processing a non-zero submatrix of a superimposed LDPC matrix. This embodiment can be generalized to be applied to the decoding process of an encoded signal of an LDPC matrix of any desired size.

Referring to Figure 11, this embodiment includes a plurality of memories 1110 (i.e., memories 1111-1113). The bit metric/LLR is provided to a plurality of bit engines (e.g., bit engine 1131 and bit engine 1133). The switching module 1191 is connected between the bit engines 1131-1133 and the plurality of memories 1110. Another switching engine 1192 is connected between the verification engines 1121-1123 and the plurality of memories 1110.

Again, as with another embodiment, it is noted that the switching module 1191 (and other switching modules described herein) can use a multiplexer (MUX) with multiple inputs/outputs, multiple MUXs, or allow multiple memories. The body 1110 is implemented with a plurality of bit engines 1131-1133 and other devices that are selectively connected between the memory 1110 and the plurality of check engines 1121-1123.

In decoding the first signal encoded according to the first LDPC encoding, the first subset of the memory 1110 is used to process the non-zero submatrices in the first LDPC encoded LDPC matrix.

In decoding the second signal encoded according to the second LDPC encoding, the second subset of the memory 1110 is for processing the non-zero submatrices in the second LDPC encoded LDPC matrix.

In decoding the third signal encoded according to the third LDPC encoding, a third subset of the memory 1110 is used to process the non-zero submatrices in the second LDPC encoded LDPC matrix.

And so on......

In some embodiments, the same amount is used when decoding each encoded signal A plurality of memories 1110. In other embodiments, a different number of multiple memories are used in decoding different encoded signals. For example, in various embodiments, each of the first subset, the second subset, and the third subset described above may include the same amount of memory or include a different number of memories.

Switching modules 1191 and 1192 are used to ensure proper communication between the plurality of bit engines 1131-1133 and the plurality of memories 1110 to obtain the check edge messages required during the execution of the update bit side message, and Switching modules 1191 and 1192 are used to ensure proper communication between the plurality of check engines 1121-1123 and the plurality of memories 1110 to obtain the bit side messages required during the execution of the update check edge message.

After performing the appropriate bit node processing and check node processing and satisfying the stopping criteria, the bit engine 1131-1132 operates to generate soft information from which the encoding of the particular LDPC encoding according to the interest can be obtained. The best estimate of the coding bits in the LDPC coded signal.

FIG. 12 shows a schematic diagram of another embodiment 1200 of a decoding apparatus for processing a non-zero submatrix of a superimposed LDPC matrix.

Referring to Figure 12, this embodiment includes a plurality of memories 1210 (i.e., memories 1211-1213). The bit metric/LLR is provided to a plurality of bit engines (eg, bit engine 1231 and bit engine 1233). The switching module 1291 is connected between the plurality of bit engines 1231-1233 and the plurality of memories 1210. The same switching engine 1191 also provides selectable connectivity between the verification engines 1221-1223 and the plurality of memories 1210.

In decoding the first signal encoded according to the first LDPC encoding, the first subset of the memory 1210 is used to process the non-zero submatrices in the first LDPC encoded LDPC matrix.

In decoding the second signal encoded according to the second LDPC encoding, a second subset of the memory 1210 is used to process the non-zero submatrices in the second LDPC encoded LDPC matrix.

In the process of decoding the third signal encoded according to the third LDPC encoding, the third subset of the memory 1210 is used to process the second LDPC encoded LDPC A non-zero submatrix in a matrix.

And so on......

In some embodiments, the same number of multiple memories 1210 are used in decoding each encoded signal. In other embodiments, a different number of multiple memories are used in decoding different encoded signals. For example, in various embodiments, each of the first subset, the second subset, and the third subset described above may include the same amount of memory or include a different number of memories.

The switching module 1291 is configured to ensure proper communication between the plurality of bit engines 1231-1233 and the plurality of memories 1210 to acquire a check edge message required during the execution of the update bit side message, and switch the mode Group 1291 is also used to ensure proper communication between the plurality of check engines 1221-1223 and the plurality of memories 1210 to obtain the bit side messages required during the execution of the update check edge message.

After performing appropriate bit node processing and node verification processing, and encountering a stop criterion

The bit engine 1231-1232 will generate soft information from the best estimate, which may be made based on the LDPC coded LDPC coded signal of the particular interest.

Figures 13 and 14 illustrate hardware instructions for decoding non-zero sub-matrices of a superposed LDPC matrix.

Referring to Figure 13, each LDPC coded signal decoded in accordance with embodiment 4300 has the same number of non-zero sub-matrices. In decoding LDPC coded signals encoded in accordance with each LDPC code, the only difference is that the subset of memory employed by each coded signal is different.

For example, when decoding a signal encoded in accordance with code 1, the corresponding LDPC matrix includes an 'X' non-zero submatrix, and all provided bit engines are available for bit node processing. All provided check engines are used for verification processing. The total number of memories is 'Y', and the 'X' memories are used, that is, the subset 1 of these 'Y' memories is used.

When decoding a signal encoded in accordance with code 2, the corresponding LDPC matrix includes 'X' non-zero sub-matrices, and all of the provided bit-element engines are available for bit-node processing. All provided check engines are used for verification processing. The total number of memories is 'Y', and to which 'X' memories are used, that is, subsets 2 of these 'Y' memories are used. And so on, as shown in the figure.

It can be seen that in embodiment 1300, the only difference in decoding different LDPC coded signals is the difference in the subset of memory used.

When decoding each LDPC coded signal encoded in accordance with each LDPC code in Fig. 13, the number of bit engines and check engines used is the same.

Referring to Figure 14, an embodiment 1400 illustrates an embodiment employing varying degrees of parallelism. This embodiment 1400 illustrates better variability and flexibility in decoding different LDPC coded signals.

For example, when decoding a signal encoded in accordance with code a, the corresponding LDPC matrix includes 'a1' non-zero sub-matrices. The a2 subset of the provided bit engine with a total of 'M' can be used for bit node processing, and the a3 subset of the provided check engines with a total of 'L' can be used for node check processing and can use the total number For the 'a2' or 'a3' memory in the available memory of 'Z', the subset a4 in the 'Z' memory can be used.

When decoding a signal encoded in accordance with code b, the corresponding LDPC matrix includes 'b2' non-zero sub-matrices. The b2 subset of the provided bit engine with a total of 'M' can be used for bit node processing, and the b3 subset of the provided check engines with a total of 'L' can be used for node check processing and can use the total number For the 'b2' or 'b3' memory in the available memory of 'Z', the subset b4 in the 'Z' memory can be used. And so on, as shown in the figure.

For example, in embodiment 1400, each sub-replacion (eg, bit node processing or node verification processing) can be performed using multiple loops. Note that in one example, the bit node processing can update the first half of the bit edge messages using the provided number of bit engines in the first time, and can use the number of bits provided in the second time. The meta engine updates the second half of the bit side message, which can be seen as a semi-parallel bit node processing method, so that the decoding sub-over generation is completed step by step in two steps. (for example, bit node processing).

In another embodiment, note that in another example, the node check process may update the first one third of the check edge message using the provided number of check engines in the first time, and in the second In time, the second third of the check edge message is updated using the provided number of check engines, and the last one third of the check edge message is updated using the provided number of check engines in the third time. This can be regarded as a parallelism node check processing method, so that the decoding sub-health (for example, the node check processing) is completed step by step in three steps.

It will be apparent that various modifications may be made to the invention without departing from the scope and spirit of the invention, and therefore, the number of loops employed per sub-replacion may vary depending on the particular embodiment.

Returning to embodiment 1400, each LDPC matrix need not include the same number of non-zero sub-matrices. When decoding a particular LDPC coded signal (when all of the provided memory is not required), the memory for the corresponding zero submatrix of a particular LDPC may be broken. During the decoding of a particular signal, when a particular memory is not in use, the memory can be disconnected from the rest of the circuit (for example, disconnected) to prevent idle memory from interfering with active computation and Save energy. The disconnection of the memory can be achieved by setting the input of each variable node and check node to the memory to 0 (or the maximum value "maxval"), which are used for decoding, respectively. The particular unused sub-matrices (zero sub-matrices) of the particular code are connected.

Figures 15 and 16 illustrate an embodiment using at least one merge memoty. In these embodiments, there are memories that can be used as follows.

Memory A is available when decoding signals encoded in accordance with codes 0 and 1, and memory A is free when other codes are decoded.

Memory B is available when decoding signals encoded in accordance with codes 2 and 3, and memory B is idle when other codes are decoded.

Fig. 15 shows the connectivity between two mutually exclusive memories for the check node processing in accordance with the LDPC decoding process. This embodiment shows when decoding is coded according to codes 0 and 1. How to use the memory A in the signal of the code, and how to disconnect the memory A from the hardware (for example, disconnection) when decoding the encoded signal of the other code. When decoding certain signals, when memory A is not in use, memory A is effectively disconnected from the rest of the hardware/circuit (for example, disconnected) to prevent idle memory from interfering with active operations and saves energy. The disconnection of the memory can be achieved by setting the input of each variable node and check node to the memory to 0 (or the maximum value "maxval"), which are used for decoding, respectively. The particular unused sub-matrices (zero sub-matrices) of the particular code are connected.

This embodiment also shows how to use the memory B when decoding the signals encoded in accordance with codes 2 and 3, and shows how to unlink the memory B from the hardware when decoding the encoded signals of other codes (for example Said, disconnected). When decoding certain signals, when memory B is not in use, memory B is effectively disconnected from the rest of the hardware/circuit (for example, disconnected) to prevent idle memory from interfering with active operations and saves energy. The disconnection of the memory can be achieved by setting the input of each variable node and check node to the memory to 0 (or the maximum value "maxval"), which are used for decoding, respectively. The particular unused sub-matrices (zero sub-matrices) of the particular code are connected.

It should be noted that the connection of the variable/bit engine to the memories A and B is not shown in the figure, and the connection of the variable/bit engine to the memory C is not shown in the following figures. However, those skilled in the art will appreciate the connectivity of the associated variable/bit engine when the connectivity of the verification engine is shown.

It can be seen that the memories A and B can be combined into a single memory C. Next, when the signals encoded in accordance with codes 0, 1, 2, and 3 are decoded, the memory C is available, and when the signals encoded by the other codes are decoded, the memory C is idle.

It should be noted that when the combined memory is provided separately, it maintains all of the emerging connectivity. In the example shown in Figs. 15 and 16, when the memory C is used (Fig. 16), the original connectivity of the memory A and the memory B (Fig. 15) can be maintained.

For example, consider that there is a mutually exclusive code group in memory A and memory B, and The memory A is in an embodiment different from the sub-matrix row of the memory B (for example, each of the memory A and the memory B corresponds to a sub-matrix at a different position in the true LDPC matrix), Then memory A and B will be connected to different check nodes and can be merged into memory C. Similarly, the memory C can maintain the connectivity of the memory A to the check node, and can also maintain the connectivity of the memory B to the check node.

Figure 16 illustrates an embodiment 1600 for the connectivity of merged memory processed by check nodes in accordance with LPDC decoding processing. In a two-step embodiment, 3MUX is employed to allow a single memory C to replace memory A and B.

FIG. 17 illustrates an embodiment of a method 1700 for processing an LDPC coded signal.

Referring to Figure 17, as shown in block 1710, the method 1700 initially includes receiving a continuous time signal. As shown in block 1712, the receiving and processing of the continuous time signal can include performing any necessary downconversion on the first continuous time signal to generate a second continuous time signal. The frequency conversion can be achieved by directly converting the carrier frequency to a baseband frequency. Alternatively, the frequency transform can be implemented by IF (Intermediate Frequency). In either embodiment, the received continuous time signal is typically downconverted to a baseband continuous time signal when the method is performed. Likewise, some type of gain adjustment/gain control can be applied to the received continuous time signal.

As shown in block 1720, the method 1700 can also include sampling the first (or second) continuous time signal to generate a discrete signal and extracting I, Q (in-phase, integral) components therefrom. An ADC (analog to digital converter) or similar device can be used to generate the discrete signal from the received continuous time signal that is suitably downconverted (and can be processed by filtered, gain adjusted, etc.). It is also possible to extract the I, Q components of a single sample of the discrete time signal at this step. Next, as shown in block 1730, method 1700 includes demodulating the I, Q components and can include a symbol map of the I, Q components (for example, a constellation of maps with constellation points) to A sequence of discrete value modulation symbols is generated.

As shown in block 1740, the next step of method 1700 includes performing an edge message update until a stop criterion is encountered (for example, a preset iteration number until all symbols are equal to 0, or until other stop criteria are encountered) . This step can be seen as being performed in accordance with the above LPDC decoding of various embodiments. The LPDC decoding typically includes bit engine processing for updating bit side messages (e.g., variable edge messages) (as shown in block 1742), and check engine processing for updating check edge messages. (as shown in block 1744).

As shown in block 1746, method 1700 can also include sampling the selected hardware to provide for the selected LDPC code when decoding the particular LPDC encoded signal of interest. For example, the method 1700 is for performing processing of different LDPC coded signals that are generated using different LDPC codes (and thus having different LDPC matrices, respectively). Depending on the signal being decoded, method 1700 is for selecting to provide suitable hardware to perform decoding of the particular LPDC encoded signal of interest.

As shown in block 1750, after encountering the stop criterion, method 1700 includes making soft decisions based on soft information corresponding to the most recently updated bit side information. The method 1700 finally includes outputting a best estimate of the LDPC coded bits (eg, LDPC codewords or LDPC code regions) (including information bits) extracted from the received continuous time signal.

FIG. 18 illustrates an embodiment of a method 1800 for processing an LDPC coded signal.

As shown in block 1810, the method 1800 begins by identifying all LDPC matrices required to decode all LDPC encoded signals.

Next, as shown in block 1820, the method 1800 generates superposition results for all LDPC matrices (for example, including superposition of each sub-matrix position of all LDPC matrices).

Next, as shown in block 1830, the method 1800 provides memory that accommodates the sub-matrices of each superposition result. This can be done in a number of ways and can include any number of steps. In one embodiment, this includes a first greedy depth search of the last superimposed LDPC matrix to determine the desired number of memories (as shown in block 1822).

Although a polynomial time-combined search algorithm can be employed to obtain a solution provided by the memory, it does not always provide a minimum memory solution. In a 4-node embodiment, the node can be considered to be in alphabetical order.

Memory A can be merged with Memory B without further merging. The 4-node minimum memory solution combines memory A and memory B (for example, merged into memory E), and merges memory C and memory D (for example, merged into memory F) .

A first depth search can also be employed to obtain the least memory solution, such that a first full depth search is exhaustive and an actual minimal memory solution can be found. However, certain embodiments show difficulties in using this approach. When considering that the root of the solution can be adjusted to accommodate the IEEE 802.11n standard and all 12 LDPC codes here (each code has its own corresponding LDPC matrix), then the root of the IEEE 802.11n standard has 2041 branches. The result of the maximum tree depth is approximately 105. The search field of (O(2041) ¹⁰⁵ ) cannot complete all searches without requiring a large amount of processing and time.

The search for one or more heuristics to accomplish the minimum memory requirement (or relatively little memory requirement) and the merging of the memory in the resulting superimposed LDPC matrix becomes simpler. A measure of those rows along the column affine can be taken. In addition, some assumptions that can be used to manage the merge search heuristics include: (1) the variable/bit nodes can be compressed relative to each other, and the check nodes can cover a relatively large area of the resulting superimposed LDPC matrix, and 2) The memory to be provided can be tightly clustered around the variable/bit node.

The search can sample such a heuristic method, the memory belonging to the column of the finally obtained superimposed LDPC matrix is tightly packed, and the check node is connected to the superposition Different columns of the LDPC matrix.

The column affine metric can then be generated based on the connections between the columns of the particular sub-matrices and other sub-matrices in the resulting superimposed LDPC matrix. As in another embodiment, the column affine metric can be used to control/manage the first greedy depth search of the resulting superimposed LDPC matrix.

As shown in block 1824, this may also include combining memory with mutually exclusive active code into the merged memory. As shown in block 1826, the method 1800 can also include generating a merge mode of memory (eg, based on a first greedy depth search and a mutually exclusive merge) and setting the memory based thereon.

Next, as shown in block 1831, method 1800 decodes the first LDPC encoded signal having the first corresponding LDPC matrix using the first subset of the provided memory.

As shown in block 1832, if the LDPC coded signal is to be decoded, then method 1800 can then decode the nth LDPC coded signal having the nth corresponding LDPC matrix using the nth subset of the provided memory.

FIG. 19 illustrates a method 1900 for providing hardware for various LDPC coded signal processing.

As shown in block 1910, the method 1900 begins by identifying all LDPC matrices needed to decode all LDPC coded signals based on connectivity between each column and other columns.

As shown in block 1920, the method 1900 then generates superposition results for all LDPC matrices (for example, including superposition of each sub-matrix position of all LDPC matrices).

As shown in block 1930, method 1900 then uses the column affine as a metric to perform a first greedy depth search of the overlay results to determine the desired number of memory and the merged group (eg, merge mode).

As shown in block 1940, the method 1900 then provides appropriate memory to each sub-matrix of the overlay result based on the merge mode.

Figure 20 illustrates an alternative embodiment 2000 of superimposing an LDPC matrix. This embodiment 2000 corresponds to the superposition of 12 individual LDPC matrices to perform decoding processing using 12 codes in the IEEE 802.11n standard. When 12 separate LDPC matrices are superimposed (and each of their sub-matrices), there are a total of 205 non-zero sub-matrices in the last appearing superposed LDPC matrix.

Messages corresponding to each non-zero sub-matrix can be stored in memory. The checksum bit engine can be run so that they can properly and selectively read information from the running memory or write information to the running memory to extract each suitable one that can be used to decode a particular signal. Non-zero sub-matrices, these specific signals are encoded according to any of the 12 coding schemes used by the IEEE 802.11n standard.

In this embodiment, only 88 of the 205 memories are available at any time. At least 117 of the 205 memories are always free. Obviously, when decoding the first encoded signal, the first subset of the 205 memories (88 memories) can be used, and when decoding the second encoded signal, the first of the 205 memories can be used. Two subsets (88 memories).

The number of 205 memories provided can be significantly reduced by the sample merge mode, and the minimum amount can be used by using the first greedy depth search of the last stacked LDPC matrix to determine the amount of memory required (may not be practical) Really least) memory. Such a merge mode is shown in the appendix, and this particular merge mode can be obtained by using the column affine as the first greedy depth search of the last superimposed LDPC matrix of the metric. This merge mode only needs to provide 102 memories (compared to 205). Visible memory can save about 50%, and this will also make adjacent paths much more compressed. In fact, a solution can be found that requires less than 102 memories (for example, using the first full depth search) and can be found using 102 provided memories (for example, Using the first greedy depth search found) has a relatively good regional trade-off ratio and signal congestion.

During the decoding of a particular signal, when a particular memory is not in use, the memory can be disconnected from the rest of the circuit (for example, disconnected) to prevent idle memory from interfering with active operations and saving energy. The disconnection of the memory can be passed Each variable node and check node is implemented with a memory input of 0 (or a maximum value "maxval"), respectively, with the particular unused one used to decode the particular code. Submatrices (zero submatrices) are connected.

It should be noted that the multi-code approach presented here can be used on any sub-matrix/subclock based on an LDPC decoder, where the messages corresponding to the sub-matrix/sub-clock are stored in some type of memory (for example , SRAM, register set, etc.). In addition, when attempting to obtain a more efficient memory solution, the heuristics used can be more precisely tuned based on the backend implementation detail. In other words, depending on the particular application that the multi-code LDPC decoder needs to perform, the heuristics can be more accurately tuned depending on the particular application.

It should be noted that the various modules (eg, encoders, decoders, processing modules, etc.) described herein can be separate processing devices or multiple processing devices. Such a processing device may be a microprocessor, a microcontroller, a digital signal processor, a micro-calculator, a central processing unit, a field programmable gate array, a programmable logic device, a state machine, an analog circuit, a digital circuit, and/or Any device that processes signals (digits and/or analogies) according to operational instructions. The memory can be a separate storage device or multiple storage devices. Such a storage device may be read only memory, random access memory, static memory, dynamic memory, flash memory, and/or any memory that can store digital information. It should be noted that when the processing device performs one or more functions through a state machine, an analog circuit, a digital circuit, and/or a logic circuit, a memory storing the corresponding operational command can be implanted into the state machine, the analog circuit, and the digital circuit. And / or logic circuit in the circuit. In such an embodiment, the memory stores at least some of the steps and/or instructions shown herein, and the processing module coupled to the memory executes the instructions.

The invention has been described above by means of method steps illustrating the specified functions and relationships. For the convenience of description, the boundaries and order of these functional component modules and method steps are specifically defined herein. However, as long as a given function and relationship can be properly implemented, changes in boundaries and order are allowed. The boundaries of any of the above changes or The order should be considered to be within the scope of the claims.

The invention has also been described above with the aid of functional modules that illustrate certain important functions. For the convenience of description, the boundaries of these functional component modules are specifically defined herein. When these important functions are properly implemented, it is permissible to change their boundaries. Similarly, flowchart modules are also specifically defined herein to illustrate certain important functions. For a wide range of applications, the boundaries and order of the flowchart modules can be additionally defined as long as these important functions are still implemented. Variations in the boundaries and sequence of the above-described functional modules and flow-through functional modules are still considered to be within the scope of the claims.

Those skilled in the art are also aware of the functional modules described herein, as well as other illustrative modules, modules, and components, which may be, for example, or by discrete components, special-purpose integrated circuits, processors with appropriate software. And a combination of similar devices.

Further, although the details are described in detail to understand and understand the above embodiments, the invention is not limited to the embodiments. Any technical solution known to those skilled in the art that makes various changes or equivalent substitutions to these features and embodiments is within the scope of the present invention.

Attachment introduction

The merge mode can be generated in a variety of manners and embodiments to guide the provision of medium hardware in a device for decoding multiple LDPC coded signals. One possible embodiment involves decoding in accordance with any of the 12 coding schemes used in the IEEE 802.11n standard.

In this embodiment, it can be seen that only 102 memories are required when sampling the merge search, and 205 memories are required when using the simple overlay method.

Attachment (merger mode)

Unmerge memory, row 0 column 0, code 0 (0,0), code 1 (0,0), code 2 (0,0), code 3 (0,0), code 4 (0,0), Encoding 5 (0,0), encoding 6 (0,0), encoding 7 (0,0), encoding 8 (0,0), encoding 9 (0,0), encoding 10 (0,0), encoding 11 (0,0)

Uncombined memory, row 0 column 2, code 1 (0, 2), code 2 (0, 2), code 3 (0, 2), code 4 (0, 2), code 5 (0, 2), Code 6 (0, 2), code 7 (0, 2), code 8 (0, 2), Code 9 (0, 2), code 10 (0, 2), code 11 (0, 2)

Unmerge memory, row 0 column 3, code 1 (0, 3), code 2 (0, 3), code 3 (0, 3), code 5 (0, 3), code 6 (0, 3), Encoding 7 (0, 3), encoding 9 (0, 3), encoding 10 (0, 3), encoding 11 (0, 3)

Unmerge memory, row 0 column 4, code 0 (0, 4), code 2 (0, 4), code 3 (0, 4), code 4 (0, 4), code 5 (0, 4), Code 6 (0, 4), code 7 (0, 4), code 8 (0, 4), code 9 (0, 4), code 10 (0, 4), code 11 (0, 4)

Uncombined memory, row 0 column 7, code 0 (0,7), code 1 (0,7), code 2 (0,7), code 3 (0,7), code 7 (0,7), Encoding 8 (0, 7), encoding 9 (0, 7), encoding 10 (0, 7), encoding 11 (0, 7)

Unmerge memory, row 0 column 8, code 0 (0,8), code 3 (0,8), code 4 (0,8), code 5 (0,8), code 6 (0,8), Encoding 7 (0, 8), encoding 8 (0, 8), encoding 9 (0, 8), encoding 11 (0, 8)

Unconsolidated memory, row 0 column 23, code 0 (0, 23), code 1 (0, 23), code 2 (0, 23), code 3 (0, 23), code 4 (0, 23), Encoding 5 (0, 23), encoding 6 (0, 23), encoding 7 (0, 23), encoding 8 (0, 23), encoding 9 (0, 23), encoding 10 (0, 23), encoding 11 (0,23)

Unmerge memory, row 1 column 0, code 0 (1,0), code 1 (1,0), code 2 (1,0), code 3 (1,0), code 5 (1,0), Encoding 6 (1, 0), encoding 7 (1, 0), encoding 8 (1, 0), encoding 9 (1, 0), encoding 10 (1, 0), encoding 11 (1, 0)

Uncombined memory, row 1 column 1, code 1 (1, 1), code 2 (1, 1), code 3 (1, 1), code 4 (1, 1), code 5 (1, 1), Code 6 (1, 1), code 7 (1, 1), code 8 (1, 1), code 9 (1, 1), code 10 (1, 1), code 11 (1, 1)

Unconsolidated memory, row 1 column 2, code 0 (1, 2), code 1 (1, 2), code 2 (1, 2), code 3 (1, 2), code 5 (1, 2), Code 6 (1, 2), code 7 (1, 2), code 9 (1, 2), code 10 (1, 2), code 11 (1, 2)

Uncombined memory, row 1 column 4, code 0 (1, 4), code 1 (1, 4), code 2 (1, 4), code 3 (1, 4), code 4 (1, 4), Code 5 (1, 4), code 6 (1, 4), code 7 (1, 4), Code 8 (1, 4), code 9 (1, 4), code 10 (1, 4), code 11 (1, 4)

Uncombined memory, row 1 column 5, code 0 (1, 5), code 3 (1, 5), code 6 (1, 5), code 7 (1, 5), code 9 (1, 5), Code 10 (1, 5), code 11 (1, 5)

Unconsolidated memory, row 1 column 7, code 0 (1,7), code 2 (1,7), code 3 (1,7), code 4 (1,7), code 5 (1,7), Code 6 (1, 7), code 7 (1, 7), code 9 (1, 7), code 10 (1, 7), code 11 (1, 7)

Uncombined memory, row 1 column 8, code 0 (1, 8), code 1 (1, 8), code 2 (1, 8), code 3 (1, 8), code 4 (1, 8), Code 7 (1, 8), code 10 (1, 8), code 11 (1, 8)

Uncombined memory, row 1 column 22, code 0 (1, 22), code 1 (1, 22), code 2 (1, 22), code 3 (1, 22), code 4 (1, 22), Code 5 (1, 22), code 6 (1, 22), code 7 (1, 22), code 8 (1, 22), code 9 (1, 22), code 10 (1, 22), code 11 (1,22)

Uncombined memory, row 1 column 23, code 0 (1, 23), code 1 (1, 23), code 2 (1, 23), code 3 (1, 23), code 4 (1, 23), Code 5 (1, 23), code 6 (1, 23), code 7 (1, 23), code 8 (1, 23), code 9 (1, 23), code 10 (1, 23), code 11 (1,23)

Uncombined memory, row 2 column 0, code 0 (2,0), code 1 (2,0), code 2 (2,0), code 3 (2,0), code 4 (2,0), Encoding 5 (2,0), encoding 6 (2,0), encoding 7 (2,0), encoding 9 (2,0), encoding 10 (2,0), encoding 11 (2,0)

Unconsolidated memory, row 2 column 1, code 1 (2, 1), code 2 (2, 1), code 3 (2, 1), code 5 (2, 1), code 6 (2, 1), Code 7 (2, 1), code 8 (2, 1), code 9 (2, 1), code 10 (2, 1), code 11 (2, 1)

Uncombined memory, row 2 column 2, code 1 (2, 2), code 2 (2, 2), code 3 (2, 2), code 4 (2, 2), code 5 (2, 2), Code 6 (2, 2), code 7 (2, 2), code 9 (2, 2), code 10 (2, 2), code 11 (2, 2)

Uncombined memory, row 2 column 3, code 1 (2, 3), code 2 (2, 3), code 3 (2, 3), code 5 (2, 3), code 6 (2, 3), Code 7 (2, 3), code 8 (2, 3), code 9 (2, 3), code 10 (2, 3), code 11 (2, 3)

Unconsolidated memory, row 2, column 4, code 0 (2, 4), code 2 (2, 4), code 3 (2, 4), code 4 (2, 4), code 5 (2, 4), Code 6 (2, 4), code 7 (2, 4), code 8 (2, 4), code 9 (2, 4), code 10 (2, 4), code 11 (2, 4)

Uncombined memory, row 2 column 8, encoding 0 (2, 8), encoding 2 (2, 8), encoding 3 (2, 8), encoding 4 (2, 8), encoding 6 (2, 8), Code 7 (2, 8), code 8 (2, 8), code 10 (2, 8), code 11 (2, 8)

Uncombined memory, row 2 column 21, code 0 (2, 21), code 1 (2, 21), code 2 (2, 21), code 3 (2, 21), code 4 (2, 21), Code 5 (2, 21), code 6 (2, 21), code 7 (2, 21), code 8 (2, 21), code 9 (2, 21), code 10 (2, 21), code 11 (2,21)

Uncombined memory, row 2 column 22, code 0 (2, 22), code 1 (2, 22), code 2 (2, 22), code 3 (2, 22), code 4 (2, 22), Code 5 (2, 22), code 6 (2, 22), code 7 (2, 22), code 8 (2, 22), code 9 (2, 22), code 10 (2, 22), code 11 (2,22)

Uncombined memory, row 3 column 0, code 0 (3,0), code 1 (3,0), code 2 (3,0), code 3 (3,0), code 4 (3,0), Encoding 5 (3, 0), encoding 6 (3, 0), encoding 7 (3, 0), encoding 8 (3, 0), encoding 9 (3, 0), encoding 10 (3, 0), encoding 11 (3,0)

Uncombined memory, row 3 column 1, code 0 (3, 1), code 1 (3, 1), code 2 (3, 1), code 3 (3, 1), code 5 (3, 1), Code 6 (3, 1), code 7 (3, 1), code 9 (3, 1), code 10 (3, 1), code 11 (3, 1)

Uncombined memory, row 3 column 2, code 1 (3, 2), code 2 (3, 2), code 3 (3, 2), code 5 (3, 2), code 6 (3, 2), Code 7 (3, 2), code 9 (3, 2), code 10 (3, 2), code 11 (3, 2)

Uncombined memory, row 3 column 3, code 0 (3, 3), code 2 (3, 3), code 3 (3, 3), code 4 (3, 3), code 5 (3, 3), Code 6 (3, 3), code 7 (3, 3), code 9 (3, 3), code 10 (3, 3), code 11 (3, 3)

Uncombined memory, row 3 column 4, code 0 (3, 4), code 1 (3, 4), code 2 (3, 4), code 3 (3, 4), code 4 (3, 4), Code 5 (3, 4), code 6 (3, 4), code 7 (3, 4), Code 8 (3, 4), code 10 (3, 4), code 11 (3, 4)

Unconsolidated memory, row 3 column 5, code 0 (3, 5), code 2 (3, 5), code 3 (3, 5), code 5 (3, 5), code 6 (3, 5), Code 7 (3, 5), code 8 (3, 5), code 9 (3, 5), code 10 (3, 5), code 11 (3, 5)

Uncombined memory, row 3 column 8, code 0 (3, 8), code 1 (3, 8), code 2 (3, 8), code 3 (3, 8), code 4 (3, 8), Code 7 (3, 8), code 8 (3, 8), code 9 (3, 8), code 10 (3, 8), code 11 (3, 8)

Uncombined memory, row 3 column 20, code 0 (3, 20), code 1 (3, 20), code 2 (3, 20), code 3 (3, 20), code 4 (3, 20), Encoding 5 (3, 20), encoding 6 (3, 20), encoding 7 (3, 20), encoding 8 (3, 20), encoding 9 (3, 20), encoding 10 (3, 20), encoding 11 (3,20)

Uncombined memory, row 3, column 21, code 0 (3, 21), code 1 (3, 21), code 2 (3, 21), code 3 (3, 21), code 4 (3, 21), Code 5 (3, 21), code 6 (3, 21), code 7 (3, 21), code 8 (3, 21), code 9 (3, 21), code 10 (3, 21), code 11 (3,21)

Uncombined memory, row 4 column 1, code 0 (4, 1), code 1 (4, 1), code 2 (4, 1), code 3 (4, 1), code 5 (4, 1), Code 6 (4, 1), code 7 (4, 1), code 9 (4, 1), code 10 (4, 1), code 11 (4, 1)

Unconsolidated memory, row 4 column 2, code 1 (4, 2), code 2 (4, 2), code 3 (4, 2), code 4 (4, 2), code 5 (4, 2), Code 6 (4, 2), code 7 (4, 2), code 9 (4, 2), code 10 (4, 2), code 11 (4, 2)

Uncombined memory, row 4 column 3, code 1 (4, 3), code 2 (4, 3), code 3 (4, 3), code 6 (4, 3), code 7 (4, 3), Code 9 (4, 3), code 10 (4, 3), code 11 (4, 3)

Unconsolidated memory, row 4, column 4, code 0 (4, 4), code 2 (4, 4), code 3 (4, 4), code 4 (4, 4), code 5 (4, 4), Code 6 (4, 4), code 7 (4, 4), code 8 (4, 4), code 9 (4, 4), code 10 (4, 4), code 11 (4, 4)

Unconsolidated memory, row 4 column 5, code 1 (4, 5), code 2 (4, 5), code 3 (4, 5), code 5 (4, 5), code 6 (4, 5), Code 7 (4, 5), code 8 (4, 5), code 10 (4, 5), code 11 (4, 5)

Uncombined memory, row 5 column 0, code 0 (5,0), code 1 (5,0), code 2 (5,0), code 3 (5,0), code 4 (5,0), Encoding 5 (5,0), encoding 6 (5,0), encoding 7 (5,0), encoding 8 (5,0), encoding 9 (5,0), encoding 10 (5,0), encoding 11 (5,0)

Unconsolidated memory, row 5 column 1, code 1 (5, 1), code 2 (5, 1), code 3 (5, 1), code 4 (5, 1), code 5 (5, 1), Code 6 (5, 1), code 7 (5, 1), code 8 (5, 1), code 9 (5, 1), code 10 (5, 1), code 11 (5, 1)

Unconsolidated memory, row 5 column 2, code 1 (5, 2), code 2 (5, 2), code 3 (5, 2), code 5 (5, 2), code 6 (5, 2), Code 7 (5, 2), code 8 (5, 2), code 9 (5, 2), code 10 (5, 2), code 11 (5, 2)

Uncombined memory, row 5 column 4, code 0 (5, 4), code 1 (5, 4), code 2 (5, 4), code 3 (5, 4), code 5 (5, 4), Code 6 (5, 4), code 7 (5, 4), code 9 (5, 4), code 10 (5, 4), code 11 (5, 4)

Uncombined memory, row 5 column 6, code 1 (5, 6), code 2 (5, 6), code 3 (5, 6), code 5 (5, 6), code 6 (5, 6), Code 7 (5, 6), code 8 (5, 6), code 9 (5, 6), code 11 (5, 6)

Unconsolidated memory, row 5, column 8, encoding 0 (5, 8), code 1 (5, 8), code 2 (5, 8), code 3 (5, 8), code 4 (5, 8), Code 7 (5, 8), code 8 (5, 8), code 11 (5, 8)

Merge memory, code 0 (11, 8), code 1 (2, 5), code 3 (2, 5), code 4 (11, 8), code 6 (2, 5), code 7 (2, 5) ), code 8 (11, 8), code 10 (2, 5), code 11 (2, 5)

Merge memory, code 0 (8, 3), code 1 (1, 3), code 2 (1, 3), code 3 (1, 3), code 4 (8, 3), code 5 (1, 3), code 6 (1, 3), code 7 (1, 3), code 8 (1, 3), code 9 (1, 3), code 10 (1, 3), code 11 (1, 3)

Merge memory, code 0 (4,19), code 1 (4,19), code 2 (4,19), code 3 (3,19), code 4 (4,19), code 5 (4,19 ), code 6 (4, 19), code 7 (3, 19), code 8 (4, 19), code 9 (4, 19), code 10 (4, 19)

Merge memory, code 0 (10,0), code 1 (7,2), code 2 (4,17), code 3 (3,17), code 4 (10,0), code 5 (7,2 ), code 6 (3, 17), code 8 (10, 0), Code 9 (7, 2), code 10 (3, 17), code 11 (3, 17)

Merge memory, code 0 (9,0), code 1 (6,1), code 3 (0,20), code 4 (9,0), code 5 (6,1), code 6 (5,7 ), code 7 (0, 20), code 8 (9, 0), code 9 (6, 1), code 10 (4, 11), code 11 (0, 20)

Merge memory, code 0 (6, 18), code 1 (6, 18), code 2 (2, 18), code 3 (2, 18), code 4 (6, 18), code 5 (6, 18) ), code 6 (2, 18), code 7 (2, 18), code 8 (6, 18), code 9 (6, 18), code 10 (2, 18), code 11 (2, 18)

Merge memory, code 0 (4, 20), code 1 (4, 20), code 2 (4, 20), code 3 (1, 20), code 4 (4, 20), code 5 (4, 20) ), code 6 (4, 20), code 7 (1, 20), code 8 (4, 20), code 9 (4, 20), code 10 (4, 20), code 11 (1, 20)

Merge memory, code 0 (7,0), code 1 (7,0), code 2 (0,18), code 3 (0,18), code 4 (7,0), code 5 (7,0 ), code 6 (0, 18), code 8 (7, 0), code 9 (7, 0), code 10 (0, 18), code 11 (0, 18)

Merge memory, code 0 (11, 13), code 1 (7, 13), code 3 (3, 13), code 4 (11, 13), code 6 (3, 13), code 7 (3, 13 ), code 8 (11, 13), code 9 (7, 13), code 10 (3, 13), code 11 (3, 13)

Merge memory, code 0 (8,0), code 1 (7,1), code 2 (2,16), code 3 (2,16), code 4 (8,0), code 5 (7,1 ), code 6 (2, 16), code 7 (2, 16), code 8 (8, 0), code 9 (7, 1), code 10 (2, 16), code 11 (2, 16)

Merge memory, code 0 (11,0), code 1 (5,3), code 2 (5,3), code 3 (2,19), code 4 (11,0), code 5 (5,3 ), code 6 (5, 3), code 8 (11, 0), code 9 (5, 3), code 10 (5, 3), code 11 (2, 19)

Merge memory, code 0 (6, 17), code 1 (6, 17), code 3 (2, 17), code 4 (6, 17), code 5 (6, 17), code 6 (4, 16 ), code 7 (2, 17), code 8 (6, 17), code 9 (6, 17), code 10 (2, 17), code 11 (2, 17)

Merge memory, code 0 (4,0), code 1 (4,0), code 2 (4,0), code 3 (1,19), code 4 (4,0), code 5 (4,0 ), code 6 (4,0), code 7 (1,19), code 8 (4,0), code 9 (4,0), code 10 (4,0), code 11 (1,19)

Merge memory, code 0 (8, 16), code 1 (0, 16), code 2 (5, 16), code 3 (0, 16), code 4 (8, 16), code 5 (0, 16 ), code 6 (0, 16), code 7 (0, 16), code 8 (8, 16), code 9 (0, 16), code 10 (5, 16), code 11 (0, 16)

Merge memory, code 0 (5,19), code 1 (5,19), code 2 (5,19), code 3 (0,19), code 4 (5,19), code 5 (5,19 ), code 6 (5, 19), code 7 (0, 19), code 8 (5, 19), code 9 (5, 19), code 10 (5, 19), code 11 (0, 19)

Merge memory, code 0 (7, 17), code 1 (7, 17), code 2 (1, 17), code 3 (1, 17), code 4 (7, 17), code 5 (7, 17) ), code 6 (1, 17), code 7 (1, 17), code 8 (7, 17), code 9 (7, 17), code 11 (1, 17)

Merge memory, code 0 (5, 12), code 1 (6, 5), code 2 (5, 12), code 3 (2, 12), code 4 (5, 12), code 5 (5, 12) ), code 6 (2, 12), code 7 (2, 12), code 8 (5, 12), code 9 (2, 12), code 10 (2, 12), code 11 (2, 12)

Merge memory, code 0 (9, 15), code 1 (7, 15), code 3 (2, 15), code 4 (9, 15), code 5 (7, 15), code 6 (5, 15 ), code 7 (2, 15), code 8 (9, 15), code 9 (7, 15), code 10 (5, 15), code 11 (2, 15)

Merge memory, code 0 (11, 12), code 1 (7, 6), code 2 (4, 12), code 3 (3, 1S), code 4 (11, 12), code 5 (7, 6 ), code 6 (4, 12), code 7 (3, 18), code 8 (11, 12), code 9 (4, 12), code 10 (4, 12), code 11 (3, 18)

Merge memory, code 0 (8, 15), code 1 (4, 15), code 2 (3, 15), code 3 (3, 15), code 4 (8, 15), code 6 (3, 15 ), code 7 (3, 15), code 8 (8, 15), code 9 (6, 9), code 10 (4, 15), code 11 (3, 15)

Merge memory, code 0 (9, 2), code 1 (6, 12), code 4 (9, 1), code 5 (6, 12), code 6 (5, 13), code 7 (1, 12) ), code 8 (10, 2), code 9 (6, 12), code 10 (1, 12), code 11 (1, 12)

Merge memory, code 0 (6,0), code 1 (6,0), code 2 (0,17), code 3 (0,17), code 4 (6,0), code 5 (6,0 ), code 6 (5, 17), code 7 (0, 17), code 8 (6, 0), code 9 (6, 0), code 10 (5, 17)

Merge memory, code 0 (8, 4), code 1 (3, 12), code 2 (3, 12), code 3 (3, 12), code 4 (8, 4), code 5 (3, 12), code 7 (3, 12), code 8 (8, 4), code 9 (7, 14)

Merge memory, code 0 (9, 4), code 1 (1, 15), code 2 (1, 15), code 3 (1, 15), code 4 (9, 4), code 5 (1, 15 ), code 6 (1, 15), code 7 (1, 19), code 8 (9, 4), code 9 (1, 15), code 11 (1, 15)

Merge memory, code 0 (0, 12), code 1 (0, 12), code 2 (5, 10), code 3 (0, 12), code 4 (0, 12), code 6 (0, 12) ), code 7 (0, 12), code 8 (0, 12), code 9 (5, 10), code 10 (5, 10), code 11 (0, 12)

Merge memory, code 0 (10, 4), code 2 (0, 15), code 3 (0, 15), code 4 (10, 4), code 5 (0, 15), code 7 (0, 15 ), code 8 (10, 4), code 9 (0, 15), code 10 (0, 15)

Merge memory, code 0 (5,18), code 1 (5,18), code 2 (5,18), code 3 (1,18), code 4 (5,18), code 5 (5,18 ), code 6 (5, 18), code 7 (1, 18), code 8 (5, 18), code 9 (5, 18), code 10 (5, 18)

Merge memory, code 0 (10, 13), code 1 (6, 7), code 2 (1, 13), code 3 (1, 13), code 4 (10, 13), code 5 (1, 13 ), code 6 (1, 13), code 7 (1, 13), code 8 (10, 13), code 9 (6, 7), code 11 (1, 13)

Merge memory, code 0 (7, 16), code 1 (7, 16), code 3 (1, 16), code 4 (7, 16), code 5 (7, 16), code 8 (7, 16 ), code 9 (7, 16), code 10 (1, 16)

Merge memory, code 0 (11, 4), code 1 (2, 13), code 2 (2, 13), code 3 (2, 13), code 4 (11, 4), code 5 (2, 13 ), code 7 (2, 13), code 8 (11, 4), code 9 (2, 13)

Merge memory, code 0 (9, 8), code 1 (3, 16), code 2 (3, 16), code 3 (3, 16), code 4 (10, 5), code 5 (3, 16 ), code 7 (3, 16), code 8 (9, 8), code 9 (3, 16), code 11 (3, 16)

Merge memory, code 0 (10, 1), code 1 (4, 13), code 3 (3, 7), code 4 (10, 1), code 5 (4, 13), code 6 (3, 7 ), code 7 (3, 7), code 8 (8, 1), code 9 (4, 13), code 10 (4, 13), code 11 (3, 7)

Merge memory, code 0 (10, 14), code 1 (6, 14), code 3 (2, 14), code 4 (10, 1), code 5 (6, 14), code 6 (2, 14 ), code 7 (2, 14), code 8 (10, 14), code 9 (2, 14), code 11 (2, 14)

Merge memory, code 0 (11, 11), code 1 (4, 7), code 2 (4, 7), code 3 (3, 11), code 4 (3, 11), code 5 (4, 7 ), code 6 (3, 11), code 7 (3, 11), code 8 (3, 11), code 9 (3, 11), code 11 (3, 11)

Merge memory, code 0 (9, 14), code 2 (4, 14), code 3 (1, 14), code 4 (9, 14), code 5 (4, 14), code 6 (4, 14 ), code 7 (1, 14), code 8 (9, 14), code 10 (1, 14)

Merge memory, code 0 (2, 11), code 1 (2, 11), code 2 (2, 11), code 3 (2, 11), code 4 (9, 11), code 5 (2, 11 ), code 7 (2, 11), code 8 (6, 11)

Merge memory, code 0 (11, 5), code 1 (0, 14), code 2 (5, 14), code 3 (0, 14), code 4 (9, 6), code 5 (5, 14), code 6 (0, 14), code 7 (0, 14), code 8 (9, 5), code 9 (5, 14), code 10 (0, 14), code 11 (0, 14)

Merge memory, code 0 (7, 11), code 1 (7, 11), code 2 (0, 13), code 3 (0, 13), code 4 (11, 6), code 5 (7, 11 ), code 7 (0, 13), code 8 (11, 6), code 9 (7, 11), code 10 (0, 13), code 11 (0, 13)

Merge memory, code 0 (6, 4), code 1 (3, 14), code 2 (3, 14), code 3 (3, 14), code 4 (6, 4), code 5 (6, 4 ), code 7 (3, 14), code 8 (6, 4), code 10 (3, 14), code 11 (3, 14)

Merge memory, code 0 (10,6), code 1 (5,11), code 2 (3,10), code 3 (3,10), code 4 (11,7), code 5 (7,3 ), code 6 (5, 11), code 7 (3, 10), code 8 (7, 3), code 9 (7, 3), code 10 (5, 11), code 11 (3, 10)

Merge memory, code 0 (7,10), code 1 (6,10), code 3 (0,10), code 4 (6,10), code 6 (0,10), code 7 (0,10 ), code 8 (11, 10), code 9 (6, 10)

Merge memory, code 0 (10,7), code 2 (1,11), code 3 (1,11), code 4 (7,5), code 5 (7,5), code 6 (1,11 ), code 7 (1, 11), code 8 (7, 7), code 9 (1, 11), code 11 (1, 11)

Combined memory, code 0 (2, 10), code 2 (2, 10), code 3 (2, 10), code 4 (2, 10), code 5 (2, 10), code 6 (2, 10) ), code 7 (2, 10), code 8 (10, (3, 6), code 4 (8, 8), code 6 (3, 6), code 7 (3, 6), code 8 (8, 8), code 9 (3, 6), code 10 (3, 6), code 11 (3, 6)

Merge memory, code 1 (2, 9), code 2 (5, 5), code 3 (2, 9), code 4 (5, 5), code 6 (5, 5), code 7 (2, 9 ), code 8 (2, 9), code 9 (5, 5), code 10 (5, 5), code 11 (2, 9)

Merge memory, code 0 (6, 3), code 1 (6, 3), code 2 (0, 6), code 3 (0, 6), code 4 (6, 3), code 5 (6, 3 ), code 6 (0, 6), code 7 (0, 6), code 9 (6, 3), code 10 (0, 6), code 11 (0, 6)

Merge memory, code 0 (4, 8), code 1 (2, 7), code 2 (2, 7), code 3 (2, 7), code 4 (4, 8), code 5 (2, 7) ), code 6 (4, 8), code 7 (2, 7), code 8 (4, 8), code 10 (2, 7), code 11 (2, 7)

Merge memory, code 0 (7,8), code 1 (7,8), code 3 (2,6), code 4 (7,8), code 5 (7,8), code 6 (2,6 ), code 7 (2, 6), code 8 (7, 8), code 9 (2, 6), code 10 (2, 6) code 11 (2, 6)

Merge memory, code 0 (7, 4), code 1 (7, 4), code 3 (3, 9), code 4 (7, 4), code 5 (3, 9), code 6 (3, 9 ), code 7 (3, 9), code 8 (7, 4), code 9 (7, 4), code 10 (3, 9), code 11 (3, 9)

Merge memory, code 0 (6, 8), code 1 (0, 5), code 2 (0, 5), code 3 (0, 5), code 4 (6, 8), code 5 (6, 8 ), code 6 (0, 5), code 7 (0, 5), code 8 (6, 8), code 9 (6, 8), code 10 (0, 5), code 11 (0, 5)

Merge memory, code 0 (10,8), code 1 (0,1), code 2 (0,1), code 3 (0,1), code 4 (10,8), code 5 (0,1 ), code 6 (0, 1), code 7 (0, 1), code 8 (10, 8), code 9 (0, 1), code 10 (0, 1), code 11 (0, 1)

600‧‧‧LDPC decoding function

610‧‧‧Analog Front End (AFE)

611‧‧‧Discrete time signal

620‧‧‧Metric Generator

621‧‧‧ bit metric and/or log likelihood ratio (LLR)

630‧‧‧ bit engine

632‧‧‧Soft Information

635‧‧‧ Iterative decoding processing

640‧‧‧Check engine

641‧‧‧Check side messages

650‧‧‧hard limiter

651‧‧‧hard/best estimate

660‧‧‧Calculator

Claims (10)

A decoder for decoding a low density parity check encoded signal, wherein the decoder comprises: a plurality of memories; a plurality of bit engines, and each of the plurality of bit engines An engine is used to connect to at least one of the plurality of memories; a plurality of verification engines, each of the plurality of verification engines for connecting to the plurality of memories And at least one memory; and a plurality of multiplexers for selectively selecting the plurality of bit engines and the plurality of schools during a decoding process of the first low density parity check coded signal The engine is coupled to the first selected one of the plurality of memories; and selectively, the plurality of bit engines and the plurality of bits during the decoding process of the second low density parity check encoded signal a check engine coupled to the second selected one of the plurality of memories; and wherein: the plurality of memories includes a predetermined number of memories, the predetermined number of memories being used to indicate corresponding plurality of low Multiple low density parity encoding a plurality of non-zero sub-matrices in the parity check matrix; the decoder is configured to decode the first low-density parity-check encoded signal, the first low-density parity-check encoded signal corresponding to the plurality of low a first low density parity check matrix of the density parity check matrix to generate a best estimate of the bit encoded within the first low density parity check encoded signal; and the decoder for decoding the second low a density parity check coded signal, the second low density parity check coded signal corresponding to a second low density parity check matrix of the plurality of low density parity check matrices, thereby generating a second low density parity check The best estimate of the encoded bit within the encoded signal. The decoder according to claim 1, wherein the decoders are superimposed on each other A portion of the memory in the plurality of memories is determined by a plurality of non-zero sub-matrices of the plurality of low-density parity check matrices encoded by the plurality of low-density parity check codes. The decoder of claim 1, wherein the first greedy is performed by superimposing a plurality of non-zero sub-matrices in the plurality of low-density parity check matrices corresponding to the plurality of low-density parity check codes, A depth search determines a portion of the memory in the plurality of memories. The decoder of claim 1, wherein the first greedy is performed by superimposing a plurality of non-zero sub-matrices in the plurality of low-density parity check matrices corresponding to the plurality of low-density parity check codes, a depth search to determine a portion of the memory in the plurality of memories; and the first greedy, depth search at least partially considers a column affine metric, the column affine metric representing the first low density parity check matrix The column is connected to at least one other column of the first low density parity check matrix and the columns of the second low density parity check matrix. The decoder of claim 1, wherein the layout of the plurality of memories within the communication device is based on a merge mode, the merge mode being generated by at least partially considering a column affine metric, the column affine The metric represents connectivity of a column in the first low density parity check matrix to at least one other column of the first low density parity check matrix and a column in the second low density parity check matrix. The decoder of claim 1, wherein the plurality of memories comprise a plurality of merged memories, and one of the plurality of merged memories corresponds to the first low-density parity The first non-zero submatrix in the matrix also corresponds to the second non-zero submatrix in the second low density parity check matrix. A decoder for decoding a low density parity check encoded signal, wherein the decoder comprises: a plurality of memories; a plurality of bit engines, and each of the plurality of bit engines An engine is used to connect to at least one of the plurality of memories; a plurality of check engines, each of the plurality of check engines being configured to connect to at least one of the plurality of memories; and a plurality of multiplexers for: when decoding The first low-density parity-check coded signal, in the processing of the bit node, connecting the first selected one of the plurality of bit-level engines to the first selected one of the plurality of memories When decoding the first low density parity check coded signal, connecting a first selected check engine of the plurality of check engines to the plurality of memorys during check node processing The first selected memory; when decoding the second low density parity check encoded signal, connecting the second selected positioning meta engine of the plurality of bit engines to the bit node processing a second selected one of the plurality of memories; and when decoding the second low density parity check coded signal, in a process of verifying node processing, the first of the plurality of check engines Two selected verification engines are connected to the plurality of memories The second selected memory; wherein: the plurality of memories comprise a predetermined number of memories, the predetermined number of memories being used to represent a plurality of low density parity checks corresponding to a plurality of low density parity check codes a plurality of non-zero sub-matrices in the matrix; the decoder is configured to decode the first low-density parity-check encoded signal, the first low-density parity-check encoded signal corresponding to the plurality of low-density parity check matrices a first low density parity check matrix to generate a best estimate of the bit encoded within the first low density parity check encoded signal; and the decoder for decoding the second low density parity check encoded signal, The second low density parity check coded signal corresponds to the second low density parity check matrix of the plurality of low density parity check matrices, thereby generating a bit encoded in the second low density parity check coded signal The best estimate. The decoder of claim 7, wherein the first selected positioning meta engine of the plurality of bit engines is the second selected positioning meta engine of the plurality of bit engines; The first selected verification engine of the plurality of verification engines is the second selected verification engine of the plurality of verification engines. The decoder of claim 7, wherein the first selected positioning meta engine of the plurality of bit engines is all bit engines of the plurality of bit engines; and the plurality of The first selected verification engine of the verification engine is all of the verification engines of the plurality of verification engines. A decoder for decoding a low density parity check encoded signal, wherein the decoder comprises: a plurality of memories; a plurality of bit engines, and each of the plurality of bit engines An engine is coupled to at least one of the plurality of memories; a plurality of verification engines, each of the plurality of verification engines being coupled to at least one of the plurality of memories a memory; and a plurality of multiplexers for: connecting the plurality of bit engines to the plurality of memories during bit node processing during decoding of the first low density parity check encoded signal a first selected memory in the body; when decoding the first low density parity check coded signal, connecting the plurality of check engines to the plurality of memories during check node processing The first selected memory; when decoding the second low density parity check encoded signal, connecting the plurality of bit engines to the first of the plurality of memories during bit node processing Second selected memory; when decoding the second low When the parity of the coded signal, school During the processing of the node, the plurality of check engines are connected to the second selected one of the plurality of memories; when the third low density parity check coded signal is decoded, at the bit node In the process of processing, connecting the plurality of bit engines to a third selected one of the plurality of memories; and processing the check nodes when decoding the third low density parity check coded signals Connecting the plurality of verification engines to the third selected one of the plurality of memories; wherein: the plurality of memories comprises a predetermined number of memories, the predetermined number of The memory is configured to represent a plurality of non-zero sub-matrices in the plurality of low-density parity check matrices corresponding to the plurality of low-density parity check codes; the decoder is configured to decode the first low-density parity-check encoded signals, The first low density parity check encoded signal corresponds to a first low density parity check matrix of the plurality of low density parity check matrices to generate a bit encoded in the first low density parity check encoded signal Best estimate of yuan The decoder is configured to decode the second low density parity check encoded signal, and the second low density parity check encoded signal corresponds to a second low density parity check of the plurality of low density parity check matrices a matrix to generate a best estimate of the bit encoded within the second low density parity check encoded signal; and the decoder for decoding the third low density parity check encoded signal, the third low density The parity encoded signal corresponds to a third low density parity check matrix of the plurality of low density parity check matrices to generate a best estimate of the bits encoded within the third low density parity check encoded signal.