1321935 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種GFSK數位解調器及其訊號同步方 法，尤指一種以數位方式恢復GFSK調變訊號載波同步誤 差之方法與裝置，係針對包含直料位偏移的輸人訊號達 成載波同步之目的。 【先前技術】 按解調器在數據通訊中為重要的—環，其可分為類比 解調态及數位解調器；丨中類比解調技術已經很成熟，但 採用類:匕解調器解調數位調變的資訊時，必須面對兩個問 題· -是必須消除類比解調輸出的直流偏移；其次，則需 使用體積大且昂眚# μ、、者4 貝的類比濾波器在限幅器之前完成所有接 收器的據波。1321935 IX. Description of the Invention: [Technical Field] The present invention relates to a GFSK digital demodulator and a signal synchronization method thereof, and more particularly to a method and apparatus for recovering GGSK modulated signal carrier synchronization error in a digital manner. The input signal including the direct material bit offset achieves the purpose of carrier synchronization. [Prior Art] According to the demodulator, it is important in data communication - ring, which can be divided into analog demodulation state and digital demodulator; 丨 analogy demodulation technology is very mature, but adopts class: 匕 demodulator When demodulating the information of digital modulation, there are two problems that must be faced. - It is necessary to eliminate the DC offset of the analog demodulation output. Secondly, it is necessary to use an analog filter with a large volume and an 眚# μ, 4 Å. Complete the data of all receivers before the limiter.
、位解調器則是在解調之前將類比訊號轉換成為 數位訊號，前述的轉換過程通常可由下列兩種方式實現： 在較低的中頻（丨F)(例如455kHz)對訊號進行採樣； ^ ~帛訊號直接混頻到基帛’但必須同時得到同相 刀1正乂分即l/Q分量）以保留訊號中的所有資訊。 別述IF私樣方法雖然透過數位下變頻技術消除了直流 偏移，但須使㈣護元件以避免受鏡像頻率的干擾，而這 個干擾防護問題在l/Q方法來說則並不存在，目|/〇方法 被廣泛且普遍的；重田 y ，巨丨/Q方法仍然必須消除由混頻弓丨 起的直流準位偏移。 1321935 目刖有一些方法可以用來消除直流偏移，例如直接對 接收到的訊號取平均值，由於數位訊號的正負脈波數量相 同，即可透過該平均的步驟而消除該直流準位成份。但前 述作法僅在理想㈣境下始能成立，因訊號在傳遞過程中 可能因干擾等外在因素致使正負脈波的數量不—定相等。 即使對很長-段時間内的訊號求平均值仍然會有問題，例 如，若檢測的是短的突發訊號，則在數據到達時，所取的 平均值可能還不是最理想的，因此直接對接收的訊號取平 均值，顯然仍存在諸多變數，而未盡周延。 【發明内容】 因此，本發明主要目的在提供一種以數位方式恢復 GFSK調變訊號載波同㈣差及料直流準位t數位解調 器’藉此可有效消除直流準位。 為達成前述目的採取的主要技術手段係令前述數位解 調器包括有： 一數位差分解調器，其輸入端接收具丨/Q分量的輸入 訊號； 一罈頻器，係設於前述數位差分解調器的輸出端上， 5玄頻器具有一輸入端及一輸出端； 減法器，對鑑頻器之輸入及輸出訊號進行訊號相減 處理，獲得一不含直流位準之頻率誤差訊號； 一遞迴運算器，係對減法器送入之頻率誤差訊號執行 遞迴累加運算； 1321935 Λ w=-^: k-n~N-¥\ 由於GFSK解調器將射頻訊號直接混頻到基頻，必定 產生直流分里，則述公式累加接收的訊號再予平均，僅適 用於DC FREE環境，並未將直流準位考量在内，僅屬理The bit demodulator converts the analog signal into a digital signal before demodulation. The above conversion process can usually be implemented in two ways: sampling the signal at a lower intermediate frequency (丨F) (for example, 455 kHz); ^ ~ The signal is directly mixed to the base 'but must also get the in-phase knife 1 positive, ie l/Q component) to retain all the information in the signal. Although the IF private sample method eliminates the DC offset through the digital down-conversion technology, the (four) protection components must be protected from interference by the image frequency, and this interference protection problem does not exist in the l/Q method. The |/〇 method is widely and universally; the heavy field y, the python/Q method still has to eliminate the DC level shift caused by the mixing bow. 1321935 There are some ways to eliminate the DC offset. For example, the average of the received signals is averaged. Since the number of positive and negative pulses of the digital signal is the same, the DC level component can be eliminated by the averaging step. However, the foregoing practice can only be established under the ideal (4) situation. Because the signal may be transmitted in the process, the number of positive and negative pulse waves may not be equal due to external factors such as interference. Even if the signal is averaged over a long period of time, there is still a problem. For example, if a short burst signal is detected, the average value taken may not be optimal when the data arrives, so directly By averaging the received signals, there are obviously many variables that are not exhausted. SUMMARY OF THE INVENTION Accordingly, it is a primary object of the present invention to provide a digitally restored GFSK modulated signal carrier with a (four) difference and a material DC level t digital demodulator, whereby the DC level can be effectively eliminated. The main technical means for achieving the foregoing purpose is that the digital demodulator comprises: a digital differential demodulator, the input end of which receives an input signal having a 丨/Q component; and an octave frequency device which is set in the aforementioned digital difference At the output end of the demodulator, the 5 sine frequency converter has an input end and an output end; the subtractor performs signal subtraction processing on the input and output signals of the discriminator to obtain a frequency error signal without a DC level; A recursive operator performs a recursive accumulation operation on the frequency error signal sent by the subtractor; 1321935 Λ w=-^: kn~N-¥\ Since the GFSK demodulator directly mixes the RF signal to the fundamental frequency, The DC branch must be generated. The formula accumulates the received signal and averages it. It is only applicable to the DC FREE environment. It does not take the DC level into consideration.
論化的作法，無法適用於現實環境，即：NON DC FREE 的環境，勢必因直流準位嚴重影響輸出的結果。 而本發明為解決前述問題，乃提出如第一圖所示之裝 置’其包括有： • ^ 一數位差分解調器（10)，其輸入端接收具丨/Q分量的 輸入訊號，於本實施例中，該數位差分解調器（1〇)係由一 頻率合成器（11)、一相位旋轉器（12)及一減法器（13)組成； 鑑頻器（20)，係設於前述數位差分解調器（1〇)的輸 出端上，該鑑頻器（20)具有一輸入端及一輪出端，為方便 說明，吾人定義數位差分解調器（1〇)輸出至鑑頻器（2 :现马一預定傳送訊號；該鑑頻器（2〇)係用以確認輸出訊 籲 ° _、兩低電位’假設預定傳送訊號為高電位脈波時，經由 錐頻器（2〇)執行硬式決策（hard decision)後即送出一言雷 位脈、、古 _ 间电 右預疋傳送訊被為低電位脈波時，則經由鐘頻器 (2〇)執行硬式決策後即送出一低電位脈波； 係、減法器（30)，具有兩輸入端及一輸出端，兩輸入端 刀別與鏗頻器（20)的輸入端及輸出端連接，以便對預定 ’、訊號與鐘頻器（2〇)的輸出訊號執行相減之運算； ''累加器（40)，具有一輸入端及一輸出端，其輸入端 '減法器（30)輸出端連接； 冑相迴路(50) ’其連接於前述累加 )為一階鎖相迴路，其由一迴路濾波器（51)及一數 =制振㈣52)(咖）組成，其中迴路爐波器（51)輸入端 '、累》十器（4〇)輸出端連接，數值控制振盪器⑻）則與數 位差分解調器（10)中的頻率合成器（11)連接。 、 前述，^執行功能可由下式代表之： 〇〇其中，該N指接收訊號的次數，对幻為數位差分解調 广（1〇)輸出的預傳送訊號，又训為鐘頻器（2〇)之輸出訊 號’亦即’本發明為對每個脈波進行扣除直流準位後，再 進行累加及平均值運算，以取得實際的頻率誤差（Λ)，此 即表不本發明為不含直流準位之頻率誤差，相形之下，當 然較傳統所獲得的效果穩定及精確。 在前述裝置的架構下，前述減法器（30)其將鑑頻器 • (20)輸入端的預定傳送訊號取]減去輸出端的輸出訊號〜闵 ’藉此將預定傳送訊號对幻中所包含的直流準位偏移部分消 除掉’由於僅針對訊號中的直流準位，並非直接對接收訊 號取平均值，故不致發生所取平均值不具代表性而影響運 .算準確性之問題。 又由減法g§(30)送出的訊號將送至遞迴累計器（4〇)以 累加計算出一載波頻率誤差量，再利用鎖相迴路（5〇)回饋 至數位差分解調器（1〇)，由頻率合成器（1彳）、相位旋轉器 (12)等進行頻率誤差更正^ 8 1321935 在實際運作中，考慮訊號收斂速度快慢等因素，可在 負迴授路徑上設置一訊號放大器，亦即為如第一圖中位在 減法器（30)與累加器（40)之間的放大器（K)，其訊號放大 率為K’此K值為一可調整參數，其將影響估計收斂速度 與性能： 如第二圖所示，係揭示在不同的/<值下，載波頻率漂 移 CFO(carrier frequency offset)的變化。 又如第二圖所不，則揭不在不同的/^'值下的估計性能 •影響。 再如第四圖所示，係揭示在不同CF0條件下，DC_ free資料來源之整體傳輸錯誤率（BEr)性能比較。 另如第五圖所示’係揭示在不同Non-DC free資料來 源情形下’本發明與已知技術（平均法）之錯誤率性能差 異（/*為non-DC free data source參數，表示+1所佔的 原始二元資料量比例）。 _ 在前述裝置中，係採用數位方式恢復GFSK調變訊號 的載波頻率誤差，並排除直流準位偏移對輸入訊號的影響 ’而達成載波同步回復之目的。具體技術方面，減法器配 合鑑頻器採迴授訊號消除方式自數位差分解調器輸出訊號 中取出載波頻率誤差量，再使用二階鎖相回路更正頻率誤 差。利用前述技術得有效解決既有技術之問題，並且更易 於達成訊號同步之目的。 【圖式簡單說明】 1321935 第一圖：係本發明之電路方塊圖。 第二圖：係表示本發明參數κ之估計收斂速度影響曲 線圖。（CFO = 0.033 radian/sample) 第三圖：係表示本發明參數κ之估計性能影響曲線圖 。（CF〇=〇.〇33 radian/sample) 第四圖：係表示在不同CF〇條件下，D〇_free資料來 源之整體傳輸錯誤率（BER)性能比較曲線圖。 ’本發明與已知技術（平均: 【主要元件符號說明】 (10)數位差分解調器 (12)相位旋轉器 (20)鑑頻器 (50)鎖相迴路 (52)數值控制振盪器 第五圖：係揭示在不同Non_DC free資料來源情形下 技術（平均法）之錯誤率性能差異比較圖。 (11)頻率合成器 (1 3) (3 0)減法器 (4〇)累加器 (51)迴路濾波器The practice of narration cannot be applied to the real environment, that is, the environment of NON DC FREE is bound to seriously affect the output result due to the DC level. In order to solve the foregoing problems, the present invention provides a device as shown in the first figure, which includes: • a digital differential demodulator (10) whose input terminal receives an input signal having a 丨/Q component, In an embodiment, the digital differential demodulator (1〇) is composed of a frequency synthesizer (11), a phase rotator (12) and a subtractor (13); the discriminator (20) is provided in At the output of the aforementioned digital differential demodulator (1〇), the discriminator (20) has an input terminal and a round output terminal. For convenience of explanation, we define a digital differential demodulator (1〇) output to the frequency discrimination. (2: the current scheduled transmission signal; the discriminator (2〇) is used to confirm the output signal _, two low potentials] assuming that the predetermined transmission signal is a high potential pulse wave, via the cone frequency device (2 〇)After performing a hard decision, a statement is sent, and when the left-hand transmission is a low-potential pulse, the hard decision is performed via the clock (2〇). Sending a low potential pulse wave; system, subtractor (30), having two input ends and one output end, two input end cutters The input end and the output end of the frequency converter (20) are connected to perform a subtraction operation on the output signal of the predetermined ', signal and clock frequency (2〇); ''the accumulator (40) has an input terminal and An output terminal whose input terminal 'subtractor (30) is connected; the 胄 phase loop (50) 'which is connected to the aforementioned accumulation) is a first-order phase-locked loop, which is composed of a loop filter (51) and a number = Vibration suppression (4) 52) (cafe) composition, in which the input of the loop furnace (51) input terminal, the tired ten device (4〇) output terminal, the numerical control oscillator (8)) and the digital differential demodulator (10) The frequency synthesizer (11) is connected. In the above, the ^ execution function can be represented by the following formula: 〇〇 where N refers to the number of times the signal is received, and the pre-transmitted signal of the digital differential differential demodulation (1〇) output is trained as a clock frequency device (2)输出) The output signal 'that is, 'the invention is to deduct the DC level for each pulse wave, and then perform the accumulation and average calculation to obtain the actual frequency error (Λ), which means that the present invention is not The frequency error of the DC level is, in contrast, more stable and accurate than the conventional one. Under the framework of the foregoing apparatus, the subtractor (30) subtracts the output signal of the output terminal from the predetermined transmission signal of the input terminal of the discriminator (20), thereby accommodating the predetermined transmission signal to be included in the illusion. The DC level offset is partially eliminated. Because it only targets the DC level in the signal, it does not directly average the received signal. Therefore, the average value of the received signal is not representative and affects the accuracy of the calculation. The signal sent by the subtraction g§(30) will be sent to the recursive accumulator (4〇) to accumulate a carrier frequency error amount, and then fed back to the digital differential demodulator by the phase-locked loop (5〇). 〇), frequency error correction by frequency synthesizer (1彳), phase rotator (12), etc. ^ 8 1321935 In actual operation, considering the speed of signal convergence, etc., a signal amplifier can be set on the negative feedback path. , that is, the amplifier (K) between the subtractor (30) and the accumulator (40) in the first figure, the signal amplification factor is K', and the K value is an adjustable parameter, which will affect the estimation. Convergence Speed and Performance: As shown in the second figure, the change in carrier frequency offset (CFO) is revealed at different values of < Again, as shown in the second figure, the estimated performance of the different /^' values is not affected. As shown in the fourth figure, the overall transmission error rate (BEr) performance comparison of DC_free data sources under different CF0 conditions is revealed. In addition, as shown in the fifth figure, 'the system reveals the error rate performance difference between the present invention and the known technology (average method) in the case of different Non-DC free data sources (/* is a non-DC free data source parameter, indicating + 1 The proportion of the original binary data amount). _ In the foregoing device, the carrier frequency error of the GFSK modulation signal is recovered by digital means, and the influence of the DC level offset on the input signal is eliminated, and the carrier synchronous reply is achieved. In a specific technical aspect, the subtractor is combined with the discriminator to recover the signal cancellation mode, and the carrier frequency error amount is taken out from the digital differential demodulator output signal, and the second-order phase-locked loop is used to correct the frequency error. The foregoing techniques can effectively solve the problems of the prior art and are more convenient for signal synchronization. BRIEF DESCRIPTION OF THE DRAWINGS 1321935 The first figure is a block diagram of the circuit of the present invention. Fig. 2 is a graph showing the influence of the estimated convergence speed of the parameter κ of the present invention. (CFO = 0.033 radian/sample) Fig. 3 is a graph showing the estimated performance influence of the parameter κ of the present invention. (CF〇=〇.〇33 radian/sample) The fourth figure shows the overall transmission error rate (BER) performance comparison curve of the D〇_free data source under different CF〇 conditions. 'The present invention and known techniques (Average: [Major component symbol description] (10) Digital differential demodulator (12) Phase rotator (20) Discriminator (50) Phase-locked loop (52) Numerically controlled oscillator No. Figure 5: Reveals the error rate performance difference of the technology (average method) under different Non_DC free data sources. (11) Frequency synthesizer (1 3) (3 0) Subtractor (4〇) accumulator (51) Loop filter