JPH05110616A - Automatic interference removing device - Google Patents

Abstract

PURPOSE:To prevent the divergence of control and to remove stably interference by using a digital signal at the input side of the automatic interference removing circuit when a difference between each carrier frequency of a digital modulation signal and that of an analog signal is lower than a threshold level. CONSTITUTION:When a frequency difference between the carrier frequency of a digital modulation signal at a terminal 2 and the carrier frequency of an analog signal at a terminal 1 is smaller than a set frequency, a frequency difference discrimination circuit 37 outputs '0' as a selective signal Sel and the input signal of the automatic interference removing circuit 104 is selected as the output of a switching device 38. Then analog interference appears in a deviation between DC bias voltages from analog/digital conversion circuits 13, 14 the interference is removed by controlling them by DC offset control signals OFFSET (P) and (Q) being the outputs of a DC offset control signal generating circuit 103.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in an interference canceller for digital microwave radio communication. In particular, it relates to an automatic interference canceller using a transversal filter.

[0002]

2. Description of the Related Art In recent digital microwave communication,
Since interleaved transmission has been changed to co-channel transmission for effective frequency use, if the frequency use efficiency is increased in this way, the problem of interference from analog wireless communication (FM interference) arises. To remove this interference, an interference removing means utilizing various transversal filters, for example, is proposed in Japanese Patent Laid-Open No. 62-233943.

A conventional example will be described with reference to FIG. In the figure →
Indicates that it is an N (or ZN: N is an integer) bit digital signal. The digital modulation signal input from the terminal 1 is branched into two and input to the multipliers 3 and 4, respectively, and is orthogonal to the output of the carrier recovery circuit 17 and the carrier whose phase is delayed by π / 2 (90 °) with respect to this output. Synchronous detection is performed, and after removing the harmonic components by the low-pass filters 9 and 10, the data signals of the P and Q channels sent on the transmission side by the analog-to-digital conversion circuits 13 and 14 are erroneous due to analog interference. It is identified and reproduced as a digital signal of P and Q channels. On the other hand, the analog signal which becomes the interference source is input from the terminal 2, is branched into two, and is multiplied by the multipliers 5 and 6.
Is input to the demodulation circuit 100, and quadrature synchronous detection is performed on the carrier whose phase is adjusted by the phase shifter 19 so that it has the same phase as the carrier to be quadrature synchronous detected by the demodulation circuit 100. After removing the harmonic components by the low-pass filters 11 and 12, the analog-digital conversion circuits 15 and 16 are respectively
Quantizes the in-phase component and the quadrature component of the analog signal, which are interference sources. These quantized signals are input to the digital multipliers 21 to 24, and the most significant (Most Significant Bit) bits of these quantized signals are
The quadrant determination signals D _P and D _Q are input to the control signal generation circuit 102 for the automatic interference cancellation circuit. In the digital multipliers 21-24, the control signal generation circuit for the automatic interference cancellation circuit
The in-phase interference control signals R _OP and R _OQ and the quadrature interference control signals I _OP and I _OQ which are the outputs of 102 and the outputs of the analog-digital conversion circuits 15 and 16 are respectively digitally multiplied, and the result is digitally added. Output to device 35 or 36. Digital adder 35 (36) is a digital multiplier 21
And 23 (22 and 24) to the digital adder 33 (34),
Here, it is added to the output of the analog / digital conversion circuit 13 (14). Of the outputs of digital adders 33 and 34,
The next significant bits of the transmitted data signal are input to the control signal generating circuit 102 for the automatic interference canceling circuit as error signals E _P and E _Q , respectively. This error signal E _P and E _Q
Is an amount proportional to the error component including the analog interference component included in the digital modulation signal. The exclusive OR circuits 25 to 28 of the control signal generating circuit 102 for the automatic interference canceling circuit take the respective correlations between these error signals E _P and E _Q and the quadrant decision signals D _P and D _Q, and move up and down. The averaging operation is performed in the counting circuits 29 to 32 for counting, and the in-phase interference control signals R _OP and R _OQ and the quadrature interference control signals I _OP and I _OQ are output, respectively. By controlling the outputs of the digital multipliers 21 to 24 in this manner, the error value of the interference component due to the analog signals included in the digital signals of the digital adders 33 and 34 is minimized in the sense of a square error. Is guaranteed. The outputs of the digital adders 33 and 34 are input to the DC offset control signal generation circuit 103, and the DC offset control signal OF
FSET (P) and (Q) are created. These DC offset control signals OFFSET (P) and (Q) are controlled to optimize the DC offset of the input baseband signals of the analog / digital conversion circuits 13 and 14. Here, the control signal generation circuit 103 for DC offset is
Although it can be located after the digital conversion circuits 13 and 14, the analog-digital conversion circuits 13 and
Since the output of 14 is a digital signal containing an analog interference component, the control is likely to be unstable, and is usually located after the analog interference component is removed, that is, after the digital adders 33 and 34.

[0004]

In such a conventional apparatus, since the error component due to the DC offset shift and the error component due to the analog interference are commonly used, the carrier frequency of the analog interference signal is the carrier frequency of the digital signal. In the vicinity of, the control due to the DC offset deviation and the control for removing the analog interference are in a conflicting state,
There was a drawback that the control diverged.

The present invention eliminates such drawbacks, and provides an automatic interference canceller capable of realizing stable interference cancellation even when the frequency difference between the carrier frequency of a digital modulation signal and the carrier frequency of an analog signal is small. The purpose is to do.

[0006]

According to the present invention, there is provided a first terminal for interfering with a first modulated carrier wave modulated by an analog signal and inputting a second modulated carrier wave modulated by a digital modulated signal, and the above-mentioned first terminal. A second terminal for inputting one modulated carrier,
A first demodulation circuit that performs quadrature synchronous detection on the second modulated carrier and outputs a first quantized signal; and a quadrature synchronous detection on the second modulated carrier in the same phase as the first demodulation circuit. A second demodulation circuit that outputs a second quantized signal by applying the above, an automatic interference removal circuit that removes the second quantized signal from the first quantized signal, and generates a third quantized signal; A first control signal generation circuit that outputs a control signal of the automatic interference cancellation circuit based on the three quantized signals and the second quantized signal, and an offset control signal to the first demodulation circuit based on the given signal In the automatic interference canceller having a second control signal generating circuit, the second quantized signal is input and the frequency difference between the carrier frequency of the first modulated carrier and the carrier frequency of the second modulated carrier is input. Frequency to compare with the threshold A difference discriminating circuit and a switcher for selecting one of the third quantized signal or the first quantized signal based on the comparison result of the frequency difference discriminating circuit and supplying the selected second quantized signal to the second control signal generating circuit. It is characterized by

[0007]

When the frequency difference between the carrier frequency of the digital modulation signal and the carrier frequency of the analog signal falls below the threshold value, the digital signal on the input side of the automatic interference canceling circuit is replaced with DC instead of the digital signal on the output side of the automatic interference canceling circuit. It is given to the offset control signal generation circuit. As a result, even when the frequency difference is small, divergence of control is prevented and stable interference removal is performed.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of this embodiment. In this embodiment, as shown in FIG. 1, a terminal 1 for inputting a second modulated carrier wave which is interfered with a first modulated carrier wave modulated by an analog signal and modulated by a digital modulated signal, and the first modulated carrier wave Terminal 2 for inputting a modulated carrier wave, demodulation circuit 100 for performing quadrature synchronous detection on the second modulated carrier wave and outputting a first quantized signal, and demodulation circuit 100 for the second modulated carrier wave Demodulation circuit 101 that performs quadrature synchronous detection in phase and outputs a second quantized signal, and automatic interference removal circuit that removes the second quantized signal from the first quantized signal to generate a third quantized signal 104, a first control signal generation circuit for outputting a control signal of the automatic interference cancellation circuit 104 based on the third quantized signal and the second quantized signal.
102, and a second control signal generation circuit 103 for outputting an offset control signal to the demodulation circuit 100 based on a given signal, and further, as a feature of the present invention, the second quantized signal is input. The frequency difference determination circuit 37 for comparing the frequency difference between the carrier frequency of the first modulated carrier wave and the carrier frequency of the second modulated carrier wave and the threshold value, and the frequency difference determination circuit 37 based on the comparison result of the frequency difference determination circuit 37. And a switch 38 for selecting either the third quantized signal or the first quantized signal and supplying the selected second quantized signal to the second control signal generating circuit 103.

Next, the operation of this embodiment will be described. The operations and signal flows of the demodulation circuits 100 and 101 of the present invention, the control signal generation circuit 102 for the automatic interference elimination circuit, the control signal generation circuit 103 for DC offset, and the automatic interference elimination circuit 104 are the same as those of the conventional example. Is the same. That is, when the frequency difference Δf between the carrier frequency of the digital modulation signal and the carrier frequency of the analog signal is larger than the preset frequency difference, the analog-digital conversion circuits 15 and 16 are provided.
The frequency difference discriminating circuit 37 connected to outputs the reset signal Sel, for example, "1". At this time, the switch 38 causes the control signal generating circuit 103 for DC offset to output the output signal of the automatic interference canceling circuit 104 (that is, the digital adder 33
And the output signals of 34) are output as they are, the operation in this case is the same as that of the conventional example. However, when the frequency difference Δf becomes smaller than the preset frequency, “0” is output as the selection signal Sel, and the output of the switch 38 is the input signal of the automatic interference canceling circuit 104 (that is, the analog-digital conversion circuits 13 and 14). Output signal of). Since the carrier frequency of the analog signal is close to the carrier frequency of the digital modulation signal, analog interference appears as a deviation of the DC bias of the analog-digital conversion circuits 13 and 14, and a control signal generation circuit for DC offset is generated.
The interference can be eliminated by controlling the output DC offset control signals OFFSET (P) and (Q). In addition, the output signal of the automatic interference cancellation circuit 104 (output signals of the digital adders 33 and 34) does not include an error component due to analog interference, and is in the same state as in the steady state. The signal generation circuit 102 also operates in this way.

[0010]

As described above, the present invention provides the control for DC offset when the frequency difference discriminating circuit is provided and the frequency difference between the carrier frequency of the digital modulation signal and the carrier frequency of the analog signal is smaller than a certain frequency difference. Since the digital signal before being input to the automatic interference canceling circuit is selected as the input of the signal generating circuit, there is an effect that the interference can be stably canceled even when the frequency difference is small.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block configuration diagram showing a configuration of a conventional example.

[Explanation of symbols]

 1, 2 Terminals 3 to 6 Multiplier 7, 8 π / 2 Phase shifter 9 to 12 Low-pass filter 13 to 16 Analog-digital conversion circuit 17 Carrier recovery circuit 18 Clock recovery circuit 19, 20 Phase shifter 21 to 24 Digital multiplying circuit 25 to 28 Exclusive logic circuit 29 to 32 Counting circuit 33 to 36 Digital adder 37 Frequency difference determining circuit 38 Switching device 100, 101 Demodulating circuit 102, 103 Control signal generating circuit 104 Automatic interference canceling circuit

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[Procedure amendment]

[Submission date] October 7, 1992

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Correction target item name] All drawings

[Correction method] Change

[Correction content]

[Figure 1]

[Fig. 2]

Claims (1)

[Claims] 1. A first terminal for receiving a second modulated carrier wave, which is interfered with a first modulated carrier wave modulated by an analog signal and modulated by a digital modulated signal, and a first terminal for inputting the first modulated carrier wave. Two terminals, a first demodulation circuit for performing quadrature synchronous detection on the second modulated carrier and outputting a first quantized signal, and the same phase as the first demodulation circuit for the second modulated carrier. Second demodulation circuit that outputs a second quantized signal by performing quadrature synchronous detection with an automatic interference removal circuit that removes the second quantized signal from the first quantized signal to generate a third quantized signal And a first control signal generation circuit that outputs a control signal of the automatic interference cancellation circuit based on the third quantized signal and the second quantized signal, and an offset to the first demodulation circuit based on a given signal. A second control signal that outputs a control signal In an automatic interference canceller having a signal generation circuit, the second quantized signal is input, and a frequency difference between a carrier frequency of the first modulated carrier and a carrier frequency of the second modulated carrier and a threshold value are set. A frequency difference discriminating circuit to be compared, and a switcher for selecting one of the third quantized signal or the first quantized signal based on the comparison result of the frequency difference discriminating circuit and giving it to the second control signal generating circuit. An automatic interference canceller, comprising: