TW389965B - Method for improving reliability of a gate oxide layer by NF3 annealing - Google Patents

Method for improving reliability of a gate oxide layer by NF3 annealing Download PDF

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TW389965B
TW389965B TW87121975A TW87121975A TW389965B TW 389965 B TW389965 B TW 389965B TW 87121975 A TW87121975 A TW 87121975A TW 87121975 A TW87121975 A TW 87121975A TW 389965 B TW389965 B TW 389965B
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Taiwan
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patent application
item
annealing
scope
oxide layer
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TW87121975A
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Chinese (zh)
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Tian-Sheng Jau
Tian-Fu Lei
Tz-Yun Jang
Tzung-Shian Jou
Michael S K Chen
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San Fu Chemical Co Ltd
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Abstract

This invention provides a method for improving reliability of a gate oxide layer by NF3 annealing, which combines the advantages of nitrogen and fluorine to enhance the reliability of the gate oxide layer. A polysilicon gate is annealed by using NF3 to produce Si-F and Si-N bonding at the Si/SiO2 interface. Such stronger bonding replaces the weaker bonding such as Si-H and Si-OH to enhance the reliability of the oxide layer.

Description

Λ7 137 經濟部中央樣準局員工消費合作社印製 五、發明説明 ( 1 ) « 1 1 C 發 明 之 範 圍 ] 1 ] 本 發 明 係 關 於 一 種 改 善 閘 極 氧 化 層 可 靠 度 的 方 法,特別 /--V I 是 利 用 三 氟 化 氮 (NF3 )對閘極退火處理的製程 以降低閘 請 £ 1 1 閲 | 極 漏 電 流 的 方 法 〇 靖 背 1 面 I r t 發 明 之 背 景 ] 之 注 1 意 1 I 隨 著 半 導 體 元 件 的 縮 小 (S c a 1 e d 0 W η) * 閘 極 氧 化層 事 項 1 1 I (S at e 0 X id e ) 的 可 靠 度 也 變 得 更 為 重 要 * 如 何 獲 得高可靠 填 寫 (< 度 的 閘 極· 氧 化 層 就 變 成 當 今 最 重 要 的 問 題 0 閘 極 (g a t e )漏 本 頁 '—' 1 | 電 流 (1 e a k a g e C U Γ Γ e η t ) 是 一 個 判 斷 閘 極 氧 化 層 優劣的主 1 1 要 因 素 9 尤 其 是 在 FN 穿 透 (F -N t u η n e 1 i n g )前低電場下的 1 1 漏 電 流 0 因 此 如 何 得 到 一 個 低 漏 電 流 的 閛 極 氧 化層便成 1 訂 為 當 今 主 要 的 問 題 〇 1 1 百 前 有 幾 項 技 術 可 增 進 閘 極 氧 化 層 的 品 質 例 如,在形 1 I 成 氧 化 層 的 同 時 通 入 少 量 的 氟 (F) 使其與氧氣同時在矽 晶 圓 上 反 pflg 應 又 如 使 用 氮 離 子 佈 植 (i on 1 扭P 1 a n t a t ί ο η ) 1 Γ 在 多 晶 矽 閛 極 (P 〇 1 y - Si -g at e ) 對 於 閘 極 氧 化 層 的品質也 fj 有 所 改 善 0 ;( 而 就 另 一 方 面 來 說 在 深 次 微 米 的 製 程 中 如 何減低閘 1 1 I 極 的 電 阻 也 是 — 個 重 要 的 翮 鐽 〇 傳 統 的 鈦 矽 化 物 (Ti- 1 1 si I i c 1 d e )雖可以有效的降低閘極電阻 ,但其在閘極線寬 1 1 變 窄 後 » 其 電 阻 值 也 會 隨 之 而 變 大 〇 鈷 矽 化 物 (C 0 一 1 1 si I ί C 1 d e )是- -個收代的方法 因為鈷矽化物的電阻值不 1 1 會 因 線 寬 的 變 窄 而 麥 大 > 但 鈷 矽 化 物 又 存 在 著 另 一個問題 1 1 I y 其 漏 電 流 太 大 〇 1 1 本紙張尺度適用中國國家標準(CNS ) A4規格(210X 297公漦) Λ7 B7 五、發明説明(2 ) 〔發明之目的與概述〕 本發明之目的在於,提供一種改善閘極氧化層可靠度的 方法,特別是利用三氟化氮(N F 3)對閘極氧化層做退火處 理的製程,其可顯著改善閘極氧化層的漏電流及崩潰電場。 本發明之另一目的在於,提供一種改善閛極氧化層可靠 度的方法*特別是利用三氟化氮(N F 3 )對閘極氧化層做退 火處理的製程*其可有效減少因形成閘極鈷矽化物而來的 漏電流。 本發明之Μ三氟化氮退火處理製程改善閘極氧化層可靠 度之方法,係一項结合氮、氟儍點的技術來改善閛極氧化 層的可靠度,其係Μ三氟化氮(N F 3)對多晶矽(ρ ο 1 y -S ί )閘 極作退火(a η n e a 1 i η趵處理,使氟化矽(S i -F )與氮化矽 (S i - N )的鏈结在二氧化矽與矽晶圓的界面(S i 0 2 / S i interface)中產生,此種較強的鍵结會取代較弱的_结, 例如氫化矽(S i - Η )與氫氧化矽(S i -Ο Η ),而使得氧化層的 可靠度增強。 〔附圖之簡要說明〕 經濟部中央榡準局貝工消費合作社印装 (請先閲讀背面之注意事項再填寫本頁) 圖1係為本發明製程之一實施例之試片製作流程圖。 圖2係為不同退火時間的鋁電極試片之崩潰電^場分怖_。 圖3係為不同退火時間的鋁電極試片之漏電课分佈圖。 _ 4係為以三氟化氮退火處理試片之二次離子分佈圖。 圖5係為本發明製程之另一實施例之試片製作流程_。 _ 6係為不同退火時間的鈷矽化物電極試片之崩潰電場 分佈圖。 本紙張又度逋用中國國家標準(CNS ) Α4規格(210Χ297公婊) 5 ΛΊ B7 五、發明説明(3 ) 圖7係為不同退火時間的鈷砂化.物電極試片之漏電流分 佈圖。 〔發明之詳细說明〕 Μ下參照附圖說明本發明之簧施例。 如圖1所示本發明製程之一實施例之試片製作流程圖, 在Ρ型(100)矽晶圓上製作一金氧半電容(HOS capacitor) ,其步驟為:首先,Μ傳統爐管在晶圓上形成一層5000埃 的阻隔氧化層(field oxide),並触刻出一主動區(active region)。其次,在用氮氣稀釋的氧氣下(N2: 02=10: 1) ,肜成一約33埃厚的超薄氧化層(ultra-thin oxide)(該 超薄氧化層的厚度並不限定於3 3埃,其範園可為1 5至7 0埃 ),並用低壓化學氣相沉積法(LPCVD)堆叠一層3000埃的多 晶矽(P〇 I y-S i )。然後,在攝氏620度低壓的環境下,用三 氟化氮(N F 3)對多晶矽做不同時間(5至2 0分鐘)的退火處理 。最後*以鋁做成閘極電極。 經濟部中央標準局貝工消費合作社印装 (請先閲讀背面之注意事項再填寫本頁) 在上述Μ三氟化氮對多晶矽做退火處理的過程中,會有 氟化矽(S i -F)與氮化矽(S i -Ν)的鍵结在二氧化矽與矽晶圓 的界面(S ί 0 z / S i i n t e r f a c e )中產生,此種較強的鍵结會 取代較弱的鏈结,例如氫化矽(S i -Η )與氫氧化矽(S i -0 Η ) ,而使得氧化層的可靠度增強。如圖4所示,經由對三氟 化氮退火處理的試片做二次離子分析(S IMS),可確知在二 氧化矽與矽晶圓的界面有氟與氮的鍵结形成。 圖2及圖3分別為不同退火時間之鋁電極試片的崩潰電場 (breakdown field)及漏電流(leakage current)之統計分 本紙張尺度逋用中國國家標準(CNS ) A4規格(210X 297公釐) 6 五、發明説明(4 」 所 其組 5 , 照圖 圖對如 佈比 Λ7 B7 皆 場 電 〇 潰低 崩 片 其試 片組 試照 的對 理比 處皆 火亦 退流 做 電 氮漏 化其 氟且 三 > 用高 使片 中試 圖 程 流 作 製 片 試 之 例 施 實 一 另 之 程 製 明 發 本 示 及 开 6 鈷圖 以 。 係 同 驟相 步例 後施 最 S 了 一 除前 , 與 中皆 其驟 , 步 餘間 其時 , 火 外退 極同 電不 極為 By tnu ffs 成分 做,’ 矽 圖 其 組 , 照 圖對 佈 比 分 皆 計場 統電 之 潰 流崩 電其 漏片 及試 場的 電 理 漬處 萠火 的退 片做 試氮 極化 電氟 矽三 化用 鈷使 之中 施 之 黃間 此時 在的 mE , 理 又處 。 火 低退 片做 試片 組試 照 極 對電 比矽 皆化 亦鈷 流對 電 氮 漏化 其氟 且三 -* Μ 高 ’ 片中 試例 著 顯 可 確 9 理 處 火 退 做 矽 晶 多 對 。 氮 鐘化 分氟 ο 1 1 三 為K 係 , 件述 條所 化上 佳綜 最 ο 限 度囿 靠 不 可並 的其 層然 化, 氧明 進說 增细 , 詳 流例 電施 漏簧 及及 場圖 電附 潰照 崩參 的已 層雖 化明 氧發 善本 改 所 圍 S $ 利 專 請 申 ο 及園 神範 精之 之 明 明發 發本 本於 依屬 何應 任仍 o f 例改 施修 實及 二 化 述變 上 的 於做 (請先閱讀背面之注意事項再填寫本頁) ,11 經濟部中央標準局負工消費合作社印裝 本紙張尺度適用中國國家標準(CNS ) A4規格(210X 297公f )Λ7 137 Printed by the Consumer Cooperatives of the Central Procurement Bureau of the Ministry of Economic Affairs 5. Description of the invention (1) «1 1 C Scope of the invention] 1] This invention relates to a method for improving the reliability of the gate oxide layer, especially VI It is a process of annealing the gate by using nitrogen trifluoride (NF3) to reduce the gate. 1 1 Read | The method of electrode leakage current. Jing Jing 1 1 I rt Background of the invention] Note 1 I 1 With the semiconductor Reduction of components (S ca 1 ed 0 W η) * Reliability of gate oxide 1 1 I (S at e 0 X id e) becomes more important * How to obtain highly reliable fill Gate · Oxidation layer becomes the most important problem today 0 Gate (Leak) on this page '—' 1 | Current (1 eakage CU Γ Γ e η t) is a main judge of the quality of gate oxide layer 1 1 factor 9 Especially in the low electric field before FN penetration (F-N tu η ne 1 ing) 1 1 Leakage current 0 So how to get a low-leakage current cathode oxide layer becomes 1 It is a major problem today. A few hundred years ago, there are several technologies that can improve the quality of the gate oxide layer. For example, when a 1 I oxide layer is formed, a small amount of fluorine (F) is passed in to make it anti-pflg on the silicon wafer at the same time as oxygen. Nitrogen ion implantation (i on 1 twist P 1 antat ί η) 1 Γ also improves the quality of the gate oxide layer fj at the polycrystalline silicon wafer (P 〇1 y-Si -g at e); On the other hand, how to reduce the resistance of the gate 1 1 I electrode in the deep sub-micron process is also an important issue. Although traditional titanium silicide (Ti-1 1 si I ic 1 de) can be effective Reduce the gate resistance, but after the gate line width 1 1 becomes narrower »its resistance value will also increase accordingly. Cobalt silicide (C 0-1 1 si I ί C 1 de) is-a method of replacement because the resistance value of cobalt silicide is not 1 1 because of the narrowing of the line width. There is another problem 1 1 I y whose leakage current is too large. 0 1 1 This paper size is applicable to Chinese National Standard (CNS) A4 specification (210X 297 cm) Λ7 B7 V. Description of the invention (2) [Objective of the invention and [Summary] The purpose of the present invention is to provide a method for improving the reliability of the gate oxide layer, especially the process of annealing the gate oxide layer by using nitrogen trifluoride (NF 3), which can significantly improve the gate oxide layer. Leakage current and collapse electric field. Another object of the present invention is to provide a method for improving the reliability of the gate oxide layer. * Especially, the process of annealing the gate oxide layer by using nitrogen trifluoride (NF 3) * can effectively reduce the gate formation. Leakage current from cobalt silicide. The method for improving the reliability of the gate oxide layer by the M nitrogen trifluoride annealing process of the present invention is a technology combining nitrogen and fluorine stupid points to improve the reliability of the rubidium oxide layer, which is M nitrogen trifluoride ( NF 3) Annealing (a η nea 1 i η) gates of polycrystalline silicon (ρ ο 1 y -S) to make the chain of silicon fluoride (S i -F) and silicon nitride (S i-N) The junction is generated at the interface between silicon dioxide and silicon wafer (S i 0 2 / Si interface). This stronger bond will replace the weaker junction, such as silicon hydride (S i-Η) and hydrogen. Silicon oxide (S i -〇 Η), which makes the reliability of the oxide layer enhanced. [Brief description of the drawing] Printed by the Shellfish Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the precautions on the back before filling this page) ) Figure 1 is a flow chart of test piece production according to an embodiment of the process of the present invention. Figure 2 is a breakdown electric field distribution of aluminum electrode test pieces with different annealing times. Figure 3 is an aluminum electrode with different annealing times. Distribution diagram of the leakage course of the test piece. _ 4 is the secondary ion distribution diagram of the test piece annealed with nitrogen trifluoride. Figure 5 is another part of the process of the present invention. The production process of the test piece in the embodiment _. _ 6 is the breakdown electric field distribution chart of cobalt silicide electrode test pieces with different annealing times. This paper is again using the Chinese National Standard (CNS) A4 size (210 × 297 mm) 5 ΛΊ B7 V. Description of the invention (3) Figure 7 shows the leakage current distribution diagram of cobalt sanding and electrode test pieces with different annealing times. [Detailed description of the invention] The following describes the spring embodiment of the present invention with reference to the drawings. As shown in FIG. 1, a test piece manufacturing flowchart of an embodiment of the manufacturing process of the present invention, a metal-oxygen half capacitor (HOS capacitor) is fabricated on a P-type (100) silicon wafer. The steps are as follows: first, a traditional furnace tube A layer of 5000 angs of field oxide was formed on the wafer, and an active region was etched. Secondly, under oxygen diluted with nitrogen (N2: 02 = 10: 1), it was formed into a About 33 angstroms of ultra-thin oxide (the thickness of the ultra-thin oxide is not limited to 33 angstroms, and its range can be 15 to 70 angstroms), and low pressure chemical vapor deposition is used (LPCVD) stack a layer of 3000 angstroms of polycrystalline silicon (PoI yS i). Then, at 620 ° C In a low-pressure environment, polycrystalline silicon is annealed with nitrogen trifluoride (NF 3) at different times (5 to 20 minutes). Finally * the gate electrode is made of aluminum. Printing (please read the precautions on the back before filling this page) During the annealing process of polycrystalline silicon by the above M trifluoride, there will be silicon fluoride (S i -F) and silicon nitride (S i- Ν) bond is generated in the interface between silicon dioxide and silicon wafer (S0 0 / Si interface), this stronger bond will replace the weaker link, such as silicon hydride (S i -Η ) And silicon hydroxide (S i -0 Η), so that the reliability of the oxide layer is enhanced. As shown in Figure 4, by performing secondary ion analysis (S IMS) on the annealed test piece of nitrogen trifluoride, it was confirmed that a bond between fluorine and nitrogen was formed at the interface between the silicon dioxide and the silicon wafer. Figures 2 and 3 are statistics of the breakdown field and leakage current of the aluminum electrode test pieces with different annealing times, respectively. The paper size uses the Chinese National Standard (CNS) A4 specification (210X 297 mm). ) 6 V. Description of the invention (4) All of its group 5, according to the picture, Rubobi Λ7 B7 are all electric field. The low-disintegration tablets of the test group of the test group are all fired and also flow back to do electric nitrogen. Leak its fluorine and three > Use the example of the high-level film to try to make a production test for the implementation of a different procedure to make the instructions and open the 6 cobalt map. After the same step as the example, apply the S division Previously, it was all in the middle, and in the meantime, the outside of the fire was not the same as the By tnu ffs composition, and the 'silicon map' group, according to the picture, the cloth score was calculated by the field power failure. The missing piece and the fire-resistant strip of the test site are tested for nitrogen polarization, electrofluorine, silicon, and silicon. The cobalt is used to make Zhongshi Zhihuang's mE at this time, and the process is again. Group test photos Nitrogen leaks its fluorine and the three- * Μ high 'test specimens are significantly confirmed. 9 treatments have been made to retreat and make silicon crystals. Nitrogen is divided into fluorine. 1 1 The three are K series. The best combination is the limit, which depends on the incompatibility of the layers. The oxygen level is increased, and the detailed examples of electrical leakage leakage and field maps are included. Please apply for the change of S $ profit, and send the copy of the garden god Fan Jingzhi's copy clearly to the role of which the role should be based on the modification and implementation of the two changes (please read the note on the back first) Please fill in this page again for details), 11 The paper standard printed by the Central Bureau of Standards of the Ministry of Economic Affairs and Consumer Cooperatives applies the Chinese National Standard (CNS) A4 specification (210X 297 male f)

Claims (1)

經濟部中央梂率局貝工消費合作社印袈 A8 B8 C8 D8 六、申請專利範圍 1. 一種Μ三氟化氮退火處理製程改善閘極氧化層可靠度 之方法,其具有下列主要步驟: 在晶圓上形成一阻隔氧化層(field oxide),並蝕刻一 主動區(active region): 形成一超薄氧化層(ultra-thin oxide),並堆曼一層多 -晶砂(ρο丨y-Si); Μ三氟化氮(N F 3)對多晶矽作退火處裡;及 形成閘極電極。 2 .如申請專利範圍第1項之方法*其中該超薄氧化層之 厚度係為15至70埃。 3 .如申請專利範圍第1項之方法,其中該多晶矽係Μ低 壓化學氣相沉積(LPCVD)堆叠。 4 .如申請專利範圍第1項之方法,其中該退火處理係於 攝氏620度低壓的環境下進行。 5.如申請專利範圍第1項之方法,其中該退火處理之時 間係為5至2 0分鐘。 6 .如申請專利範圍第1項之方法,其中該閘極電極係為 鋁電極。 7 .如申請專利範圍第1項之方法,其中該閘極電極係為 鈷矽化物電極。 8 .如申請專利範圍第7項之方法,其中該退火處理之時 間係Κ 1 0分鐘為最佳。 本紙張尺度逋用中國國家標準(CNS〉A4规格(210X297公釐) -- i -..... ------ -- - ·— - - I mvl— I- I- I (請先閲讀背面之注意事項再填寫本頁) 訂 1Central Government Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative Co., Ltd. Seal A8 B8 C8 D8 6. Scope of Patent Application 1. A method for improving the reliability of the gate oxide layer by the annealing process of nitrogen trifluoride, which has the following main steps: A field oxide is formed on the circle, and an active region is etched: an ultra-thin oxide is formed, and a layer of poly-crystalline sand (ρο 丨 y-Si) is formed M trifluoride (NF 3) is used for annealing polycrystalline silicon; and a gate electrode is formed. 2. The method according to item 1 of the scope of patent application *, wherein the thickness of the ultra-thin oxide layer is 15 to 70 angstroms. 3. The method of claim 1, wherein the polycrystalline silicon system M is a low pressure chemical vapor deposition (LPCVD) stack. 4. The method according to item 1 of the scope of patent application, wherein the annealing treatment is performed under a low pressure environment of 620 ° C. 5. The method according to item 1 of the patent application range, wherein the annealing time is 5 to 20 minutes. 6. The method according to item 1 of the patent application scope, wherein the gate electrode is an aluminum electrode. 7. The method according to item 1 of the scope of patent application, wherein the gate electrode is a cobalt silicide electrode. 8. The method according to item 7 of the scope of patent application, wherein the annealing time is preferably K 10 minutes. This paper uses the Chinese national standard (CNS> A4 size (210X297 mm)-i -..... ------------I mvl— I- I- I (Please (Read the notes on the back before filling out this page) Order 1
TW87121975A 1998-12-31 1998-12-31 Method for improving reliability of a gate oxide layer by NF3 annealing TW389965B (en)

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US10434749B2 (en) 2003-05-19 2019-10-08 Invensas Bonding Technologies, Inc. Method of room temperature covalent bonding

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* Cited by examiner, † Cited by third party
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US9431368B2 (en) 1999-10-01 2016-08-30 Ziptronix, Inc. Three dimensional device integration method and integrated device
US9564414B2 (en) 1999-10-01 2017-02-07 Ziptronix, Inc. Three dimensional device integration method and integrated device
US10366962B2 (en) 1999-10-01 2019-07-30 Invensas Bonding Technologies, Inc. Three dimensional device integration method and integrated device
US9331149B2 (en) 2000-02-16 2016-05-03 Ziptronix, Inc. Method for low temperature bonding and bonded structure
US9391143B2 (en) 2000-02-16 2016-07-12 Ziptronix, Inc. Method for low temperature bonding and bonded structure
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