TW201830398A - Ternary content addressable memory device for software defined networking and method thereof - Google Patents

Abstract

A ternary content addressable memory (TCAM) device for software defined networking and method thereof is disclosed. By storing M bits of each forwarding rule as a first part into a NAND-Type TCAM, and storing N bits of the same forwarding rule as a second part into a NOR-Type TCAM. Then comparing the M bits of a searching data to the first part to generate a first matching result, comparing the N bits of the searching data to the second part to generate a second matching result after the first matching result is match, and disabling comparing process of the second part when the first matching result is mismatched. The mechanism is help to improve the words length elasticity of the TCAM and to reduce power consumption.

Description

Ternary content addressed memory device and method thereof for software defined network

The invention relates to a ternary content addressing memory device and a method thereof, in particular, a ternary suitable for a software-defined network, which divides a transfer rule into two parts and filters and searches with different types of ternary content-addressed memory. Content addressed memory device and method therefor.

In recent years, with the popularity and boom of the Internet, the amount of traffic and information on the Internet is very impressive. How to effectively manage the growing network has become one of the problems that various vendors are trying to solve. Among them, the technology of Software Defined Networking (SDN) is the most popular.

In simple terms, the traditional network is managed by the local router or switch to manage its own packet forwarding rules, while the software-defined network is to centrally manage the packet forwarding rules. The software can define the network without changing the hardware device. Under the premise, use the program to centrally manage the network and quickly find the best path for packet forwarding. In practical implementation, the software definition network is based on the "OpenFlow" communication protocol, which has long, variable string length, and random dot (Don't care bit) dispersion. However, these characteristics are difficult to apply to the traditional fixed string length of Ternary Content Addressable Memory (TCAM).

In addition, the power consumption of the ternary content-addressed memory is very large, because in each search, each match line (Math Line, ML) is pre-charged, and then the matching error is matched. Line discharge, because the matching line of the error is much more accurate than correct, most of the matching lines are discharged, which results in a large power consumption. Therefore, the conventional ternary content-addressed memory has a problem of large power consumption in addition to the problem of poor elasticity in the length of the string.

In view of this, some manufacturers have proposed to reduce the power consumption of the matching line, and reduce the power consumption by using a low-power matching line. However, this method still cannot change the string length of the search data. In other words, the string length is still short and unchangeable, and has the problem of poor elasticity of the string length.

In summary, it can be seen that in the prior art, there has been a long-standing problem that the ternary content addressed memory has poor power consumption and string length. Therefore, it is necessary to propose an improved technical means to solve this problem.

The invention discloses a ternary content addressed memory device and a method thereof suitable for a software defined network.

First, the present invention discloses a ternary content addressed memory device suitable for a software-defined network. The device includes: a search data temporary register, a pre-filter module, a search module, and a pipeline temporary storage module. The search data register is used for temporarily storing binary search data, and the search data is composed of L bits, wherein L is a positive integer; the pre-filter module is electrically connected to the search data register, and includes a reverse A NAND-Type ternary content addressing memory stores a first portion of each forwarding rule, the first portion being M bits, and comparing the M bits of the search data with the first portion to output a a matching result, wherein M is a positive integer and M<L; the search module is electrically connected to the search data register, and includes at least one inverse OR gate type (NOR-Type) ternary content address memory storage per a second part of the forwarding rule, the second part is N bits, and after the first matching result is matched, the N bits of the search data are compared with the second part of the same forwarding rule to output The second matching result, wherein N is a positive integer and N=LM; the pipeline temporary storage module is electrically connected between the pre-filter module and the search module for pre-charging to reduce the energy delay, and the field effect transistor Electrically connected to the search module, First matching result is a mismatch, the field effect transistor is turned discharged to the ground to disable a second search module.

In addition, the present invention discloses a ternary content addressed memory method suitable for a software-defined network, the steps comprising: temporarily storing binary search data, the search data consisting of L bits, wherein L is a positive integer; NAND-Type ternary content-addressed memory stores a first portion of each forwarding rule, the first portion being M bits, where M is a positive integer and M < L; providing an inverse or gate type (NOR-Type) ternary content addressing memory stores a second portion of each forwarding rule, the second portion being N bits, where N is a positive integer and N = LM; M bits of the search data will be searched The element is compared with the first part to output a first matching result; after the first matching result is matched, pre-charging is performed to reduce the energy delay, and the N bits of the search data are compared with the second part to output the first The result of the two matching, when the first matching result is a mismatch, the conductive field effect transistor is discharged to the ground to disable the comparison of the N bits of the search data with the second portion.

The apparatus and method disclosed in the present invention are as above, and the difference from the prior art is that the present invention stores the M bits of each transfer rule as the first part through the NAND-type ternary content addressed memory, and The N-bit content-addressed memory stores N bits of the same transfer rule as the second part, and then compares the M bits of the search data with the first part to output the first match. As a result, and after the first matching result is a match, the N bits of the search data are compared with the second part to output a second matching result, and when the first matching result is not matched, the second part is disabled. Comparison.

Through the above technical means, the present invention can achieve the technical effect of improving the flexibility of the ternary content addressed memory in the string length and reducing the power consumption.

The embodiments of the present invention will be described in detail below with reference to the drawings and embodiments, so that the application of the technical means to solve the technical problems and achieve the technical effects can be fully understood and implemented.

Before describing the ternary content addressed memory device and method thereof for a software-defined network disclosed in the present invention, the present invention is briefly described. The present invention is an improved ternary content addressed memory in which each memory Two transistors are added to the unit to control the disable/enable control with the mask unit, and the pipeline temporary storage module is used to divide the search of the transfer rule into two stages, and then the matching of the first stage is matched. The second stage of the search comparison, and vice versa, when the first stage of the search is not matched, the second stage search comparison is not needed, and finally the packet is forwarded according to the transfer rules matched in both stages, and the above technology is used to achieve power saving. The effect of the string and the use of multiple sets of pre-filter modules, pipeline buffer modules and search modules, or at least one of them to achieve string length adjustment, will be described in detail later with the schema.

The following is a description of the ternary content-addressed memory device and the method thereof for the software-defined network according to the present invention. Please refer to "FIG. 1", "FIG. 1" for the software-defined network. The device block diagram of the ternary content addressing memory device includes: a search data register 110, a pre-filter module 120, a search module 130, and a pipeline temporary storage module 140. The search data register 110 is configured to temporarily store binary search data, and the search data is composed of L bits, where L is a positive integer. In practical implementation, L can be 144 to 576, that is, the search data can be 144 bits to 576 bits.

The pre-filter module 112 is electrically connected to the search data register 110, and includes a NAND-type ternary content-addressed memory to store a first part of each transfer rule, the first part being M bits. And comparing the M bits of the search material with the first portion to output a first matching result, where M is a positive integer and M < L. In practical implementation, M can be 9 to 36, that is, the first portion can be 9 to 36 bits. In addition, the NAND-Type ternary content-addressed memory has the same bit as the first-part bit. For example, when the first part is 9-bit, the NAND-Type III The meta-content address memory is also 9 bits; when the second part is 18 bits, the NAND-type ternary content address memory is also 18 bits, and so on. Each bit of the NAND-type ternary content-addressed memory is electrically connected to a mask unit for setting the corresponding bit to a random bit (Don't care bit). When the mask unit is set to logic 1, the alignment of the corresponding bits is disabled.

The search module 113 is electrically connected to the search data register 110, and includes a NOR-Type ternary content address memory to store a second portion of each transfer rule, and the second portion is N bits. And, after the first matching result is matched, comparing the N bits of the search data with the second portion of the same forwarding rule to output a second matching result, where N is a positive integer and N=LM. For example, if L is 144 and M is 9, then N is "144-9=135". In practice, N can be 135 to 540, that is, the second part can be 135 to 540. Bit. In addition, the bit of the NOR-Type ternary content-addressed memory is the same as the bit of the second part. For example, when the second part is 135-bit, the inverse or gate type (NOR-Type) The ternary content address memory is also 135 bits; when the second part is 270 bits, the NOR-Type ternary content address memory is also 270 bits, and so on. Similarly, each bit of the NOR-Type ternary content-addressed memory is electrically connected to a mask unit for setting the corresponding bit to a random bit when the mask unit is set to When the logic is 1, the comparison of the corresponding bits is disabled.

The pipeline temporary storage module 140 is electrically connected between the pre-filter module 120 and the search module 130 for pre-charging to reduce the energy delay, and is electrically connected to the search module 130 by a field effect transistor. When the matching result is a mismatch, the field effect transistor is turned on to ground to disable the second search module 130, so that power saving can be achieved. In practical implementation, the pipeline temporary storage module 140 can also add a surge suppression circuit to avoid the glitch, which will be described in detail later with the drawings.

Next, please refer to "Fig. 2", which is a flowchart of a method for applying the ternary content addressed memory method of the software definition network, the steps including: temporarily storing binary search data, the search The data consists of L bits, where L is a positive integer (step 210); the NAND-Type ternary content addressed memory is stored to store the first part of each forwarding rule, the first part being M a bit, where M is a positive integer and M < L (step 220); providing a NOR-Type ternary content addressed memory storing a second portion of each forwarding rule, the second portion being N a bit, where N is a positive integer and N = LM (step 230); comparing the M bits of the search data with the first portion to output a first match result (step 240); After matching, pre-charging is performed to reduce the energy delay, and the N bits of the search data are compared with the second part to output a second matching result, and when the first matching result is not matched, the field-effect transistor discharge is turned on. N to the ground to disable the search for data Yuan and match (step 250) a second portion. Through the above steps, the M-bits of each transfer rule can be stored as the first part through the NAND-type ternary content-addressed memory, and the ternary content by the inverse OR gate type (NOR-Type) The address memory stores N bits of the same transfer rule as the second part, and then compares the M bits of the search data with the first part to output the first matching result, and after the first matching result is matched, The N bits of the search data are compared with the second part to output a second matching result, and when the first matching result is not matched, the comparison of the second part is disabled.

The following is a description of the following examples in conjunction with "3" to "8". Please refer to "3" and "3" for the NAND-Type III of the present invention. A schematic diagram of the circuit of the meta-addressed memory. In practical implementation, the pre-filter module 120 uses a NAND-type ternary content-addressed memory, which uses XNOR logic gate unit 310 (XNOR Cell) to store data, and is matched with a mask unit 320 (Mask Cell). Control is not compared at random bits to save power. The XNOR logic gate unit 310 is internally controlled by the mask unit 320 using two transistors (S-PG), and does not need to be controlled by an external cable. When the mask unit 320 is logic 1, the transistor (S-PG) can be controlled to turn off the XNOR logic gate unit 310, helping to reduce leakage current. Conversely, when the mask unit 320 is logic 0, the XNOR logic gate unit 310 performs conventional operations. It should be additionally noted that the transistor (S-PG) may be an N-channel metal oxide semiconductor field effect transistor (hereinafter referred to as NMOS) or a P-channel metal oxide semiconductor field effect transistor (hereinafter referred to as PMOS).

Please refer to "Fig. 4", which is a circuit diagram of the NOR-Type ternary content addressed memory of the present invention. In practical implementation, the search module 130 uses an inverse OR gate type (NOR-Type) ternary content addressing memory, which uses XOR logic gate unit 410 (XOR Cell) to store data, and is controlled with random mask unit 420 in random bits. Do not compare the yuan to save power. The XOR logic gate unit 410 is internally controlled by the mask unit 420 using two transistors (S-PG) as well, and does not need to be controlled by an external cable. When the mask unit 420 is logic 1, the transistor (S-PG) can be controlled to turn off the XOR logic gate unit 410, helping to reduce leakage current. Conversely, when the mask unit 420 is logic 0, the XOR logic gate unit 410 performs conventional operations. Likewise, the transistor (S-PG) can be either NMOS or PMOS.

As shown in "figure 5", "figure 5" is a circuit diagram of the pre-filter module of the present invention. As previously mentioned, the pre-filter module 120 uses NAND-type ternary content addressed memory that uses XNOR logic gate unit 310 to store data. When MLPre is logic 1, Precharged to a high potential through PMOS P2, the search data is transferred to XNOR logic gate unit 310, and NMOS N1 is turned off to avoid short circuit to ground. When MLPre is logic 0, PMOS P2 stops charging. Assuming that the input data matches the stored transfer rules, the match line will be discharged to ground. The mask unit 320 can always turn on the channel transistor of the pre-filter module 120 regardless of the matching result of the XNOR logic gate unit 310.

Please refer to "Figure 6", "Figure 6" is a circuit diagram of the pipeline temporary storage module of the present invention. Because of the use of OpenFlow routers or switches, the random bits may be discontinuous, ie, appear in the pre-filter module 120, so the present invention uses NAND-Type ternary content addressed memory (NAND) -TCAM) replaces NAND-Type content-addressed memory (NAND-CAM) and can complete the search in one time period. Therefore, in order to improve throughput (Throughput), the present invention adds a pipeline temporary storage module 140 between the pre-filter module 120 and the search module 130, and can divide the search into two stages. Assuming that the first match result output in the first phase is a match, It is a logic 0, and the first matching result is first stored in the left side of the pipeline temporary storage module 140 and then transmitted to the right side, and the PMOS P3 will be turned on to be pre-charged in a subsequent time period. On the contrary, assuming that the first matching result is a mismatch, the PMOS P3 will be turned off until the first matching result output by the pre-filtering module 120 becomes a match again. Among them, PMOS P3 is composed of Control, and . In addition, due to the body effect, the threshold voltage of the NMOS N2 is greater than that of the NMOS N3. Because of the transfer delay of the pipeline temporary storage module 140, the first matching result is slower than the MLPre, in order to avoid unnecessary power consumption caused by the surge. The MLPre can be electrically connected to the NMOS N2 through the surge suppression circuit 610 and the Match is electrically connected to the NMOS N3. In particular, if NMOS N2 and N3 are reversed, because NMOS N2 discharges at a slower rate than NMOS N3, Unnecessary power consumption due to slower NMOS N2 discharge.

Please refer to "Figure 7", "Figure 7" is a circuit diagram of the search module of the present invention. In practical implementation, the search module 130 includes a ML Sense Amplifier (MLSA) with clock gating. Assuming that the matching occurs in the first phase (ie, the first matching result is a match), the ML_NOR will be Precharged to VDD while the match line sense amplifier 710 will be turned on and ML_SENSE will be set to logic 1. Assuming that the second matching result output by the search module 130 is a mismatch, the match line sense amplifier 710 senses a mismatch condition, and once ML_NOR is discharged to the threshold voltage (| Vtp |), ML_SENSE is pulled down to Ground. On the other hand, assuming that the first phase does not match, then the match line sense amplifier 710 will not be turned on to reduce unnecessary power consumption. In other words, unlike the NAND-Type ternary content-addressed memory, the match line is pulled down when all the bits match, and the NOR-Type ternary content-addressed memory is at any position. Discharge the match line to ground with a mismatch. The mask unit 420 can turn off the pull-down transistor of the search module 130.

Please refer to Figure 8 and Figure 8 is a schematic diagram of a circuit for applying different string lengths according to the present invention. Among them, it can be clearly seen that there are four pre-filter modules 120, four search modules 130 and four pipeline temporary storage modules 140. In practice, they can be divided into four groups, each of which has a pre-filter. The module 120, a search module 130 and a pipeline temporary storage module 140 are used to compare the transfer rules within each 144 bits. Even these four groups can be combined into two groups to compare the transfer rules within each 288 (144 * 2) bits, and the four groups can be combined into one group to compare each 576 (144 * 4) bits. The transfer rule implements the case for different string lengths. Specifically, it has three modes, mode one represents four sets of transfer rules for comparing four independent 144-bits from the search data register 110, and uses the displacement register 810 to shift the output to ML_Out. . In mode 2, the first group and the second group, and the third group and the fourth group form another group, so the mode 2 can compare the transfer rules within 288 bits, and the pre-filter module 120 compares the transfer rules. The first 18 (9 * 2) bits, and the matching module 301 then compares the last 270 (135 * 2) bits of the forwarding rule. In mode 3, the four groups are combined into one group for comparing the transfer rules within 576 bits, and the pre-filter module 120 compares the first 36 bits, and is matched by the search module 130 when matching. The last 540 bits of the forwarding rule. The combination can be realized by multiple multiplexers and logic gates as shown in Figure 8, and the mode used by the multiplexer is set. In the mode 2, the wires, multiplexers and logic gates through which the signals pass are used. For example, "Fig. 8" is indicated by a bold black line. In particular, in order to process multiple routing tables simultaneously, the four groups can also be treated as one unit (576 bits) and expanded into multiple units (for example: 64) to form a ternary content addressed memory array (eg :576 * 64), therefore, in mode one, 256 * 144 bits can be compared, in mode two can be compared to 128 * 288 bits, and in mode three can be compared to 64 * 576 bits.

In summary, it can be seen that the difference between the present invention and the prior art is that the NAND-Type ternary content addressed memory stores M bits of each transfer rule as the first part, and The gate type (NOR-Type) ternary content address memory stores N bits of the same transfer rule as the second part, and then compares the M bits of the search data with the first part to output the first matching result, and After the first matching result is a match, the N bits of the search data are compared with the second part to output a second matching result, and when the first matching result is not matched, the comparison of the second part is disabled. The technical problem can be solved by the prior art, and the technical effect of improving the flexibility of the ternary content-addressed memory in the string length and reducing the power consumption is achieved.

While the present invention has been described above in the foregoing embodiments, it is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of patent protection shall be subject to the definition of the scope of the patent application attached to this specification.

110‧‧‧Search data register

120‧‧‧Pre-filter module

130‧‧‧Search Module

140‧‧‧ Pipeline temporary storage module

310‧‧‧XNOR logic gate unit

320‧‧‧Mask unit

410‧‧‧XOR logic gate unit

420‧‧‧Mask unit

610‧‧‧ Surge suppression circuit

710‧‧‧Matching line sense amplifier

810‧‧‧Displacement register

Step 210‧‧‧ temporarily stores a search data of binary, the search data is composed of L bits, wherein L is a positive integer

Step 220 ‧ ‧ provides at least one NAND-Type ternary content addressed memory storing a first portion of each transfer rule, the first portion being M bits, where M is a positive integer and M <L

Step 230‧ ‧ provides at least one NOR-Type ternary content addressing memory to store a second portion of each forwarding rule, the second portion being N bits, where N is a positive integer And N=LM

Step 240‧‧‧ align the M bits of the search data with the first portion to output a first matching result

Step 250‧‧‧ After the first matching result is a match, pre-charging is performed to reduce the energy delay, and the N bits of the search data are compared with the second part to output a second matching result. When the first matching result is a mismatch, turning on a potential transistor discharge to ground to disable the comparison between the N bits of the search data and the second portion

1 is a block diagram of a device for applying a ternary content addressed memory device to a software-defined network. 2 is a flow chart of a method for applying a ternary content addressed memory method of a software-defined network according to the present invention. FIG. 3 is a circuit diagram of the NAND-type ternary content addressed memory of the present invention. Figure 4 is a circuit diagram of the inverse OR gate type (NOR-Type) ternary content addressed memory of the present invention. Figure 5 is a circuit diagram of the pre-filter module of the present invention. Figure 6 is a circuit diagram of the pipeline temporary storage module of the present invention. Figure 7 is a circuit diagram of the search module of the present invention. Figure 8 is a circuit diagram showing the application of the present invention to different string lengths.

Claims (10)

A ternary content addressed memory device suitable for a software-defined network, the device comprising: a search data register for temporarily storing a binary search data, the search data consisting of L bits, wherein, L a pre-filter module, the pre-filter module is electrically connected to the search data register, and includes at least one NAND-type ternary content address memory to store each transfer rule. a first portion, the first portion is M bits, and the M bits of the search data are compared with the first portion to output a first matching result, where M is a positive integer and M < L; a search module, the search module is electrically connected to the search data register, and includes at least one NOR-Type ternary content address memory to store a second portion of each transfer rule. The second part is N bits, and after the first matching result is matched, the N bits of the search data are compared with the second part of the same forwarding rule to output a second matching result. Where N is a positive integer N=LM; and a pipeline temporary storage module electrically connected between the pre-filter module and the search module for pre-charging to reduce energy delay, and The search module is electrically connected. When the first matching result is a mismatch, the field effect transistor is electrically discharged to ground to disable the second search module. A ternary content addressed memory device for a software-defined network according to the first aspect of the patent application, wherein the NAND-type ternary content addressed memory is M bits, and the inverse Or NOR-Type ternary content-addressed memory is N bits, wherein each bit is electrically connected to a mask unit to set the corresponding bit to a random bit (Don't Care bit). According to the ternary content-addressed memory device applicable to the software-defined network according to Item 2 of the patent application scope, when the mask unit is set to logic 1, the corresponding alignment of the bit is disabled. A ternary content addressed memory device suitable for a software-defined network according to claim 1 of the scope of the patent application, wherein the search data may be 144-bit to 576-bit, and the NAND-Type ternary The content-addressed memory may be 9-bit to 36-bit, and the NOR-Type ternary content-addressed memory may be 135-bit to 540-bit. A ternary content addressed memory device for a software-defined network according to the first aspect of the patent application, wherein the pipeline temporary storage module includes a surge suppression circuit to prevent glitch. A ternary content addressed memory method suitable for a software-defined network, the steps comprising: temporarily storing a search data of a binary, the search data consisting of L bits, wherein L is a positive integer; providing at least one inverse A NAND-Type ternary content addressed memory stores a first portion of each forwarding rule, the first portion being M bits, where M is a positive integer and M < L; providing at least one inverse or gate type (NOR-Type) ternary content-addressed memory stores a second portion of each forwarding rule, the second portion being N bits, where N is a positive integer and N=LM; M of the search data Comparing the bit with the first portion to output a first matching result; and after the first matching result is a match, performing precharging to reduce the energy delay, and comparing the N bits of the search data with the second Partially aligning to output a second matching result, when the first matching result is a mismatch, turning on a potential transistor discharge to ground to disable the comparison of the N bits of the search data with the second portion . The ternary content addressed memory method applicable to a software-defined network according to claim 6 of the scope of the patent application, wherein the NAND-type ternary content addressed memory is M bits, and the inverse Or NOR-Type ternary content-addressed memory is N bits, wherein each bit is electrically connected to a mask unit to set the corresponding bit to a random bit (Don't Care bit). The ternary content addressed memory method applicable to a software-defined network according to item 7 of the patent application scope, wherein when the mask unit is set to logic 1, the corresponding alignment of the bits is disabled. The ternary content addressed memory method applicable to a software-defined network according to claim 6 of the scope of the patent application, wherein the search data may be 144-bit to 576-bit, and the NAND-Type ternary The content-addressed memory may be 9-bit to 36-bit, and the NOR-Type ternary content-addressed memory may be 135-bit to 540-bit. The ternary content addressed memory method applicable to a software-defined network according to claim 6 of the scope of the patent application, wherein the step of precharging to reduce the energy delay further comprises a surge suppression circuit to prevent glitch.