CN108055206B - Compact look-up table type hardware search engine and data conversion method thereof - Google Patents

Abstract

Compact table look-up type hardware search engine belongs to information technology field for reform transform traditional TCAM hardware search engine for circuit performance is higher, and the technical essential is: the decoder is used for decoding a search word and sending the search word into the CTL-TCAM array, the decoding is to convert the search word SL corresponding to data in a TCAM hardware search engine table into a search word LSL corresponding to data in the CTL-TCAM hardware search engine table, the CTL-TCAM array mainly comprises word circuits of a CTL-TCAM hardware search engine, each word circuit mainly comprises a plurality of NOR type CTL-TCAM hardware search engine units NORCTL-Tcell which are connected on a matched line ML in parallel or a plurality of NAND type CTL-TCAM hardware search engine units NANDCTL-Tcell which are connected in series, and the CTL-Tcell is connected with the decoder by a search data line and a global shielding line, and the effect is as follows: decoders are added so that the cell circuits with the added search lines can still fit the TCAM table data.

Description

Compact look-up table type hardware search engine and data conversion method thereof

Technical Field

The invention belongs to the technical field of information, and relates to a hardware search engine.

Background

TCAM (Ternary Content-Addressable Memory) is a high-speed hardware search engine, and is widely used in search-intensive operations, such as routers of backbone networks/edge networks in the Internet, to implement routing table lookup and packet forwarding.

BiCAM (binary CAM) can only store 1bit of data 0 or 1. And TCAM can store three values of 0,1, and X, where X is a wildcard and can represent either 0 or 1. According to the difference of the operation principle, TCAM match lines are mainly classified into NOR type and NAND type, as shown in fig. 1. The memory cell mainly comprises a memory cell, a match line ML, a search line SL and comparison tubes M1-M4, wherein the memory cell is a 6-tube SRAM cell, 2 read-write access tubes are omitted in figure 1, and the functional description of a cell circuit is shown in Table 1.

TABLE 1 TCAM cell coding

The NOR type TCAM word circuit is formed by connecting NOR type TCAM units together in parallel. The NAND type TCAM word circuit is formed by connecting NAND type TCAM units in series. See fig. 2. Wherein the NOR-type match line structure connects match lines ML of NOR-type TCAM cells in parallel, and the NAND-type match lines connect NAND-type TCAM cells in series. TCAM is composed of an array of word circuits, a decoder, and a priority encoder, see fig. 3. When the TCAM works, all word circuits are started simultaneously, which results in high power consumption of the TCAM, and a typical TCAM chip consumes about 25 watts. How to reduce power consumption without affecting search speed is a major research direction for scholars at home and abroad.

Mohan et al, 2007 proposed a NOR-type TCAM cell structure with Low parasitic capacitance (see [1] N. Mohan, et al, "Low-capacitance and charge-shared lines for Low-energy high-performance TCAMs," IEEE JSSC, vol.42, No.9, pp.2054-2060, Sept 2007 "), see FIG. 4. There is only one pipe M1 on the match line ML, while 2 pipes M1 and M2 are connected to ML of a conventional 16T NOR TCAM cell (see fig. 1 (a)). The parasitic capacitance is reduced, the power consumption is reduced, and the circuit speed can be accelerated.

The inventor continuously researches on the circuit to find that if a TCAM unit Tcell is combined every 2 bits to form a new circuit unit CTL-Tcell in an optimized mode, the parasitic capacitance of a matched line can be reduced by half, the probability of power consumption of a search line in a turning mode is reduced by half, and the search performance is greatly improved. The data stored in the CTL-Tcell unit needs to be processed from the TCAM.

Disclosure of Invention

In order to reduce the parasitic capacitance of a matched line, reduce the probability of power consumption of a search line in a turnover manner and improve the search performance, the invention provides the following scheme: a compact look-up type CTL-TCAM hardware search engine comprises a SL decoder and a CTL-TCAM array, the decoder is used to decode the search word and feed it into the CTL-TCAM array, the decoding is such that search word SL corresponding to data in the TCAM hardware search engine table is converted to search word LSL corresponding to CTL-TCAM hardware search engine table data, the CTL-TCAM array mainly comprises word circuits of a CTL-TCAM hardware search engine, each word circuit mainly comprises a plurality of NOR type CTL-TCAM hardware search engine units NOR CTL-Tcell which are connected on a matched line ML in parallel or a plurality of NAND type CTL-TCAM hardware search engine units NAND CTL-Tcell which are connected in series, the CTL-Tcell is connected with a decoder by a search data line and a global shielding line, and the CTL-TCAM array only comprises one global shielding line GLX.

The invention also relates to a data conversion method of the compact look-up table type CTL-TCAM hardware search engine, wherein the data stored in the CTL-TCAM hardware search engine is obtained by looking up the table of the data stored in the corresponding TCAM hardware search engine: grouping every two ternary bits in a TCAM hardware search engine word circuit, wherein each group is marked as T _ block, the group T _ block is mapped into a corresponding group CTL _ block in a CTL-TCAM hardware search engine, each group CTL _ block consists of four binary bits, and the conversion of each group T _ block into the corresponding group CTL _ block is realized by table lookup operation:

for each packet T _ block, the following operations are performed:

performing table lookup operation in the packet T _ block by 00, taking a hit result as a value of a first binary bit B-bit in the corresponding packet CTL _ block, and recording the value as B-bit [1], wherein the B-bit [1] is 1 when hit is performed, and otherwise, the B-bit [1] is 0;

performing table lookup operation on 01 in the packet T _ block, taking a hit result as the value of a second binary bit B-bit in the corresponding packet CTL _ block, and marking the value as B-bit [2], wherein the B-bit [2] is 1 when hit is performed, and otherwise, the B-bit [2] is 0;

performing table lookup operation in the packet T _ block by using 10, taking a hit result as a value of a third binary bit B-bit in the corresponding packet CTL _ block, and recording the value as B-bit [3], wherein the B-bit [3] is 1 when hit is performed, and otherwise, the B-bit [3] is 0;

and 11, performing table lookup operation in the packet T _ block, and taking a hit result as a value of a fourth binary bit B-bit in the corresponding packet CTL _ block, which is marked as B-bit [4], wherein the B-bit [4] is 1 when hit occurs, and otherwise, the B-bit [4] is 0.

The invention also relates to another data conversion method of the CTL-TCAM hardware search engine, wherein the data of the TCAM hardware search engine is obtained by mapping the data stored in the CTL-TCAM hardware search engine: grouping every four binary bits in a CTL-TCAM word circuit, wherein each group is marked as CTL _ block, the grouping CTL _ block is mapped into a corresponding group T _ block in TCAM, each group T _ block consists of two three-valued bits, and each group CTL _ block is converted into the corresponding group T _ block through table look-up operation:

the following is performed for each packet CTL _ block:

two data a and B are generated, a being the or of the first and second columns and B being the or of the third and fourth columns "

If { a, B } ═ 11; the value T-bit [1] ═ X in the first column of the TCAM table;

if { a, B } ═ 10; the value T-bit [1] of the first column of the TCAM table is 0;

if { a, B } ═ 01; the value T-bit [1] in the first column of the TCAM table is 1;

two data M and N are generated again, where M is an or of the first and third columns, and N is an or of the second and fourth columns.

If { M, N } ═ 11; the value T-bit [2] ═ X in the second column of the TCAM table;

if { M, N } ═ 10; the value T-bit [2] of the second column of the TCAM table is 0;

if { M, N } ═ 01; the value T-bit [2] in the second column of the TCAM table is 1.

Has the advantages that: the invention can reduce the stray capacitance of the matched line, reduce the probability of power consumption of the search line in turning and improve the search performance. The data stored in the CTL-Tcell unit needs to be looked up from the TCAM.

Drawings

FIG. 1 is a schematic diagram of a TCAM cell, wherein: (a) is NOR type TCAM unit, (b) is NAND type TCAM unit;

FIG. 2 is a schematic diagram of a TCAM word circuit configuration, in which: (a) a NOR type match line, (b) a NAND type match line;

FIG. 3 is a simple CAM block diagram;

FIG. 4 is a schematic diagram of a low parasitic capacitance TCAM structure;

FIG. 5 is an exemplary diagram of data interchange between a TCAM and a CTL-TCAM;

FIG. 6 is a block circuit diagram of a CTL-TCAM hardware search engine;

FIG. 7 is a schematic circuit diagram of the elements of a NOR type CTL-TCAM hardware search engine;

FIG. 8 is a schematic block circuit diagram of a NAND type CTL-TCAM hardware search engine;

FIG. 9 is a word circuit schematic of a NOR type CTL-TCAM hardware search engine;

FIG. 10 is a word circuit schematic of a NAND type CTL-TCAM hardware search engine;

FIG. 11 is a table partitioning diagram of a TCAM hardware search engine;

FIG. 12 is a table partitioning diagram of a CTL-TCAM hardware search engine;

FIG. 13 is a cell circuit diagram of a NOR type TL-TCAM hardware search engine;

FIG. 14 is a cell circuit diagram of a NAND type TL-TCAM hardware search engine.

Detailed Description

The present invention defines some of the terms used herein or Chinese translations: TCAM (Ternary Content-Addressable Memory) is a hardware search engine; CTL-TCAM is the improved compact look-up table type hardware search engine of the invention, and the embodiment also relates to a full-function TL-TCAM hardware search engine, for example, FIG. 13 shows a full-function NOR type TL-TCAM unit circuit and its connection relationship in the system, FIG. 14 shows a full-function NAND type TL-TCAM unit circuit and its connection relationship in the system, the two unit circuits described in FIGS. 9 and 10 of the invention are simplified circuits shown in FIGS. 13 and 14, compared with the full-function unit circuit, the simplified circuits are characterized in that the unit circuit of the invention only has NMOS tubes N1 and N2, no NMOS tubes N3 and N4, only has a global shielding line GLX, and no global shielding line GLX _ h, namely only has a global shielding line, based on which, the invention simplifies the full-function unit circuit, the unit circuit of the invention supports the global shielding (global shielding) of 1bit TCAM no longer, only every 2 bits of simultaneous overall shielding can be supported, but because the simplified circuit of the invention has fewer N3 and N4 tubes, and the global shielding line GLX _ h is also removed, the circuit is greatly simplified, and the performances such as area, power consumption and the like are greatly improved.

The following embodiments will be described with reference to the drawings, wherein the CTL-TCAM hardware search engine is involved in the invention.

In one embodiment, a CTL-TCAM hardware search engine includes a SL decoder for decoding a search word and feeding it into a CTL-TCAM array, the decoding being such that the search word SL corresponding to data in a TCAM hardware search engine table is converted to a search word LSL corresponding to data in the CTL-TCAM hardware search engine table, the CTL-TCAM array consisting essentially of word circuits of the CTL-TCAM hardware search engine, each word circuit consisting essentially of a plurality of CTL-TCAM hardware search engine units NOR CTL-Tcell of the NOR type connected in parallel on a matchline ML or a plurality of NAND-TCAM hardware search engine units NAND CTL-Tcell connected in series, the CTL-Tcell being connected to the decoder by a search data line and a global mask line.

In one scheme, data stored in a CTL-TCAM hardware search engine is obtained by looking up a data table stored in a corresponding TCAM hardware search engine, and data of the TCAM hardware search engine is obtained by means of data mapping stored in the CTL-TCAM hardware search engine; thus, the following scheme will specifically illustrate the data conversion manner of the CTL-TCAM hardware search engine of the present invention and the existing TCAM hardware search engine:

each bit in the TCAM hardware search engine table (set to T-bit) is ternary, and can be 0,1, X. In terms of circuit implementation, it is actually composed of 2-bit SRAM, i.e., T-bit (SRAM1, SRAM2), e.g., 0 ═ 0,1 ═ 1, (1,0), and X ═ 0, 0.

The CTL-TCAM hardware search engine divides the TCAM table equally, one packet (T _ block) per 2T-bit groups in each word circuit (one row is called a word circuit), see fig. 11, which needs to be described: here each bit T-bit is ternary.

FIG. 11 illustrates the manner in which a TCAM hardware search engine's tables are partitioned. Each 2T-bit bits in the word circuit constitutes a packet T _ block. T-bit is ternary, i.e. T-bit ═ SRAM1, SRAM 2.

Each T block is then transformed into a block CTL _ block of CTL-TCAM, see fig. 12. It should be noted that: here each bit B-bit is binary.

FIG. 12 shows the composition of a table for a CTL-TCAM hardware search engine. Each packet CTL _ block has a size of 1 row × 4 columns, where the B-bit is binary. The T _ block and CTL _ block storage capacities are therefore the same.

The main operation of the conversion is as follows:

for each packet T _ block, the following operations are performed:

performing table lookup operation on the packet T _ block by 00, taking a result of whether the packet T _ block is hit or not as a value of a first binary bit B-bit in the corresponding packet CTL _ block, and recording the value as B-bit [1], "hit" time when the packet T _ block is hit, and otherwise, when the packet T _ block is hit, the value of B-bit [1] ═ 0;

performing table lookup operation on 01 in the packet T _ block, taking a result of whether the packet T _ block is hit or not as the value of a second binary bit B-bit in the corresponding packet CTL _ block, and recording the value as B-bit [2], (B-bit [2] ═ 1 when the packet T _ block is hit), or else, setting B-bit [2] ═ 0;

performing table lookup operation in the packet T _ block by using 10, taking a result of whether the packet T _ block is hit or not as a value of a third binary bit B-bit in the corresponding packet CTL _ block, and recording the value as B-bit [3], "hit" time when the packet T _ block is hit, B-bit [3] ═ 1, otherwise, B-bit [3] ═ 0;

and performing table lookup operation on the packet T _ block by using 11, and taking a result of whether the packet T _ block is hit or not as a value of a fourth binary bit B-bit in the corresponding packet CTL _ block, wherein the value is marked as B-bit [4], "hit" is performed when the value of B-bit [4] ═ 1, and otherwise, the value of B-bit [4] ═ 0.

The TCAM to CTL-TCAM conversion pseudo-code is described as follows:

it should be noted that: since one bit of the TCAM is actually composed of 2-bit SRAM, the TCAM to CTL-TCAM conversion does not cause any additional bit increase, i.e., no additional increase in area.

Conversely, data in the tables of the CTL-TCAM hardware search engine may also be converted to data in the tables of the TCAM hardware search engine.

The main process of conversion is as follows:

the following is performed for each packet CTL _ block:

two data a and B are generated, a being the or of the first and second columns and B being the or of the third and fourth columns "

If { a, B } ═ 11; the value T-bit [1] ═ X in the first column of the TCAM table;

if { a, B } ═ 10; the value T-bit [1] of the first column of the TCAM table is 0;

if { a, B } ═ 01; the value T-bit [1] in the first column of the TCAM table is 1;

two data M and N are generated again, where M is an or of the first and third columns, and N is an or of the second and fourth columns.

If { M, N } ═ 11; the value T-bit [2] ═ X in the second column of the TCAM table;

if { M, N } ═ 10; the value T-bit [2] of the second column of the TCAM table is 0;

if { M, N } ═ 01; the value T-bit [2] in the second column of the TCAM table is 1.

The conversion pseudo code for the data conversion in the CTL-TCAM to TCAM table is described as follows:

FIG. 5 shows an example of data conversion between different hardware search engines.

In one embodiment, the circuitry of the CTL-TCAM hardware search engine is shown in FIG. 6, because the CTL-TCAM hardware search engine is converted from a TCAM hardware search engine, and thus the search word SL fed into the CTL-TCAM array (CTL-TCAM array) needs to be decoded. For a TCAM hardware search engine packet T _ block, the search line SL is decoded every 2 bits.

The CTL-TCAM array mainly comprises word circuits of a CTL-TCAM hardware search engine, each word circuit mainly comprises a plurality of NOR type CTL-TCAM hardware search engine units NOR CTL-Tcell which are connected on a matched line ML in parallel or a plurality of NAND type CTL-TCAM hardware search engine units NAND CTL-Tcell which are connected in series, and the CTL-Tcell is connected with a decoder by a search data line and a global shielding line.

The conventional TCAM units, whose incoming search lines support the global masking function, can each be globally masked. In this embodiment, however, the search line only supports a simultaneous global masking function at the packet (CTL _ block) level, i.e., a corresponding T _ block, with both T-bits either simultaneously globally masked or without global masking. . The functional pseudo-code for an SL decoder (SL decoder) is described as follows:

the function for the decoder is described as follows:

(1) when SL [2n:2n +1] is two global Xs, the search data lines LSL _00, LSL _01, LSL _10, LSL _11 are all 0, the global shield line GLX is 1;

(2) when SL [2n:2n +1] has no global X:

the global shielding line GLX is 0; when SL [2n:2n +1] ═ 00, search data line LSL _00 = 1; when SL [2n:2n +1] ═ 01, search data line LSL _01 ═ 1; when SL [2n:2n +1] ═ 10, search data line LSL _10 ═ 1; when SL [2n:2n +1] is equal to 11, the search data line LSL _11 is equal to 1.

For a cell circuit of a CTL-TCAM array (CTL-TCAM array), NOR type and NAND type can be classified according to the configuration.

The NOR CTL-Tcell comprises inverters T1-T8, NMOS tubes M1-M4, NMOS tubes N1-N2, search data lines LSL _00, LSL _01, LSL _10, LSL _11, a global shielding line GLX, a local matching line LML and a global matching line ML; the input end of the inverter T1 is connected with the output end of the inverter T2 to be used as a data storage end M [1] of the B-bit [1], the output end of the inverter T1 is connected with the input end of the inverter T2 to be used as a data storage end M [1] #oflogic 'NOT' of the B-bit [1], and the end M # is the logic 'NOT' of the end M; the source of MOS tube M1 is connected with M [1] # end, the grid of MOS tube M1 is connected with search data line LSL _00, the drain of MOS tube M1 is connected with local match line LML; the input end of inverter T3 is connected with the output end of inverter T4 as the data storage end M2 of B-bit 2, the output end of inverter T3 is connected with the input end of inverter T4 as the data storage end M2 # of the logical negation of B-bit 2, the end M2 # is the logical negation of the end M2, the drain of MOS tube M2 is connected with the end M2 #, the grid of MOS tube M2 is connected with the search data line LSL _01, the source of MOS tube M2 is connected with local matchline LML and with the drain of MOS tube M1; the input end of inverter T5 is connected with the output end of inverter T6 as the data storage end M [3] of B-bit [3], the output end of inverter T5 is connected with the input end of inverter T6 as the data storage end M [3] #oflogic 'NOT' of B-bit [3], M [3] # is the logic 'NOT' of M [3], the source of MOS tube M3 is connected with the end M [3] # and the grid of MOS tube M3 is connected with the search data line LSL _10, the drain of MOS tube M3 is connected with the local match line LML; the input end of inverter T7 is connected with the output end of inverter T8 as the data storage end M [4] of B-bit [4], the output end of inverter T7 is connected with the input end of inverter T8 as the data storage end M [4] #oflogic "NOT" of B-bit [4], M [4] # is the logic "NOT" of M [4], the drain of MOS tube M4 is connected with the end M [4] #, the grid of MOS tube M4 is connected with the search data line LSL _11, the source of MOS tube M4 is connected with local matchline LML and is connected with the drain of MOS tube M3; the grid electrode of the MOS tube N1 is connected with a global shielding line GLX, the source electrode of the MOS tube N1 is grounded, and the drain electrode of the MOS tube N1 is connected with a matching line LML; the grid electrode of the MOS tube N2 is connected to a local match line LML, and the source electrode of the MOS tube N2 is grounded; the drain of the MOS transistor N2 is connected to the global match line ML.

The working principle of the NOR type unit circuit is as follows:

A. SL [2n:2n +1] without global X

When the global shielding line GLX is equal to 0, the NMOS transistor N1 is turned off;

according to the SL decoder, only one of the search data lines LSL _00, LSL _01, LSL _10 and LSL _11 is 1, and the corresponding M # is sent out (namely the 'negation' of the B-bit); for example, SL [2n:2n +1] ═ {0,0}, LSL _00 ═ 1, M1 is turned on, and the "not" value of B-bit [1] is sent to LML.

If the sent M # -0 (M-1 indicates a match), the local match line LML is 0, the NMOS transistor N2 is turned off, the search result of CTL-Tcell is a match, and if the results of all CTL-Tcell in the word circuit are a match, the whole word circuit gives a matched search result; since all NMOS transistors N2 of CTL-Tcell are closed, all discharge channels of ML are closed at the moment;

if the sent M # -1 and the local match line LML is 1, the NMOS tube N2 is opened, the search result of the CTL-Tcell is mismatch, if at least one of the CTL-Tcell in the word circuit has mismatch, the whole word circuit gives the mismatched search result, and at least one discharge channel of the global match line ML is opened because at least one NMOS tube N2 of the CTL-Tcell is opened;

B. SL [2n:2n +1] with two global Xs

The search data lines LSL _00, LSL _01, LSL _10, LSL _11 are all 0, and the NMOS transistors M1, M2, M3, M4 are all off;

the global shielding line GLX is 1, the NMOS transistor N1 is turned on, and the local match line LML is 0;

at this time, the NMOS transistor N2 is turned off, the global match line ML pull-down path is turned off, and the cell comparison result is a match.

The NAND-type CTL-TCAM array is mainly composed of NAND-type CTL-TCAM hardware search engine word circuits (CTL-TCAM word) as shown in fig. 10, and for the NAND-type cell circuits, each word circuit is composed of many CTL-TCAM hardware search engine cells (CTL-Tcell) connected in series. M is the memory cell B-bit of CTL-TCAM, and M # represents the logical negation of M. M ═ 1 indicates a match, and M ═ 0 indicates a mismatch. As shown in fig. 8, the NAND CTL-Tcell includes inverters T1 to T8, NMOS transistors M1 to M4, NMOS transistors N1 to N2, search data lines LSL _00, LSL _01, LSL _10, LSL _11, global mask line GLX, local match line LML, and global match line ML _ L, ML _ R; the input end of the inverter T1 is connected with the output end of the inverter T2 to be used as a data storage end M [1] of the B-bit [1], the output end of the inverter T1 is connected with the input end of the inverter T2 to be used as a data storage end M [1] #oflogic 'NOT' of the B-bit [1], and the end M # is the logic 'NOT' of the end M; the source of MOS transistor M1 is connected to M1 end, the grid of MOS transistor M1 is connected to search data line LSL _00, the drain of MOS transistor M1 is connected to local match line LML; the input end of inverter T3 is connected with the output end of inverter T4 as the data storage end M2 of B-bit 2, the output end of inverter T3 is connected with the input end of inverter T4 as the data storage end M2 # of the logical negation of B-bit 2, the end M2 # is the logical negation of M2, the drain of MOS tube M2 is connected with the end M2, the grid of MOS tube M2 is connected with search data line LSL-01, the source of MOS tube M2 is connected with local match line LML and connected with the drain of MOS tube M1; the input end of inverter T5 is connected with the output end of inverter T6 as the data storage end M [3] of B-bit [3], the output end of inverter T5 is connected with the input end of inverter T6 as the data storage end M [3] #oflogic 'NOT' of B-bit [3], M [3] # is the logic 'NOT' of M [3], the source of MOS tube M3 is connected with the end M [3], the grid of MOS tube M3 is connected with the search data line LSL _10, the drain of MOS tube M3 is connected with the local match line LML; the input end of inverter T7 is connected with the output end of inverter T8 as the data storage end M4 of B-bit 4, the output end of inverter T7 is connected with the input end of inverter T8 as the data storage end M4 # of logic 'NOT' of B-bit 4, M4 # is the logic 'NOT' of M4, the drain of MOS tube M4 is connected with M4, the grid of MOS tube M4 is connected with search data line LSL _11, the source of MOS tube M4 is connected with local match line LML and with the drain of MOS tube M3; the grid electrode of the MOS tube N1 is connected with a global shielding line GLX, the source electrode of the MOS tube N1 is connected with a power supply, and the drain electrode of the MOS tube N1 is connected with a local matching line LML; the gate of the MOS transistor N2 is connected to a match line LML, the global match line ML _ L is connected to the drain of the MOS transistor N2, and the global match line ML _ R is connected to the source of the MOS transistor N2.

The working principle of the NAND type unit circuit is as follows:

A. SL [2n:2n +1] without global X

GLX is 0 and NMOS transistor N1 is off.

According to SL decoder, only one of the search data lines LSL _00, LSL _01, LSL _10 and LSL _11 is 1, and the corresponding M is sent out;

if the sent M is 1, the LML is 1, the NMOS transistor N2 is turned on, the search result of the CTL-Tcell is a match, and if the results of all CTL-Tcell in the word circuit are a match, the whole word circuit gives a matched search result;

if the sent M is 0, LML is 0, the NMOS transistor N2 is turned off, the search result of the CTL-Tcell is a mismatch, and if the result of at least one of all the CTL-Tcell in the word circuit is a mismatch, the entire word circuit gives the search result of the mismatch.

B. SL [2n:2n +1] with two global Xs

The search data lines LSL _00, LSL _01, LSL _10, LSL _11 are all 0, and the NMOS transistors M1, M2, M3, M4 are all off;

the global shielding line GLX is 1, the NMOS transistor N1 is turned on, and LMLs are both 1;

at this time, the NMOS transistor N2 is turned on, and the cell comparison result is a match.

In the above embodiments, the cell circuit Tcell of the existing TCAM hardware search engine of fig. 4 and the cell circuit CTL-Tcell of the CTL-TCAM hardware search engine proposed by the present invention are compared in circuit structure. First, the search line power consumption is reduced. Tcell is a 1-bit TCAM unit, while a CTL-Tcell is equivalent to a 2-bit Tcell. Since the probability of occurrence of global X is low, we only consider power consumption without global X here. Since SL ═ SL, SL # }, SL # is a strict logical "not" of SL, such as SL ═ 0,1, SL ═ 1, 0. The probabilities of 0 and 1 being equal for each clock cycle SL, i.e., there is a flip of either 0,1 to 1,0 or 1,0 to 0,1 for each cycle, as calculated by the average probability. Current is drawn from the power supply at 0 to 1, which corresponds to one SL line per 1 Tcell per cycle. In the CTL-TCAM hardware search engine provided by the invention, only one line LSL is selected in each CTL-Tcell in each period. Because one CTL-Tcell is equivalent to 2 Tcells, the equivalent thinking is that every 2 Tcells of the original hardware search engine have one line to turn over and consume power. Therefore, ideally, the power consumption of the search line SL is reduced by half. Second, match line parasitic capacitance is reduced. As can be seen from the data conversion part of the CTL-TCAM hardware search engine and the traditional TCAM hardware search engine, the storage bit of the CTL-TCAM hardware search engine is not increased and is consistent with the original TCAM hardware search engine. For the present invention, in an ideal case, the ML parasitic capacitance is halved, the power consumption is halved, and the speed is doubled, for the following reasons: A. NOR type architecture. Since CTL-Tcell is equivalent to a 2bit Tcell, the Tcell of FIG. 1(a), has a pipe (M1) directly connected to the ML for each Tcell. Whereas the CTL-Tcell of fig. 7, corresponds to a pipe (N2) directly connected to the ML for every two tcells. Therefore, the parasitic capacitance is halved, the power consumption is halved, and the speed is doubled. B. Compared with the structure shown in the figure 1 (b), the NAND type CTL-Tcell is equivalent to that one transmission tube N2 is arranged for every 2 Tcells, so that the parasitic capacitance is reduced, the power consumption is reduced, the speed is improved, and the actual speed can be even doubled due to the fact that the speed is improved in a serial connection mode in a nonlinear mode.

Claims (10)

1. A compact look-up table type CTL-TCAM hardware search engine, comprising an SL decoder for decoding a search word and sending it to a CTL-TCAM array, the decoding being such that the search word SL corresponding to data in a TCAM hardware search engine table is converted to a search word LSL corresponding to data in the CTL-TCAM hardware search engine table, the CTL-TCAM array consisting essentially of word circuits for the CTL-TCAM hardware search engine, each word circuit consisting essentially of a plurality of NOR CTL-TCAM hardware search engine cells NOR CTL-Tcell connected in parallel on a matchline ML, the CTL-Tcell being connected to the decoder by search data lines and global mask lines and having only one global mask line GLX; the NORCTL-Tcell comprises inverters T1-T8, NMOS tubes M1-M4, NMOS tubes N1-N2, search data lines LSL _00, LSL _01, LSL _10, LSL _11, a global shielding line GLX, a local matching line LML and a global matching line ML; the input end of the inverter T1 is connected with the output end of the inverter T2 to be used as a data storage end M [1] of the B-bit [1], the output end of the inverter T1 is connected with the input end of the inverter T2 to be used as a data storage end M [1] #oflogic 'NOT' of the B-bit [1], and the end M # is the logic 'NOT' of the end M; the source of MOS tube M1 is connected with M [1] # end, the grid of MOS tube M1 is connected with search data line LSL _00, the drain of MOS tube M1 is connected with local match line LML; the input end of inverter T3 is connected with the output end of inverter T4 as the data storage end M2 of B-bit 2, the output end of inverter T3 is connected with the input end of inverter T4 as the data storage end M2 # of the logical negation of B-bit 2, the end M2 # is the logical negation of the end M2, the drain of MOS tube M2 is connected with the end M2 #, the grid of MOS tube M2 is connected with the search data line LSL _01, the source of MOS tube M2 is connected with local matchline LML and with the drain of MOS tube M1; the input end of inverter T5 is connected with the output end of inverter T6 as the data storage end M [3] of B-bit [3], the output end of inverter T5 is connected with the input end of inverter T6 as the data storage end M [3] #oflogic 'NOT' of B-bit [3], M [3] # is the logic 'NOT' of M [3], the source of MOS tube M3 is connected with the end M [3] # and the grid of MOS tube M3 is connected with the search data line LSL _10, the drain of MOS tube M3 is connected with the local match line LML; the input end of inverter T7 is connected with the output end of inverter T8 as the data storage end M [4] of B-bit [4], the output end of inverter T7 is connected with the input end of inverter T8 as the data storage end M [4] #oflogic "NOT" of B-bit [4], M [4] # is the logic "NOT" of M [4], the drain of MOS tube M4 is connected with the end M [4] #, the grid of MOS tube M4 is connected with the search data line LSL _11, the source of MOS tube M4 is connected with local matchline LML and is connected with the drain of MOS tube M3; the grid electrode of the MOS tube N1 is connected with a global shielding line GLX, the source electrode of the MOS tube N1 is grounded, and the drain electrode of the MOS tube N1 is connected with a matching line LML; the grid electrode of the MOS tube N2 is connected to a local match line LML, and the source electrode of the MOS tube N2 is grounded; the drain of the MOS transistor N2 is connected to the global match line ML.

2. The compact lookup type CTL-TCAM hardware search engine as claimed in claim 1, wherein said SL decoder performs decoding based on:

(1) when SL [2n:2n +1] is two global Xs, the search data lines LSL _00, LSL _01, LSL _10, LSL _11 are all 0, the global shield line GLX is 1;

(2) when SL [2n:2n +1] has no global X:

the global shielding line GLX is 0; when SL [2n:2n +1] ═ 00, search data line LSL _00 = 1; when SL [2n:2n +1] ═ 01, search data line LSL _01 ═ 1; when SL [2n:2n +1] ═ 10, search data line LSL _10 ═ 1; when SL [2n:2n +1] is equal to 11, the search data line LSL _11 is equal to 1.

3. The compact lookup type CTL-TCAM hardware search engine of claim 2, wherein the NOR CTL-Tcell unit operates based on:

A. SL [2n:2n +1] without global X

When the global shielding line GLX is equal to 0, the NMOS transistor N1 is turned off;

according to SL decoder, only one of search data lines LSL _00, LSL _01, LSL _10 and LSL _11 is 1, and corresponding M # is sent out;

if the sent M # -0, the local match line LML-0, the NMOS transistor N2 is closed, the search result of CTL-Tcell is match, if all the CTL-Tcell results in the word circuit are match, the whole word circuit gives a matched search result; since all NMOS transistors N2 of CTL-Tcell are closed, all discharge channels of ML are closed at the moment;

if the sent M # -1 and the local match line LML is 1, the NMOS tube N2 is opened, the search result of the CTL-Tcell is mismatch, if at least one of the CTL-Tcell in the word circuit has mismatch, the whole word circuit gives the mismatched search result, and at least one discharge channel of the global match line ML is opened because at least one NMOS tube N2 of the CTL-Tcell is opened;

B. SL [2n:2n +1] with two global Xs

The search data lines LSL _00, LSL _01, LSL _10, LSL _11 are all 0, and the NMOS transistors M1, M2, M3, M4 are all off;

the global shielding line GLX is 1, the NMOS transistor N1 is turned on, and the local match line LML is 0;

at this time, the NMOS transistor N2 is turned off, the global match line ML pull-down path is turned off, and the cell comparison result is a match.

4. A method for converting data of a compact look-up type CTL-TCAM hardware search engine according to any one of claims 1 to 3, wherein the data stored in the CTL-TCAM hardware search engine is obtained from a corresponding look-up table of data stored in the TCAM hardware search engine: grouping every two ternary bits in a TCAM hardware search engine word circuit, wherein each group is marked as T _ block, the group T _ block is mapped into a corresponding group CTL _ block in a CTL-TCAM hardware search engine, each group CTL _ block consists of four binary bits, and the conversion of each group T _ block into the corresponding group CTL _ block is realized by table lookup operation:

for each packet T _ block, the following operations are performed:

performing table lookup operation in the packet T _ block by 00, taking a hit result as a value of a first binary bit B-bit in the corresponding packet CTL _ block, and recording the value as B-bit [1], wherein the B-bit [1] is 1 when hit is performed, and otherwise, the B-bit [1] is 0;

performing table lookup operation on 01 in the packet T _ block, taking a hit result as the value of a second binary bit B-bit in the corresponding packet CTL _ block, and marking the value as B-bit [2], wherein the B-bit [2] is 1 when hit is performed, and otherwise, the B-bit [2] is 0;

performing table lookup operation in the packet T _ block by using 10, taking a hit result as a value of a third binary bit B-bit in the corresponding packet CTL _ block, and recording the value as B-bit [3], wherein the B-bit [3] is 1 when hit is performed, and otherwise, the B-bit [3] is 0;

and 11, performing table lookup operation in the packet T _ block, and taking a hit result as a value of a fourth binary bit B-bit in the corresponding packet CTL _ block, which is marked as B-bit [4], wherein the B-bit [4] is 1 when hit occurs, and otherwise, the B-bit [4] is 0.

5. A method for converting data of a CTL-TCAM hardware search engine according to any one of claims 1 to 3, wherein the data of the TCAM hardware search engine is mapped by the data stored in the CTL-TCAM hardware search engine: grouping every four binary bits in a CTL-TCAM word circuit, wherein each group is marked as CTL _ block, the grouping CTL _ block is mapped into a corresponding group T _ block in TCAM, each group T _ block consists of two three-valued bits, and each group CTL _ block is converted into the corresponding group T _ block through table look-up operation:

the following is performed for each packet CTL _ block:

two data a and B are generated, a ═ or of the first column and the second column, and B ═ or of the third column and the fourth column;

if { a, B } ═ 11; the value T-bit [1] ═ X in the first column of the TCAM table;

if { a, B } ═ 10; the value T-bit [1] of the first column of the TCAM table is 0;

if { a, B } ═ 01; the value T-bit [1] in the first column of the TCAM table is 1;

two data M and N are generated, where M is an or of the first and third columns, and N is an or of the second and fourth columns;

if { M, N } ═ 11; the value T-bit [2] ═ X in the second column of the TCAM table;

if { M, N } ═ 10; the value T-bit [2] of the second column of the TCAM table is 0;

if { M, N } ═ 01; the value T-bit [2] in the second column of the TCAM table is 1.

6. A compact look-up table type CTL-TCAM hardware search engine, comprising an SL decoder, a CTL-TCAM array, said decoder for decoding and sending search words into the CTL-TCAM array, said decoding being such that search words SL corresponding to data in a TCAM hardware search engine table are converted into search words LSL corresponding to data in the CTL-TCAM hardware search engine table, said CTL-TCAM array being formed by a plurality of NAND CTL-TCAM hardware search engine units NAND CTL-Tcell connected in series, CTL-Tcell being connected to the decoder by a search data line and a global mask line and having only one global mask line GLX; the NAND CTL-Tcell comprises inverters T1-T8, NMOS tubes M1-M4, NMOS tubes N1-N2, search data lines LSL _00, LSL _01, LSL _10, LSL _11, a global shielding line GLX, a local match line LML and a global match line ML _ L, ML _ R; the input end of the inverter T1 is connected with the output end of the inverter T2 to be used as a data storage end M [1] of the B-bit [1], the output end of the inverter T1 is connected with the input end of the inverter T2 to be used as a data storage end M [1] #oflogic 'NOT' of the B-bit [1], and the end M # is the logic 'NOT' of the end M; the source of MOS transistor M1 is connected to M1 end, the grid of MOS transistor M1 is connected to search data line LSL _00, the drain of MOS transistor M1 is connected to local match line LML; the input end of inverter T3 is connected with the output end of inverter T4 as the data storage end M2 of B-bit 2, the output end of inverter T3 is connected with the input end of inverter T4 as the data storage end M2 # of the logical negation of B-bit 2, the end M2 # is the logical negation of M2, the drain of MOS tube M2 is connected with the end M2, the grid of MOS tube M2 is connected with search data line LSL-01, the source of MOS tube M2 is connected with local match line LML and connected with the drain of MOS tube M1; the input end of inverter T5 is connected with the output end of inverter T6 as the data storage end M [3] of B-bit [3], the output end of inverter T5 is connected with the input end of inverter T6 as the data storage end M [3] #oflogic 'NOT' of B-bit [3], M [3] # is the logic 'NOT' of M [3], the source of MOS tube M3 is connected with the end M [3], the grid of MOS tube M3 is connected with the search data line LSL _10, the drain of MOS tube M3 is connected with the local match line LML; the input end of inverter T7 is connected with the output end of inverter T8 as the data storage end M4 of B-bit 4, the output end of inverter T7 is connected with the input end of inverter T8 as the data storage end M4 # of logic 'NOT' of B-bit 4, M4 # is the logic 'NOT' of M4, the drain of MOS tube M4 is connected with M4, the grid of MOS tube M4 is connected with search data line LSL _11, the source of MOS tube M4 is connected with local match line LML and with the drain of MOS tube M3; the grid electrode of the MOS tube N1 is connected with a global shielding line GLX, the source electrode of the MOS tube N1 is connected with a power supply, and the drain electrode of the MOS tube N1 is connected with a local matching line LML; the gate of the MOS transistor N2 is connected to a match line LML, the global match line ML _ L is connected to the drain of the MOS transistor N2, and the global match line ML _ R is connected to the source of the MOS transistor N2.

7. The compact lookup type CTL-TCAM hardware search engine as claimed in claim 6, wherein said SL decoder performs decoding based on:

(1) when SL [2n:2n +1] is two global Xs, the search data lines LSL _00, LSL _01, LSL _10, LSL _11 are all 0, the global shield line GLX is 1;

(2) when SL [2n:2n +1] has no global X:

the global shielding line GLX is 0; when SL [2n:2n +1] ═ 00, search data line LSL _00 = 1; when SL [2n:2n +1] ═ 01, search data line LSL _01 ═ 1; when SL [2n:2n +1] ═ 10, search data line LSL _10 ═ 1; when SL [2n:2n +1] is equal to 11, the search data line LSL _11 is equal to 1.

8. The compact lookup type CTL-TCAM hardware search engine of claim 7 wherein the NAND CTL-Tcell unit operates based on:

A. SL [2n:2n +1] without global X

GLX is 0 and NMOS transistor N1 is off;

according to SL decoder, only one of the search data lines LSL _00, LSL _01, LSL _10 and LSL _11 is 1, and the corresponding M is sent out;

if the sent M is 1, the LML is 1, the NMOS transistor N2 is turned on, the search result of the CTL-Tcell is a match, and if the results of all CTL-Tcell in the word circuit are a match, the whole word circuit gives a matched search result;

if the sent M is 0, LML is 0, the NMOS pipe N2 is closed, the search result of the CTL-Tcell is mismatch, and if the result of at least one of all CTL-Tcell in the word circuit is mismatch, the whole word circuit gives the search result of mismatch;

B. SL [2n:2n +1] with two global Xs

The search data lines LSL _00, LSL _01, LSL _10, LSL _11 are all 0, and the NMOS transistors M1, M2, M3, M4 are all off;

the global shielding line GLX is 1, the NMOS transistor N1 is turned on, and LMLs are both 1;

at this time, the NMOS transistor N2 is turned on, and the cell comparison result is a match.

9. A data conversion method of a compact look-up type CTL-TCAM hardware search engine as claimed in any one of claims 6 to 8, wherein the data stored in the CTL-TCAM hardware search engine is obtained from a corresponding look-up table of data stored in the TCAM hardware search engine: grouping every two ternary bits in a TCAM hardware search engine word circuit, wherein each group is marked as T _ block, the group T _ block is mapped into a corresponding group CTL _ block in a CTL-TCAM hardware search engine, each group CTL _ block consists of four binary bits, and the conversion of each group T _ block into the corresponding group CTL _ block is realized by table lookup operation:

for each packet T _ block, the following operations are performed:

performing table lookup operation in the packet T _ block by 00, taking a hit result as a value of a first binary bit B-bit in the corresponding packet CTL _ block, and recording the value as B-bit [1], wherein the B-bit [1] is 1 when hit is performed, and otherwise, the B-bit [1] is 0;

performing table lookup operation on 01 in the packet T _ block, taking a hit result as the value of a second binary bit B-bit in the corresponding packet CTL _ block, and marking the value as B-bit [2], wherein the B-bit [2] is 1 when hit is performed, and otherwise, the B-bit [2] is 0;

performing table lookup operation in the packet T _ block by using 10, taking a hit result as a value of a third binary bit B-bit in the corresponding packet CTL _ block, and recording the value as B-bit [3], wherein the B-bit [3] is 1 when hit is performed, and otherwise, the B-bit [3] is 0;

and 11, performing table lookup operation in the packet T _ block, and taking a hit result as a value of a fourth binary bit B-bit in the corresponding packet CTL _ block, which is marked as B-bit [4], wherein the B-bit [4] is 1 when hit occurs, and otherwise, the B-bit [4] is 0.

10. A method for converting data of a CTL-TCAM hardware search engine according to any one of claims 6 to 8, wherein the data of the TCAM hardware search engine is mapped by the data stored in the CTL-TCAM hardware search engine: grouping every four binary bits in a CTL-TCAM word circuit, wherein each group is marked as CTL _ block, the grouping CTL _ block is mapped into a corresponding group T _ block in TCAM, each group T _ block consists of two three-valued bits, and each group CTL _ block is converted into the corresponding group T _ block through table look-up operation:

the following is performed for each packet CTL _ block:

two data a and B are generated, a ═ or of the first column and the second column, and B ═ or of the third column and the fourth column;

if { a, B } ═ 11; the value T-bit [1] ═ X in the first column of the TCAM table;

if { a, B } ═ 10; the value T-bit [1] of the first column of the TCAM table is 0;

if { a, B } ═ 01; the value T-bit [1] in the first column of the TCAM table is 1;

two data M and N are generated, where M is an or of the first and third columns, and N is an or of the second and fourth columns;

if { M, N } ═ 11; the value T-bit [2] ═ X in the second column of the TCAM table;

if { M, N } ═ 10; the value T-bit [2] of the second column of the TCAM table is 0;

if { M, N } ═ 01; the value T-bit [2] in the second column of the TCAM table is 1.

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