CN108199969B - Look-up type hardware search engine - Google Patents

Abstract

A table look-up type hardware search engine belongs to the technical field of information and is used for improving a traditional TCAM hardware search engine to enable the circuit performance to be higher. The technical points are as follows: the TL-TCAM hardware search engine comprises an SL decoder and a TL-TCAM array, wherein data stored in the TL-TCAM hardware search engine is obtained by looking up a data table stored in the corresponding TCAM hardware search engine, the decoder is used for decoding search words and sending the search words into the TL-TCAM hardware search engine array, the decoding is to convert the search words SL corresponding to the data in the TCAM hardware search engine table into the search words LSL corresponding to the data in the TL-TCAM hardware search engine table, and the effect is as follows: and a TCAM adding decoder which is matched with the decoder and converts TCAM table data into new circuit units which can adapt to the addition of the search lines in a table look-up mode.

Description

Look-up type hardware search engine

Technical Field

The invention belongs to the technical field of information, and relates to a hardware search engine.

Background

TCAM (Ternary Content-Addressable Memory) is a high-speed hardware search engine, and is widely used in search-intensive operations, such as routers of backbone networks/edge networks in the Internet, to implement routing table lookup and packet forwarding.

BiCAM (binary CAM) can only store 1bit of data 0 or 1. And TCAM can store three values of 0,1, and X, where X is a wildcard and can represent either 0 or 1. According to the difference of the operation principle, TCAM match lines are mainly classified into NOR type and NAND type, as shown in fig. 1. The memory cell mainly comprises a memory cell, a match line ML, a search line SL and comparison tubes M1-M4, wherein the memory cell is a 6-tube SRAM cell, 2 read-write access tubes are omitted in figure 1, and the functional description of a cell circuit is shown in Table 1.

TABLE 1 TCAM cell coding

The NOR type TCAM word circuit is formed by connecting NOR type TCAM units together in parallel. The NAND type TCAM word circuit is formed by connecting NAND type TCAM units in series. See fig. 2. Wherein the NOR-type match line structure connects match lines ML of NOR-type TCAM cells in parallel, and the NAND-type match lines connect NAND-type TCAM cells in series. TCAM is composed of an array of word circuits, a decoder, and a priority encoder, see fig. 3. When the TCAM works, all word circuits are started simultaneously, which results in high power consumption of the TCAM, and a typical TCAM chip consumes about 25 watts. How to reduce power consumption without affecting search speed is a major research direction for scholars at home and abroad.

Mohan et al, 2007 proposed a NOR-type TCAM cell structure with Low parasitic capacitance (see [1] N. Mohan, et al, "Low-capacitance and charge-shared lines for Low-energy high-performance TCAMs," IEEE JSSC, vol.42, No.9, pp.2054-2060, Sept 2007 "), see FIG. 4. There is only one pipe M1 on the match line ML, while 2 pipes M1 and M2 are connected to ML of a conventional 16T NOR TCAM cell (see fig. 1 (a)). The parasitic capacitance is reduced, the power consumption is reduced, and the circuit speed can be accelerated.

The inventor continuously researches on the circuit to find that if a TCAM unit Tcell is combined every 2 bits to form a new circuit unit TL-Tcell in an optimized mode, the parasitic capacitance of a matched line can be reduced by half, the probability of power consumption of a search line in a turning mode is reduced by half, and the search performance is greatly improved. The data stored in the TL-Tcell cell needs to be processed from the TCAM.

Disclosure of Invention

In order to reduce the parasitic capacitance of a matched line, reduce the probability of power consumption of a search line in a turnover manner and improve the search performance, the invention provides the following scheme: a table look-up TL-TCAM hardware search engine comprises an SL decoder and a TL-TCAM array, wherein data stored in the TL-TCAM hardware search engine is obtained by looking up a table of data stored in the corresponding TCAM hardware search engine, the decoder is used for decoding search words and sending the search words into the TL-TCAM hardware search engine array, and the decoding is to convert the search words SL corresponding to the data in a TCAM hardware search engine table into the search words LSL corresponding to the TL-TCAM hardware search engine table data.

Has the advantages that: the invention can reduce the stray capacitance of the matched line, reduce the probability of power consumption of the search line in turning and improve the search performance. The data stored in the TL-Tcell unit needs to be looked up from the TCAM.

Drawings

FIG. 1 is a schematic diagram of a TCAM cell, wherein: (a) is NOR type TCAM unit, (b) is NAND type TCAM unit;

FIG. 2 is a schematic diagram of a TCAM word circuit configuration, in which: (a) a NOR type match line, (b) a NAND type match line;

FIG. 3 is a simple CAM block diagram;

FIG. 4 is a schematic diagram of a low parasitic capacitance TCAM structure;

FIG. 5 is an exemplary diagram of data interchange between a TCAM and a TL-TCAM;

FIG. 6 is a block circuit diagram of a TL-TCAM hardware search engine;

FIG. 7 is a schematic circuit diagram of a cell of a NOR type TL-TCAM hardware search engine;

FIG. 8 is a schematic circuit diagram of a unit of a NAND type TL-TCAM hardware search engine;

FIG. 9 is a word circuit schematic of a NOR type TL-TCAM hardware search engine;

FIG. 10 is a word circuit schematic of a NAND type TL-TCAM hardware search engine;

FIG. 11 is a table partitioning diagram of a TCAM hardware search engine;

FIG. 12 is a table partitioning diagram of a TL-TCAM hardware search engine.

Detailed Description

The present invention defines some of the terms used herein or Chinese translations: TCAM (Ternary Content-Addressable Memory) is a hardware search engine; TL-TCAM is an improved hardware search engine of the invention.

In one embodiment, the table look-up type TL-TCAM hardware search engine comprises an SL decoder and a TL-TCAM array, wherein data stored in the TL-TCAM hardware search engine is obtained by looking up a table of data stored in a corresponding TCAM hardware search engine, the decoder is used for decoding search words and sending the search words into the TL-TCAM array, and the decoding is to convert the search words SL corresponding to the data in the TCAM hardware search engine table into search words LSL corresponding to the TL-TCAM hardware search engine table data.

In one scheme, data stored in a TL-TCAM hardware search engine is obtained by looking up a data table stored in a corresponding TCAM hardware search engine, and data of the TCAM hardware search engine is obtained by a data mapping mode stored in the TL-TCAM hardware search engine; therefore, the following scheme will specifically illustrate the data conversion mode between the TL-TCAM hardware search engine of the present invention and the existing TCAM hardware search engine:

each bit in the TCAM hardware search engine table (set to T-bit) is ternary, and can be 0,1, X. In terms of circuit implementation, it is actually composed of 2-bit SRAM, i.e., T-bit (SRAM1, SRAM2), e.g., 0 ═ 0,1 ═ 1, (1,0), and X ═ 0, 0.

The TL-TCAM hardware search engine divides the TCAM table equally, one packet (T _ block) per 2T-bit groups in each word circuit (one row is called a word circuit), see fig. 11, which needs to be described: here each bit T-bit is ternary.

FIG. 11 illustrates the manner in which a TCAM hardware search engine's tables are partitioned. Each 2T-bit bits in the word circuit constitutes a packet T _ block. T-bit is ternary, i.e. T-bit ═ SRAM1, SRAM 2.

Each T-block is then transformed into a TL-block of TL-TCAM, see fig. 12. It should be noted that: here each bit B-bit is binary.

FIG. 12 shows the composition of a table of a TL-TCAM hardware search engine. Each block TL _ block is 1 row by 4 columns in size, where the B-bit is binary. The T _ block and TL _ block storage capacities are therefore the same.

The main operation of the conversion is as follows:

for each packet T _ block, the following operations are performed:

performing table lookup operation in a packet T _ block by 00, taking a result of whether the packet T _ block is hit or not as a value of a first binary bit B-bit in the corresponding packet TL _ block, and recording the value as B-bit [1], "hit" time when B-bit [1] ═ 1, otherwise, B-bit [1] ═ 0;

performing table lookup operation on 01 in the packet T _ block, taking a result of whether the packet T _ block is hit or not as the value of a second binary bit B-bit in the corresponding packet TL _ block, and recording the value as B-bit [2], (B-bit [2] ═ 1 when the packet T _ block is hit), or else, setting B-bit [2] ═ 0;

performing table lookup operation in the packet T _ block by using 10, taking a result of whether the packet T _ block is hit or not as a value of a third binary bit B-bit in the corresponding packet TL _ block, and recording the value as B-bit [3], "hit" time when the packet T _ block is hit, B-bit [3] ═ 1, otherwise, B-bit [3] ═ 0;

and (3) performing table lookup operation in the packet T _ block by using 11, taking the result of whether the packet T _ block is hit or not as the value of a fourth binary bit B-bit in the corresponding packet TL _ block, and recording the value as B-bit [4], "hit" is that B-bit [4] ═ 1, and otherwise, B-bit [4] ═ 0.

The TCAM to TL-TCAM conversion pseudo-code is described as follows:

it should be noted that: since one bit of the TCAM is actually composed of 2-bit SRAM, the TCAM to TL-TCAM conversion does not cause any additional bit increase, i.e., no additional area increase.

Conversely, data in the table of the TL-TCAM hardware search engine can also be converted to data in the table of the TCAM hardware search engine.

The main process of conversion is as follows:

for each packet TL _ block the following is performed:

two data a and B are generated, a being the or of the first and second columns and B being the or of the third and fourth columns "

If { a, B } ═ 11; the value T-bit [1] ═ X in the first column of the TCAM table;

if { a, B } ═ 10; the value T-bit [1] of the first column of the TCAM table is 0;

if { a, B } ═ 01; the value T-bit [1] in the first column of the TCAM table is 1;

two data M and N are generated again, where M is an or of the first and third columns, and N is an or of the second and fourth columns.

If { M, N } ═ 11; the value T-bit [2] ═ X in the second column of the TCAM table;

if { M, N } ═ 10; the value T-bit [2] of the second column of the TCAM table is 0;

if { M, N } ═ 01; the value T-bit [2] in the second column of the TCAM table is 1.

The conversion pseudo-code for data conversion in the TL-TCAM to TCAM table is described as follows:

FIG. 5 shows an example of data conversion between different hardware search engines.

In one embodiment, the circuit of the look-up table type TL-TCAM hardware search engine is shown in FIG. 6, because the TL-TCAM hardware search engine is converted from a TCAM hardware search engine, the search word SL fed into the TL-TCAM array (TL-TCAM array) needs to be decoded. For a TCAM hardware search engine packet T _ block, the search line SL is decoded every 2 bits.

The TL-TCAM array mainly comprises word circuits of TL-TCAM hardware search engines, each word circuit is mainly formed by connecting a plurality of NOR type TL-TCAM hardware search engine units NORTL-Tcell on a matched line ML in parallel or by connecting a plurality of NAND type TL-TCAM hardware search engine units NANDTL-Tcell in series, and the TL-Tcell is connected with a decoder by a search data line and a global shielding line.

In one embodiment, the functional pseudo-code for an SL decoder (SL decoder) is described as follows:

the description for the decoder is as follows:

(1) when SL [2n:2n +1] is two global X (global X), i.e. { XX }, the search data lines LSL _00, LSL _01, LSL _10, LSL _11 are all 0, and the global shield lines GLX and GLX _ h are all 1;

(2) when SL [2n:2n +1] has only one global X (i.e., {0X }, {1X }, { X0}, and { X1}), global shielding lines GLX and GLX _ h are both 0, and search data lines LSL _00, LSL _01, LSL _10, and LSL _11 are shown in truth table 4:

table 4: LSL decoding truth table when SL [2n:2n +1] has only one global X

SL[2n:2n+1]	LSL_00	LSL_11	LSL_10	LSL_01
					0X
	1			1
					1X		1	1
X0	1		1
					X1		1		1

(3) When SL [2n:2n +1] has no global X:

the global shielding lines GLX and GLX _ h are both 0; when SL [2n:2n +1] ═ 00, search data line LSL _00= 1; when SL [2n:2n +1] ═ 01, search data line LSL _01 ═ 1; when SL [2n:2n +1] ═ 10, search data line LSL _10 ═ 1; when SL [2n:2n +1] is equal to 11, the search data line LSL _11 is equal to 1.

For a TL-TCAM array (TL-TCAM array) unit circuit, NOR type and NAND type can be divided according to the structure.

The TL-TCAM array is mainly composed of TL-TCAM hardware search engine word circuits (TL-TCAM word) (FIG. 9), and for NOR type cell circuits, each word circuit is composed of many TL-TCAM hardware search engine cells (TL-Tcell) connected in parallel on a matchline ML. M is a storage unit B-bit of TL-TCAM, and M # represents the logical negation of M. M ═ 1 indicates a match, and M ═ 0 indicates a mismatch. As shown in fig. 7, the NOR TL-Tcell includes inverters T1 to T8, NMOS transistors M1 to M4, NMOS transistors N1 to N4, search data lines LSL _00, LSL _01, LSL _10, LSL _11, global mask lines GLX, GLX _ h, local match lines LML, LMR, and global match lines ML;

the input end of the inverter T1 is connected with the output end of the inverter T2 to be used as a data storage end M [1] of the B-bit [1], the output end of the inverter T1 is connected with the input end of the inverter T2 to be used as a data storage end M [1] #oflogic 'NOT' of the B-bit [1], and the end M # is the logic 'NOT' of the end M; the source of MOS tube M1 is connected with M [1] # end, the grid of MOS tube M1 is connected with search data line LSL _00, the drain of MOS tube M1 is connected with local match line LML;

the input end of inverter T3 is connected with the output end of inverter T4 as the data storage end M2 of B-bit 2, the output end of inverter T3 is connected with the input end of inverter T4 as the data storage end M2 # of the logical negation of B-bit 2, the end M2 # is the logical negation of the end M2, the drain of MOS tube M2 is connected with the end M2 #, the grid of MOS tube M2 is connected with the search data line LSL _01, the source of MOS tube M2 is connected with local match line LMR;

the input end of inverter T5 is connected with the output end of inverter T6 as the data storage end M [3] of B-bit [3], the output end of inverter T5 is connected with the input end of inverter T6 as the data storage end M [3] #oflogic 'NOT' of B-bit [3], M [3] # is the logic 'NOT' of M [3], the source of MOS tube M3 is connected with the end M [3] # and the grid of MOS tube M3 is connected with the search data line LSL _10, the drain of MOS tube M3 is connected with the local match line LMR;

the input end of inverter T7 is connected with the output end of inverter T8 as the data storage end M [4] of B-bit [4], the output end of inverter T7 is connected with the input end of inverter T8 as the data storage end M [4] #oflogic "NOT" of B-bit [4], M [4] # is the logic "NOT" of M [4], the drain of MOS tube M4 is connected with the end M [4] #, the grid of MOS tube M4 is connected with the search data line LSL _11, the source of MOS tube M4 is connected with local matchline LML;

the grid electrode of the MOS tube N1 is connected with a global shielding line GLX, the source electrode of the MOS tube N1 is grounded, and the drain electrode of the MOS tube N1 is connected with a match line LMR; the grid electrode of the MOS tube N3 is connected to a global shielding line GLX _ h, the source electrode of the MOS tube N3 is connected to a local matching line LMR, and the drain electrode of the MOS tube N3 is connected to a local matching line LML; the grid electrode of the MOS tube N2 is connected to a local match line LMR, and the source electrode of the MOS tube N2 is grounded; the gate of MOS transistor N4 is connected to local match line LML, the source of MOS transistor N4 is connected to the drain of MOS transistor N2, and the drain of MOS transistor N4 is connected to global match line ML.

The working principle of the NOR type unit circuit is as follows:

A. SL [2n:2n +1] has no global X:

global shielding line GLX is 0, GLX _ h is 1, NMOS transistor N1 is turned off, NMOS transistor N3 is turned on, and local match line LML and LMR are equal in potential;

according to the SL decoder, only one of the search data lines LSL _00, LSL _01, LSL _10 and LSL _11 is 1, and the corresponding M # (namely 'negation' of B-bit) is sent out; for example, SL [2n:2n +1] ═ {0,0}, LSL _00 ═ 1, M1 is turned on, and the "not" value of B-bit [1] is sent to LML.

If the sent M # -0 (M ═ 1), the local match line LML ═ 0, LMR ═ 0, NMOS tubes N2 and N4 are closed, the search result of TL-Tcell is a match, if the results of all TL-Tcell cells in the word circuit are a match, the whole word circuit gives the matched search result, and since the NMOS tubes N2, N4 of all TL-Tcell cells are closed, all discharge channels of the global match line ML are closed at this time; if the sent M # -1 (M ═ 0), the local match line LML ═ 1, LMR ═ 1, the NMOS tubes N2 and N4 are opened, the search result of the TL-Tcell cell is a mismatch, if the result of at least one of the TL-Tcell in the word circuit is a mismatch, the whole word circuit gives the search result of the mismatch, and since the NMOS tubes N2 and N4 of at least one TL-Tcell cell are simultaneously opened, at least one discharge channel of the global match line ML is opened at this time;

B. SL [2n:2n +1] has a global X:

as can be seen from the decoder, the global mask line GLX is 0, GLX _ h is 0, the NMOS transistors N1 and N3 are both turned off, and the local match lines LML and LMR have their own potentials; meanwhile, as can be seen from table 7, one of the search data lines LSL _00 and LSL _11 must be selected, and one of the search data lines LSL _01 and LSL _10 must be selected, one of the NMOS transistors M1 and M4 must be turned on, and one of the NMOS transistors M2 and M3 must be turned on; for example, if SL [2N:2N +1] = {0, X }, LSL _00 and LSL _01 are selected (1), M1 and M2 are turned on, a value of B-bit [1] # is selected to LML, a value of B-bit [2] # is selected to LMR, at least one of NMOS transistors N2 and N4 is turned off when at least one of local match lines LML and LMR is 0, a global match line ML pull-down channel is turned off, and a cell comparison result is a match; only when the local match lines LML and LMR are both 1, the NMOS tubes N2 and N4 are opened simultaneously, the pull-down channel of the global match line ML is opened, and the unit comparison result is mismatching;

C. SL [2n:2n +1] has two global Xs:

as known by the decoder, the search data lines LSL _00, LSL _01, LSL _10 and LSL _11 are all 0, and the NMOS transistors M1, M2, M3 and M4 are all closed; the global shielding line GLX is 1, GLX _ h is 1, the NMOS transistors N1 and N3 are both turned on, and the local match lines LML and LMR are both 0; at this time, both N2 and N4 are turned off, the global match line ML pull-down channel is turned off, and the cell comparison result is a match.

The NAND-type TL-TCAM array is mainly composed of NAND-type TL-TCAM hardware search engine word circuits (NAND TL-TCAM word) as shown in fig. 10, and for the NAND-type cell circuits, each word circuit is composed of many TL-TCAM hardware search engine cells (TL-Tcell) connected in series. M is a storage unit B-bit of TL-TCAM, and M # represents the logical negation of M. M ═ 1 indicates a match, and M ═ 0 indicates a mismatch. As shown in fig. 8, the NAND TL-Tcell includes inverters T1 to T8, NMOS transistors M1 to M4, NMOS transistors N1 to N4, search data lines LSL _00, LSL _01, LSL _10, LSL _11, global mask lines GLX, GLX _ h, local match lines LML, LMR, and global match lines ML _ L, ML _ R;

the input end of the inverter T1 is connected with the output end of the inverter T2 to be used as a data storage end M [1] of the B-bit [1], the output end of the inverter T1 is connected with the input end of the inverter T2 to be used as a data storage end M [1] #oflogic 'NOT' of the B-bit [1], and the end M # is the logic 'NOT' of the end M; the source of MOS transistor M1 is connected to M1 end, the grid of MOS transistor M1 is connected to search data line LSL _00, the drain of MOS transistor M1 is connected to local match line LML;

the input end of inverter T3 is connected with the output end of inverter T4 as the data storage end M2 of B-bit 2, the output end of inverter T3 is connected with the input end of inverter T4 as the data storage end M2 # of the logical negation of B-bit 2, the end M2 # is the logical negation of M2, the drain of MOS tube M2 is connected with the end M2, the grid of MOS tube M2 is connected with the search data line LSL-01, the source of MOS tube M2 is connected with local match line LMR;

the input end of inverter T5 is connected with the output end of inverter T6 as the data storage end M [3] of B-bit [3], the output end of inverter T5 is connected with the input end of inverter T6 as the data storage end M [3] #oflogic 'NOT' of B-bit [3], M [3] # is the logic 'NOT' of M [3], the source of MOS tube M3 is connected with the end M [3], the grid of MOS tube M3 is connected with the search data line LSL _10, the drain of MOS tube M3 is connected with the local match line LMR;

the input end of inverter T7 is connected with the output end of inverter T8 as the data storage end M [4] of B-bit [4], the output end of inverter T7 is connected with the input end of inverter T8 as the data storage end M [4] #oflogic 'NOT' of B-bit [4], M [4] # is the logic 'NOT' of M [4], the drain of MOS tube M4 is connected with the end M [4], the grid of MOS tube M4 is connected with the search data line LSL _11, the source of MOS tube M4 is connected with the local match line LML;

the grid electrode of the MOS tube N1 is connected with a global shielding line GLX, the source electrode of the MOS tube N1 is connected with a power supply, and the drain electrode of the MOS tube N1 is connected with a local matching line LMR; the grid electrode of the MOS tube N3 is connected to a global shielding line GLX _ h, the source electrode of the MOS tube N3 is connected to a matching line LMR, and the drain electrode of the MOS tube N3 is connected to a matching line LML; the gate of the MOS transistor N2 is connected to a match line LMR, the gate of the MOS transistor N4 is connected to a local match line LML, the drains of the MOS transistors N2 and N4 are connected, the sources of the MOS transistors N2 and N4 are connected, the global match line ML _ L is connected to the drains of the MOS transistors N2 and N4, and the global match line ML _ R is connected to the sources of the MOS transistors N2 and N4.

The working principle of the NAND type unit circuit is as follows:

A. SL [2n:2n +1] has no global X:

global shielding line GLX is 0, GLX _ h is 1, NMOS transistor N1 is turned off, N3 is turned on, and local match line LML and LMR are equal in potential;

only one of the search data lines LSL _00, LSL _01, LSL _10 and LSL _11 is 1, and the corresponding M is sent out;

if the sent M is 1, the local matching line LML is 1, the local matching line LMR is 1, the NMOS tubes N2 and N4 are both opened, the search result of the TL-Tcell unit is matched, and if the results of all the TL-Tcell units in the word circuit are matched, the whole word circuit gives a matched search result; if M is 0, the local match line LML is 0, LMR is 0, the NMOS transistors N2 and N4 are both turned off, the search result of the TL-Tcell cell is a mismatch, and if the result of at least one of all TL-Tcell cells in the word circuit is a mismatch, the entire word circuit gives the search result of the mismatch.

B. SL [2n:2n +1] has a global X:

as can be seen from the decoder, the global mask line GLX is 0, GLX _ h is 0, the NMOS transistors N1 and N3 are both turned off, and the local match lines LML and LMR have their own potentials; meanwhile, one of the search data lines LSL _00 and LSL _11 must be selected, and one of the search data lines LSL _01 and LSL _10 must be selected, one of the NMOS transistors M1 and M4 must be turned on, and one of the NMOS transistors M2 and M3 must be turned on; when at least one of the local match lines LML and LMR is 1, at least one of the NMOS tubes N2 and N4 is opened, and the unit comparison result is matching; only when the local match lines LML and LMR are both 0, the NMOS tubes N2 and N4 are closed simultaneously, and the unit comparison result is mismatch;

C. SL [2n:2n +1] has two global Xs:

as known by the decoder, the search data lines LSL _00, LSL _01, LSL _10 and LSL _11 are all 0, and the NMOS transistors M1, M2, M3 and M4 are all closed; the global shielding line GLX is 1, GLX _ h is 1, the NMOS transistors N1 and N3 are both turned on, and the local matching lines LML and LMR are both 1; at this time, the NMOS transistors N2 and N4 are both turned on, and the cell comparison result is a match.

In the above embodiments, the circuit structures of the cell circuit Tcell of the conventional TCAM hardware search engine of fig. 4 and the cell circuit TL-Tcell of the TL-TCAM hardware search engine proposed by the present invention are compared. First, the search line power consumption is reduced. Tcell is a 1-bit TCAM cell, while a TL-Tcell is equivalent to a 2-bit Tcell. Since the probability of occurrence of global X is low, we only consider power consumption without global X here. Since SL ═ SL, SL # }, SL # is a strict logical "not" of SL, such as SL ═ 0,1, SL ═ 1, 0. The probabilities of 0 and 1 being equal for each clock cycle SL, i.e., there is a flip of either 0,1 to 1,0 or 1,0 to 0,1 for each cycle, as calculated by the average probability. Current is drawn from the power supply at 0 to 1, which corresponds to one SL line per 1 Tcell per cycle. In the TL-TCAM hardware search engine provided by the invention, only one line LSL is selected in each TL-Tcell in each period. Since one TL-Tcell is equivalent to 2 tcells, it can be equivalently considered that one line is turned over to consume power every 2 tcells per cycle of the original hardware search engine. Therefore, ideally, the power consumption of the search line SL is reduced by half. Second, match line parasitic capacitance is reduced. As can be seen from the data conversion part of the table look-up type TL-TCAM hardware search engine and the traditional TCAM hardware search engine, the storage bit of the TL-TCAM hardware search engine is not increased and is consistent with the original TCAM hardware search engine. For the present invention, in an ideal case, the ML parasitic capacitance is halved, the power consumption is halved, and the speed is doubled, for the following reasons: A. NOR type architecture. Since TL-Tcell is equivalent to a 2bit Tcell, the Tcell of FIG. 1(a) has a pipe (M1) directly connected to the ML. While TL-Tcell in fig. 7, corresponds to one pipe (N4) directly connected to ML for every two Tcell. Therefore, the parasitic capacitance is halved, the power consumption is halved, and the speed is doubled. B. Compared with the structure (b) in fig. 1, the NAND-type TL-Tcell is equivalent to that one transmission gate N2/N4 is provided for every 2 Tcell, so that parasitic capacitance is halved, power consumption is reduced, speed is increased by at least one time, and since speed is increased in a serial connection manner in a nonlinear manner, actual speed can be even increased by more than one time.

Claims (8)

1. A table look-up type TL-TCAM hardware search engine is characterized by comprising an SL decoder and a TL-TCAM array, wherein data stored in the TL-TCAM hardware search engine is obtained by looking up a table from data stored in a corresponding TCAM hardware search engine based on the following modes: grouping every two ternary bits in a TCAM hardware search engine word circuit, wherein each group is marked as T _ block, the group T _ block is mapped into a corresponding group TL _ block in a TL-TCAM hardware search engine, each group TL _ block consists of four binary bits, and converting each group T _ block into a corresponding group TL _ block through table look-up operation:

for each packet T _ block, the following operations are performed:

performing table lookup operation in the T _ block by 00, taking a hit result as the value of a first binary bit B-bit in the corresponding TL _ block, recording the value as B-bit [1], wherein the B-bit [1] =1 during hitting, and otherwise, the B-bit [1] =0;

performing table lookup operation on the group T _ block by using 01, taking a hit result as the value of a second binary bit B-bit in the corresponding group TL _ block, recording the value as B-bit [2], wherein the B-bit [2] =1 during hitting, and otherwise, the B-bit [2] =0;

performing table lookup operation in the T _ block by using a table lookup operation unit 10, taking a hit result as the value of a third binary bit B-bit in the corresponding TL _ block, recording the value as B-bit [3], wherein the B-bit [3] =1 in hit, and otherwise, the B-bit [3] =0;

performing table lookup operation in the T _ block group by using 11, taking a hit result as the value of a fourth binary bit B-bit in the corresponding TL _ block group, recording the value as B-bit [4], wherein the B-bit [4] =1 in hit, and otherwise, the B-bit [4] =0;

the decoder is used for decoding the search words and sending the search words into a TL-TCAM array of a TL-TCAM hardware search engine, wherein the decoding is to convert the search words SL corresponding to the data in the TCAM hardware search engine table into the search words LSL corresponding to the data in the TL-TCAM hardware search engine table;

the TL-TCAM array mainly comprises word circuits of TL-TCAM hardware search engines, each word circuit mainly comprises a plurality of NOR-type TL-TCAM hardware search engine units NORTL-Tcell connected in parallel on a matched line ML, and each NOR TL-Tcell comprises inverters T1-T8, NMOS tubes M1-M4, NMOS tubes N1-N4, search data lines LSL _00, LSL _01, LSL _10, LSL _11, a global shielding line GLX, GLX _ h, a local matched line LML, LMR and a global matched line ML; the input end of inverter T1 is connected to the output end of inverter T2 to be the data storage end M [1] of B-bit [1], the output end of inverter T1 is connected to the input end of inverter T2 to be the data storage end M [1] #oflogic "NOT" of B-bit [1], the end M [1] # is the logic "NOT" of M [1 ]; the source of MOS tube M1 is connected with M [1] # end, the grid of MOS tube M1 is connected with search data line LSL _00, the drain of MOS tube M1 is connected with local match line LML; the input end of inverter T3 is connected with the output end of inverter T4 as the data storage end M2 of B-bit 2, the output end of inverter T3 is connected with the input end of inverter T4 as the data storage end M2 # of the logical negation of B-bit 2, the end M2 # is the logical negation of the end M2, the drain of MOS tube M2 is connected with the end M2 #, the grid of MOS tube M2 is connected with the search data line LSL _01, the source of MOS tube M2 is connected with local match line LMR; the input end of inverter T5 is connected with the output end of inverter T6 as the data storage end M [3] of B-bit [3], the output end of inverter T5 is connected with the input end of inverter T6 as the data storage end M [3] #oflogic 'NOT' of B-bit [3], M [3] # is the logic 'NOT' of M [3], the source of MOS tube M3 is connected with the end M [3] # and the grid of MOS tube M3 is connected with the search data line LSL _10, the drain of MOS tube M3 is connected with the local match line LMR; the input end of inverter T7 is connected with the output end of inverter T8 as the data storage end M [4] of B-bit [4], the output end of inverter T7 is connected with the input end of inverter T8 as the data storage end M [4] #oflogic "NOT" of B-bit [4], M [4] # is the logic "NOT" of M [4], the drain of MOS tube M4 is connected with the end M [4] #, the grid of MOS tube M4 is connected with the search data line LSL _11, the source of MOS tube M4 is connected with local matchline LML; the grid electrode of the MOS tube N1 is connected with a global shielding line GLX, the source electrode of the MOS tube N1 is grounded, and the drain electrode of the MOS tube N1 is connected with a match line LMR; the grid electrode of the MOS tube N3 is connected to a global shielding line GLX _ h, the source electrode of the MOS tube N3 is connected to a local matching line LMR, and the drain electrode of the MOS tube N3 is connected to a local matching line LML; the grid electrode of the MOS tube N2 is connected to a local match line LMR, and the source electrode of the MOS tube N2 is grounded; the gate of MOS transistor N4 is connected to local match line LML, the source of MOS transistor N4 is connected to the drain of MOS transistor N2, and the drain of MOS transistor N4 is connected to global match line ML.

2. The table lookup TL-TCAM hardware search engine of claim 1, wherein the SL decoder performs decoding based on:

(1) when SL [2n:2n +1] is two global Xs, search data lines LSL _00, LSL _01, LSL _10, LSL _11 are all 0, and global shield lines GLX and GLX _ h are all 1;

(2) when SL [2n:2n +1] has only one global X, global shield lines GLX and GLX _ h are both 0, search data lines LSL _00, LSL _01, LSL _10, LSL _11 are in the following truth table:

SL[2n:2n+1] LSL_00 LSL_11 LSL_10 LSL_01 0X 1 1 1X 1 1 X0 1 1 X1 1 1

(3) when SL [2n:2n +1] has no global X:

the global shielding lines GLX and GLX _ h are both 0; when SL [2n:2n +1] =00, search for the data line LSL _00= 1; when SL [2n:2n +1] =01, search for the data line LSL _01= 1; when SL [2n:2n +1] =10, search for the data line LSL _10= 1; SL [2n:2n +1] =11, the data line LSL _11=1 is searched.

3. The lookup table TL-TCAM hardware search engine of claim 2, wherein the NOR TL-Tcell unit operates based on:

A. SL [2n:2n +1] has no global X:

global shielding line GLX =0, GLX _ h =1, NMOS transistor N1 is turned off, and NMOS transistor N3 is turned on, where the local match line LML and LMR are equal in potential;

only one of the search data lines LSL _00, LSL _01, LSL _10 and LSL _11 is 1, and the corresponding M # is sent out;

if the sent M # =0, the local match lines LML =0, LMR =0, the NMOS tubes N2 and N4 are closed, the search result of the TL-Tcell cell is a match, if the results of all TL-Tcell cells in the word circuit are a match, the entire word circuit gives a matched search result, and since the NMOS tubes N2 and N4 of all TL-Tcell cells are closed, all discharge channels of the global match line ML are closed at this time; if the sent M # =1, the local match line LML =1, LMR =1, NMOS tubes N2 and N4 are opened, the search result of the TL-Tcell cell is mismatch, if the result of at least one TL-Tcell cell in the word circuit is mismatch, the whole word circuit gives the search result of the mismatch, and at least one discharge channel of the global match line ML is opened at the moment because the NMOS tubes N2 and N4 of at least one TL-Tcell cell are opened simultaneously;

B. SL [2n:2n +1] has a global X:

as can be seen from the decoder, the global shielding line GLX =0, GLX _ h =0, the NMOS transistors N1 and N3 are both turned off, and the local match lines LML and LMR each have their own potential; meanwhile, one line of the LSL _00 and LSL _11 is selected, one line of the search data lines LSL _01 and LSL _10 is selected, one of the NMOS transistors M1 and M4 is opened, and one of the NMOS transistors M2 and M3 is opened;

when at least one of LML and LMR is 0, at least one of N2 and N4 is closed, the ML pull-down channel is closed, and the unit comparison result is matching; only when the LML and the LMR are both 1, N2 and N4 are opened simultaneously, the ML pull-down channel is opened, and the unit comparison result is mismatching;

C. SL [2n:2n +1] has two global Xs:

as known by the decoder, the search data lines LSL _00, LSL _01, LSL _10 and LSL _11 are all 0, and the NMOS transistors M1, M2, M3 and M4 are all closed; global shielding lines GLX =1, GLX _ h =1, NMOS transistors N1 and N3 are both open, and local match lines LML and LMR are both 0; at this time, both N2 and N4 are turned off, the global match line ML pull-down channel is turned off, and the cell comparison result is a match.

4. The table look-up TL-TCAM hardware search engine of claim 1, wherein the data of the TCAM hardware search engine is mapped from the data stored in the TL-TCAM hardware search engine based on: grouping every four binary bits in a TL-TCAM word circuit, wherein each group is marked as TL _ block, the group TL _ block is mapped into a corresponding group T _ block in TCAM, each group T _ block consists of two three-valued bits, and converting each group TL _ block into the corresponding group T _ block through table look-up operation:

for each packet TL _ block the following is performed:

two data a and B are generated, a = or of the first and second columns, B = or of the third and fourth columns;

if { a, B } = 11; the value T-bit [1] = X in the first column of the TCAM table;

if { a, B } = 10; the value T-bit [1] =0 in the first column of the TCAM table;

if { a, B } = 01; the value T-bit [1] =1 in the first column of the TCAM table;

two data M and N are generated again, M = or of the first and third columns, N = or of the second and fourth columns;

if { M, N } = 11; the value T-bit [2] = X in the second column of the TCAM table;

if { M, N } = 10; the value T-bit [2] =0 in the second column of the TCAM table;

if { M, N } = 01; the value T-bit [2] =1 in the second column of the TCAM table.

5. A table look-up type TL-TCAM hardware search engine is characterized by comprising an SL decoder and a TL-TCAM array, wherein data stored in the TL-TCAM hardware search engine is obtained by looking up a table from data stored in a corresponding TCAM hardware search engine based on the following modes: grouping every two ternary bits in a TCAM hardware search engine word circuit, wherein each group is marked as T _ block, the group T _ block is mapped into a corresponding group TL _ block in a TL-TCAM hardware search engine, each group TL _ block consists of four binary bits, and converting each group T _ block into a corresponding group TL _ block through table look-up operation:

for each packet T _ block, the following operations are performed:

performing table lookup operation in the T _ block by 00, taking a hit result as the value of a first binary bit B-bit in the corresponding TL _ block, recording the value as B-bit [1], wherein the B-bit [1] =1 during hitting, and otherwise, the B-bit [1] =0;

performing table lookup operation on the group T _ block by using 01, taking a hit result as the value of a second binary bit B-bit in the corresponding group TL _ block, recording the value as B-bit [2], wherein the B-bit [2] =1 during hitting, and otherwise, the B-bit [2] =0;

performing table lookup operation in the T _ block by using a table lookup operation unit 10, taking a hit result as the value of a third binary bit B-bit in the corresponding TL _ block, recording the value as B-bit [3], wherein the B-bit [3] =1 in hit, and otherwise, the B-bit [3] =0;

performing table lookup operation in the T _ block group by using 11, taking a hit result as the value of a fourth binary bit B-bit in the corresponding TL _ block group, recording the value as B-bit [4], wherein the B-bit [4] =1 in hit, and otherwise, the B-bit [4] =0;

the decoder is used for decoding the search words and sending the search words into a TL-TCAM array of a TL-TCAM hardware search engine, wherein the decoding is to convert the search words SL corresponding to the data in the TCAM hardware search engine table into the search words LSL corresponding to the data in the TL-TCAM hardware search engine table;

the TL-TCAM array is mainly formed by connecting a plurality of NAND type TL-TCAM hardware search engine units NANDTL-Tcell in series, and the TL-Tcell is connected with a decoder by a search data line and a global shielding line; the NAND TL-Tcell comprises inverters T1-T8, NMOS tubes M1-M4, NMOS tubes N1-N4, search data lines LSL _00, LSL _01, LSL _10, LSL _11, global shielding lines GLX, GLX _ h, local matching lines LML, LMR and global matching lines ML _ L, ML _ R; the input end of inverter T1 is connected to the output end of inverter T2 to be the data storage end M [1] of B-bit [1], the output end of inverter T1 is connected to the input end of inverter T2 to be the data storage end M [1] #oflogic "NOT" of B-bit [1], the end M [1] # is the logic "NOT" of M [1 ]; the source of MOS transistor M1 is connected to M1 end, the grid of MOS transistor M1 is connected to search data line LSL _00, the drain of MOS transistor M1 is connected to local match line LML; the input end of inverter T3 is connected with the output end of inverter T4 as the data storage end M2 of B-bit 2, the output end of inverter T3 is connected with the input end of inverter T4 as the data storage end M2 # of the logical negation of B-bit 2, the end M2 # is the logical negation of M2, the drain of MOS tube M2 is connected with the end M2, the grid of MOS tube M2 is connected with the search data line LSL-01, the source of MOS tube M2 is connected with local match line LMR; the input end of inverter T5 is connected with the output end of inverter T6 as the data storage end M [3] of B-bit [3], the output end of inverter T5 is connected with the input end of inverter T6 as the data storage end M [3] #oflogic 'NOT' of B-bit [3], M [3] # is the logic 'NOT' of M [3], the source of MOS tube M3 is connected with the end M [3], the grid of MOS tube M3 is connected with the search data line LSL _10, the drain of MOS tube M3 is connected with the local match line LMR; the input end of inverter T7 is connected with the output end of inverter T8 as the data storage end M [4] of B-bit [4], the output end of inverter T7 is connected with the input end of inverter T8 as the data storage end M [4] #oflogic 'NOT' of B-bit [4], M [4] # is the logic 'NOT' of M [4], the drain of MOS tube M4 is connected with the end M [4], the grid of MOS tube M4 is connected with the search data line LSL _11, the source of MOS tube M4 is connected with the local match line LML; the grid electrode of the MOS tube N1 is connected with a global shielding line GLX, the source electrode of the MOS tube N1 is connected with a power supply, and the drain electrode of the MOS tube N1 is connected with a local matching line LMR; the grid electrode of the MOS tube N3 is connected to a global shielding line GLX _ h, the source electrode of the MOS tube N3 is connected to a matching line LMR, and the drain electrode of the MOS tube N3 is connected to a matching line LML; the gate of the MOS transistor N2 is connected to a match line LMR, the gate of the MOS transistor N4 is connected to a local match line LML, the drains of the MOS transistors N2 and N4 are connected, the sources of the MOS transistors N2 and N4 are connected, the global match line ML _ L is connected to the drains of the MOS transistors N2 and N4, and the global match line ML _ R is connected to the sources of the MOS transistors N2 and N4.

6. The hardware search engine of claim 5, wherein the SL decoder performs decoding based on:

(1) when SL [2n:2n +1] is two global Xs, search data lines LSL _00, LSL _01, LSL _10, LSL _11 are all 0, and global shield lines GLX and GLX _ h are all 1;

(2) when SL [2n:2n +1] has only one global X, global shield lines GLX and GLX _ h are both 0, search data lines LSL _00, LSL _01, LSL _10, LSL _11 are in the following truth table:

SL[2n:2n+1] LSL_00 LSL_11 LSL_10 LSL_01 0X 1 1 1X 1 1 X0 1 1 X1 1 1

(3) when SL [2n:2n +1] has no global X:

the global shielding lines GLX and GLX _ h are both 0; when SL [2n:2n +1] =00, search for the data line LSL _00= 1; when SL [2n:2n +1] =01, search for the data line LSL _01= 1; when SL [2n:2n +1] =10, search for the data line LSL _10= 1; SL [2n:2n +1] =11, the data line LSL _11=1 is searched.

7. The lookup table TL-TCAM hardware search engine of claim 6, wherein the NAND TL-Tcell unit operates based on:

A. SL [2n:2n +1] has no global X:

global shielding lines GLX =0, GLX _ h =1, an NMOS tube N1 is closed, an NMOS tube N3 is opened, and the potentials of a local matching line LML and a local matching line LMR are equal;

only one of the search data lines LSL _00, LSL _01, LSL _10 and LSL _11 is 1, and the corresponding M is sent out;

if M =1 is sent, the local match lines LML =1, LMR =1, NMOS transistors N2 and N4 are both turned on, the search result of the TL-Tcell cell is a match, and if the results of all TL-Tcell in the word circuit are a match, the entire word circuit gives a matched search result; if the sent M =0, the local match line LML =0, LMR =0, the NMOS transistors N2 and N4 are closed, the search result of the TL-Tcell is mismatch, if the result of at least one of the TL-Tcell in the word circuit is mismatch, the whole word circuit gives the search result of the mismatch;

B. SL [2n:2n +1] has a global X:

as can be seen from the decoder, the global shielding line GLX =0, GLX _ h =0, the NMOS transistors N1 and N3 are both turned off, and the local match lines LML and LMR each have their own potential; meanwhile, one of the search data lines LSL _00 and LSL _11 must be selected, and one of the search data lines LSL _01 and LSL _10 must be selected, one of the NMOS transistors M1 and M4 must be turned on, and one of the NMOS transistors M2 and M3 must be turned on; when at least one of the local match lines LML and LMR is 1, at least one of the NMOS tubes N2 and N4 is opened, and the unit comparison result is matching; only when the local match lines LML and LMR are both 0, the NMOS tubes N2 and N4 are closed simultaneously, and the unit comparison result is mismatch;

C. SL [2n:2n +1] has two global Xs:

as known by the decoder, the search data lines LSL _00, LSL _01, LSL _10 and LSL _11 are all 0, and the NMOS transistors M1, M2, M3 and M4 are all closed; global shielding lines GLX =1, GLX _ h =1, NMOS transistors N1 and N3 are both open, and local match lines LML and LMR are both 1; at this time, the NMOS transistors N2 and N4 are both turned on, and the cell comparison result is a match.

8. The table look-up TL-TCAM hardware search engine of claim 5, wherein the data of the TCAM hardware search engine is mapped from the data stored in the TL-TCAM hardware search engine based on: grouping every four binary bits in a TL-TCAM word circuit, wherein each group is marked as TL _ block, the group TL _ block is mapped into a corresponding group T _ block in TCAM, each group T _ block consists of two three-valued bits, and converting each group TL _ block into the corresponding group T _ block through table look-up operation:

for each packet TL _ block the following is performed:

two data a and B are generated, a = or of the first and second columns, B = or of the third and fourth columns;

if { a, B } = 11; the value T-bit [1] = X in the first column of the TCAM table;

if { a, B } = 10; the value T-bit [1] =0 in the first column of the TCAM table;

if { a, B } = 01; the value T-bit [1] =1 in the first column of the TCAM table;

two data M and N are generated again, M = or of the first and third columns, N = or of the second and fourth columns;

if { M, N } = 11; the value T-bit [2] = X in the second column of the TCAM table;

if { M, N } = 10; the value T-bit [2] =0 in the second column of the TCAM table;

if { M, N } = 01; the value T-bit [2] =1 in the second column of the TCAM table.

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